74LVC1G332GW-Q100 [NEXPERIA]

3-input OR gate;
74LVC1G332GW-Q100
型号: 74LVC1G332GW-Q100
厂家: Nexperia    Nexperia
描述:

3-input OR gate

光电二极管 逻辑集成电路
文件: 总11页 (文件大小:198K)
中文:  中文翻译
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74LVC1G332-Q100  
3-input OR gate  
Rev. 3 — 21 August 2018  
Product data sheet  
1. General description  
The 74LVC1G332-Q100 provides one 3-input OR function.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices  
as translators in mixed 3.3 V and 5 V applications.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.  
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it is  
powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature  
range  
Name  
Description  
Version  
74LVC1G332GW-Q100 -40 °C to +125 °C SC-88  
74LVC1G332GV-Q100 -40 °C to +125 °C SC-74  
plastic surface-mounted package; 6 leads  
SOT363  
plastic surface-mounted package (TSOP6); 6 leads SOT457  
 
 
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
4. Marking  
Table 2. Marking  
Type number  
Marking code[1]  
74LVC1G332GW-Q100  
74LVC1G332GV-Q100  
YG  
YG  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
5. Functional diagram  
B
3
1
6
B
A
C
1
3
6
4
Y
Y
A
C
1
4
001aad933  
001aad934  
001aad935  
Fig. 1. Logic symbol  
Fig. 2. IEC logic symbol  
Fig. 3. Logic diagram  
6. Pinning information  
6.1. Pinning  
74LVC1G332-Q100  
1
2
3
6
5
4
A
GND  
B
C
V
Y
CC  
aaa-012462  
Fig. 4. Pin configuration SOT363 (SC-88) and SOT457 (SC-74)  
6.2. Pin description  
Table 3. Pin description  
Symbol  
Pin  
1
Description  
data input  
A
GND  
B
2
ground (0 V)  
data input  
3
Y
4
data output  
supply voltage  
data input  
VCC  
C
5
6
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
2 / 11  
 
 
 
 
 
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
7. Functional description  
Table 4. Function table  
H = HIGH voltage level; L = LOW voltage level; X = don’t care.  
Input  
Output  
A
H
X
X
L
B
X
H
X
L
C
X
X
H
L
Y
H
H
H
L
8. Limiting values  
Table 5. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
-0.5  
-50  
-0.5  
-
Max  
+6.5  
-
Unit  
V
VCC  
IIK  
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
VI  
[1]  
+6.5  
±50  
IOK  
VO  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
Active mode  
mA  
V
[1]  
[1]  
-0.5  
-0.5  
-
VCC + 0.5  
+6.5  
±50  
Power-down mode; VCC = 0 V  
VO = 0 V to VCC  
V
IO  
output current  
mA  
mA  
mA  
mW  
°C  
ICC  
IGND  
Ptot  
Tstg  
supply current  
-
100  
ground current  
-100  
-
-
total power dissipation  
storage temperature  
Tamb = -40 °C to +125 °C  
[2]  
250  
-65  
+150  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] For SC-88 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.  
9. Recommended operating conditions  
Table 6. Recommended operating conditions  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
5.5  
Unit  
V
VCC  
VI  
supply voltage  
input voltage  
output voltage  
1.65  
-
-
-
-
-
-
-
0
0
5.5  
V
VO  
Active mode  
VCC  
5.5  
V
VCC = 0 V; Power-down mode  
0
V
Tamb  
ambient temperature  
-40  
-
+125  
20  
°C  
ns/V  
ns/V  
Δt/ΔV  
input transition rise and fall rate  
VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 5.5 V  
-
10  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
3 / 11  
 
 
 
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
10. Static characteristics  
Table 7. Static characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
Typ[1]  
-40 °C to +125 °C Unit  
Min  
Max  
Min  
Max  
VIH  
HIGH-level input VCC = 1.65 V to 1.95 V  
0.65VCC  
-
-
-
-
-
-
-
-
-
0.65VCC  
-
V
V
V
V
V
V
V
V
voltage  
VCC = 2.3 V to 2.7 V  
1.7  
-
1.7  
-
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
2.0  
-
-
2.0  
-
-
0.7VCC  
0.7VCC  
VIL  
LOW-level input VCC = 1.65 V to 1.95 V  
-
-
-
-
0.35VCC  
0.7  
-
-
-
-
0.35VCC  
0.7  
voltage  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
0.8  
0.8  
0.3VCC  
0.3VCC  
VOH  
HIGH-level output VI = VIH or VIL  
voltage  
IO = -100 μA;  
VCC - 0.1  
-
-
VCC - 0.1  
-
V
VCC = 1.65 V to 5.5 V  
IO = -4 mA; VCC = 1.65 V  
1.2  
1.9  
2.2  
2.3  
3.8  
-
-
-
-
-
-
-
-
-
-
0.95  
1.7  
1.9  
2.0  
3.4  
-
-
-
-
-
V
V
V
V
V
IO = -8 mA; VCC = 2.3 V  
IO = -12 mA; VCC = 2.7 V  
IO = -24 mA; VCC = 3.0 V  
IO = -32 mA; VCC = 4.5 V  
VOL  
LOW-level output VI = VIH or VIL  
voltage  
IO = 100 μA;  
-
-
0.1  
-
0.1  
V
VCC = 1.65 V to 5.5 V  
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
IO = 32 mA; VCC = 4.5 V  
-
-
-
-
-
-
-
0.45  
0.3  
-
-
-
-
-
-
0.70  
0.45  
0.60  
0.80  
0.80  
±1  
V
-
V
-
0.4  
V
-
-
0.55  
0.55  
±1  
V
V
II  
input leakage  
current  
VCC = 0 V to 5.5 V;  
VI = 5.5 V or GND  
±0.1  
μA  
IOFF  
ICC  
ΔICC  
CI  
power-off leakage VCC = 0 V; VI or VO = 5.5 V  
current  
-
-
-
-
±0.1  
0.1  
5
±2  
4
-
-
-
-
±2  
4
μA  
μA  
μA  
pF  
supply current  
VCC = 1.65 V to 5.5 V;  
VI = VCC or GND; IO = 0 A  
additional supply per pin; VCC = 2.3 V to 5.5 V;  
current VI = VCC - 0.6 V; IO = 0 A  
500  
-
500  
-
input capacitance VCC = 3.3 V; VI = GND to VCC  
3
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
4 / 11  
 
 
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
11. Dynamic characteristics  
Table 8. Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6.  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
-40 °C to +125 °C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
tpd  
propagation delay A, B and C to Y; see Fig. 5  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
[2]  
1.5  
1.0  
1.0  
1.0  
1.0  
-
4.7  
3.0  
3.0  
2.6  
1.9  
12  
17.2  
6.2  
6.0  
4.8  
3.5  
-
1.5  
1.0  
1.0  
1.0  
1.0  
-
21.5  
7.8  
7.5  
6.2  
4.4  
-
ns  
ns  
ns  
ns  
ns  
pF  
VCC = 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
CPD  
power dissipation VI = GND to VCC; VCC = 3.3 V  
capacitance  
[3]  
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.  
[2] tpd is the same as tPLH and tPHL  
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).  
PD = CPD x VCC2 x fi x N + ∑(CL x VCC2 x fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
∑(CL x VCC2 x fo) = sum of outputs.  
11.1. Waveforms and test circuit  
V
I
V
M
A, B, C input  
GND  
t
t
PLH  
PHL  
V
OH  
Y output  
V
M
V
OL  
001aad936  
Measurement points are given in Table 9.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 5. The input A, B and C to output Y propagation delays  
Table 9. Measurement points  
Supply voltage  
VCC  
Input  
VM  
Output  
VM  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
0.5VCC  
0.5VCC  
1.5 V  
1.5 V  
0.5VCC  
0.5VCC  
0.5VCC  
1.5 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.5 V  
0.5VCC  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
5 / 11  
 
 
 
 
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
V
EXT  
V
CC  
R
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
mna616  
Test data is given in Table 10.  
Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance; should be equal to the output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig. 6. Test circuit for measuring switching times  
Table 10. Test data  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
VEXT  
tr = tf  
RL  
tPLH, tPHL  
open  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
VCC  
VCC  
2.7 V  
2.7 V  
VCC  
≤ 2.0 ns  
≤ 2.0 ns  
≤ 2.5 ns  
≤ 2.5 ns  
≤ 2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
50 pF  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
open  
open  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
open  
open  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
6 / 11  
 
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
12. Package outline  
Plastic surface-mounted package; 6 leads  
SOT363  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
1
2
3
c
e
1
b
L
w
M B  
p
p
e
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
1
UNIT  
A
b
p
c
D
e
e
H
L
Q
v
w
y
E
p
1
E
max  
0.30  
0.20  
1.1  
0.8  
0.25  
0.10  
2.2  
1.8  
1.35  
1.15  
2.2  
2.0  
0.45  
0.15  
0.25  
0.15  
mm  
0.1  
1.3  
0.65  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
04-11-08  
06-03-16  
SOT363  
SC-88  
Fig. 7. Package outline SOT363 (SC-88)  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
7 / 11  
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
Plastic surface-mounted package (TSOP6); 6 leads  
SOT457  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
c
1
2
3
L
p
e
b
p
w
M B  
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
1
b
c
D
e
H
L
Q
v
w
y
E
p
p
E
0.1  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
05-11-07  
06-03-16  
SOT457  
SC-74  
Fig. 8. Package outline SOT457 (SC-74)  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
8 / 11  
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
13. Abbreviations  
Table 11. Abbreviations  
Acronym  
CMOS  
DUT  
Description  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
HBM  
MIL  
Military  
MM  
Machine Model  
TTL  
Transistor-Transistor Logic  
14. Revision history  
Table 12. Revision history  
Document ID  
Release date  
20180821  
Data sheet status  
Change notice  
Supersedes  
74LVC1G332_Q100 v.3  
Modifications:  
Product data sheet  
-
74LVC1G332_Q100 v.2  
The format of this data sheet has been redesigned to comply with the identity guidelines of  
Nexperia.  
Legal texts have been adapted to the new company name where appropriate.  
74LVC1G332_Q100 v.2  
Modifications:  
20161209  
Table 7: The maximum limits for leakage current and supply current have changed.  
20140526 Product data sheet  
Product data sheet  
-
74LVC1G332_Q100 v.1  
74LVC1G332_Q100 v.1  
-
-
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
9 / 11  
 
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
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[1][2]  
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authorization from competent authorities.  
Limited warranty and liability — Information in this document is believed  
to be accurate and reliable. However, Nexperia does not give any  
representations or warranties, expressed or implied, as to the accuracy  
or completeness of such information and shall have no liability for the  
consequences of use of such information. Nexperia takes no responsibility  
for the content in this document if provided by an information source outside  
of Nexperia.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
In no event shall Nexperia be liable for any indirect, incidental, punitive,  
special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal  
or replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Trademarks  
Notice: All referenced brands, product names, service names and  
trademarks are the property of their respective owners.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, Nexperia’s aggregate and cumulative liability towards customer  
for the products described herein shall be limited in accordance with the  
Terms and conditions of commercial sale of Nexperia.  
Right to make changes — Nexperia reserves the right to make changes  
to information published in this document, including without limitation  
specifications and product descriptions, at any time and without notice. This  
document supersedes and replaces all information supplied prior to the  
publication hereof.  
Suitability for use in automotive applications — This Nexperia product  
has been qualified for use in automotive applications. Unless otherwise  
agreed in writing, the product is not designed, authorized or warranted to  
be suitable for use in life support, life-critical or safety-critical systems or  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
10 / 11  
 
Nexperia  
74LVC1G332-Q100  
3-input OR gate  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................1  
4. Marking..........................................................................2  
5. Functional diagram.......................................................2  
6. Pinning information......................................................2  
6.1. Pinning.........................................................................2  
6.2. Pin description.............................................................2  
7. Functional description................................................. 3  
8. Limiting values............................................................. 3  
9. Recommended operating conditions..........................3  
10. Static characteristics..................................................4  
11. Dynamic characteristics.............................................5  
11.1. Waveforms and test circuit........................................ 5  
12. Package outline.......................................................... 7  
13. Abbreviations..............................................................9  
14. Revision history..........................................................9  
15. Legal information......................................................10  
© Nexperia B.V. 2018. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 21 August 2018  
©
74LVC1G332_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 21 August 2018  
11 / 11  

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