74LVC594AD-Q100 [NEXPERIA]
8-bit shift register with output registerProduction;
| 型号： | 74LVC594AD-Q100 |
| 厂家： | 
Nexperia |
| 描述： | 8-bit shift register with output registerProduction 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总18页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC594A-Q100
8-bit shift register with output register
Rev. 3 — 3 September 2020
Product data sheet
1. General description
The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register.
Separate clock and reset inputs are provided on both shift and storage registers. The device
features a serial input (DS) and a serial output (Q7S) to enable cascading. Data is shifted on the
LOW-to-HIGH transitions of the SHCP input, and the data in the shift register is transferred to the
storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected
together, the shift register will always be one clock pulse ahead of the storage register. A LOW
level on one of the two register reset pins (SHR and STR) will clear the corresponding register.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
•
Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Balanced propagation delays
All inputs have Schmitt-trigger action
Complies with JEDEC standard:
•
•
•
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
•
•
ESD protection:
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
3. Applications
•
•
Serial-to-parallel data conversion
Remote control holding register
Nexperia
74LVC594A-Q100
8-bit shift register with output register
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC594AD-Q100
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT403-1
SOT763-1
74LVC594APW-Q100 -40 °C to +125 °C
74LVC594ABQ-Q100 -40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
DHVQFN16 plastic dual in-line compatible
thermal enhanced very thin quad
flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
5. Functional diagram
SHCP STCP
11
12
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
9
15
1
14
DS
11
SHCP
SHR
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
10
2
9
Q7S
DS
14
3
4
12
13
STCP
STR
5
6
7
15
1
2
3
4
5
6
7
10
13
SHR STR
mbc319
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
mbc320
Fig. 1. Logic symbol
Fig. 2. Functional diagram
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
2 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
STAGE 0
STAGES 1 TO 6
STAGE 7
DS
Q7S
D
Q
FFSH0
CP
D
Q
D
Q
FFSH7
CP
R
R
SHCP
SHR
D
FFST0
CP
D
FFST7
CP
Q
Q
R
R
STCP
STR
mbc321
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig. 3. Logic diagram
SHCP
DS
STCP
SHR
STR
Q0
Q1
Q6
Q7
Q7S
mbc323
Fig. 4. Timing diagram
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
3 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
6. Pinning information
6.1. Pinning
74LVC594A-Q100
terminal 1
index area
2
3
4
5
6
7
15
14
13
12
11
10
Q2
Q0
Q3
Q4
Q5
Q6
Q7
DS
STR
STCP
SHCP
SHR
74LVC594A-Q100
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
Q2
V
CC
(1)
GND
Q0
Q3
DS
Q4
STR
STCP
SHCP
SHR
Q7S
aaa-009698
Q5
Q6
Transparent top view
Q7
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
GND
aaa-009697
Fig. 5. Pin configuration SOT109-1 (SO16) and
SOT403-1 (TSSOP16)
Fig. 6. Pin configuration SOT763-1 (DHVQFN16)
6.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
ground (0 V)
GND
Q7S
SHR
SHCP
STCP
STR
DS
8
9
serial data output
10
11
12
13
14
16
shift register reset (active LOW)
shift register clock input
storage register clock input
storage register reset (active LOW)
serial data input
VCC
supply voltage
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
4 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
7. Functional description
Table 3. Function table
H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change
Input
Output
Q7S
L
Function
SHCP STCP
SHR
L
STR
X
DS
X
Qn
NC
L
X
X
X
↑
X
X
↑
a LOW-state on SHR only affects the shift register
a LOW-state on STR only affects the storage register
empty shift register loaded into storage register
X
L
X
NC
L
H
X
L
L
X
H
X
H
Q6S
NC
logic HIGH level shifted into shift register stage 0. Contents
of all shift register stages shifted through, e.g. previous state
of stage 6 (internal Q6S) appears on the serial output (Q7S)
X
↑
↑
↑
H
H
H
H
X
X
NC
QnS
QnS
contents of shift register stages (internal QnS) are
transferred to the storage register and parallel output stages
Q6S
contents of shift register shifted through; previous contents of
the shift register is transferred to the storage register and the
parallel output stages
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
+6.5
±50
6.5
IOK
VO
output clamping current
output voltage
VO > VCC or VO < 0 V
3-state
mA
V
[1]
[1]
-0.5
-0.5
-
output HIGH or LOW state
VO = 0 V to VCC
VCC + 0.5 V
IO
output current
±50
100
-
mA
ICC
IGND
Tstg
Ptot
supply current
-
mA
mA
°C
ground current
-100
-65
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
5 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
1.2
0
Typ
Max
3.6
-
Unit
V
VCC
supply voltage
-
-
-
-
-
-
-
-
functional
V
VI
input voltage
5.5
5.5
VCC
V
VO
output voltage
3-state
0
V
output HIGH or LOW state
0
V
Tamb
ambient temperature
-40
-
+125 °C
Δt/ΔV
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
20
10
ns/V
-
ns/V
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input
voltage
VCC = 1.2 V
1.08
-
-
-
-
-
-
-
-
-
1.08
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
0.65VCC
-
0.65VCC
-
1.7
-
-
1.7
-
-
2.0
2.0
VIL
LOW-level input
voltage
-
-
-
-
0.12
-
-
-
-
0.12
0.35VCC
0.7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.35VCC
0.7
0.8
0.8
VOH
HIGH-level output VI = VIH or VIL
voltage
IO = -100 μA;
VCC-0.2
-
-
VCC-0.3
-
V
VCC = 1.65 V to 3.6 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -18 mA; VCC = 3.0 V
IO = -24 mA; VCC = 3.0 V
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 100 μA;
-
-
0.2
-
0.3
V
VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
-
-
-
0.45
0.6
-
-
-
-
0.65
0.8
V
V
V
V
0.4
0.6
0.55
0.8
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
6 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
II
input leakage
current
VCC = 3.6 V; VI = 5.5 V or GND
-
-
-
-
±0.1
±5
-
±20
μA
μA
μA
μA
IOFF
ICC
ΔICC
power-off leakage VCC = 0 V; VI or VO = 5.5 V
current
0.1
0.1
5
10
-
-
-
20
40
supply current
VCC = 3.6 V;
VI = VCC or GND; IO = 0 A
10
additional supply per input pin;
current VCC = 1.65 V to 3.6 V;
VI = VCC - 0.6 V; IO = 0 A
500
5000
CI
input capacitance VCC = 0 V to 3.6 V;
VI = GND to VCC
-
5.0
-
-
-
pF
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 13.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation delay SHCP to Q7S; see Fig. 7
VCC = 1.2 V
[2] [3]
-
17.5
5.2
3.2
3.5
3.1
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.5
15.8
8.1
7.6
6.7
2.0
1.5
1.5
1.5
18.2
9.3
8.7
7.7
VCC = 3.0 V to 3.6 V
STCP to Qn; see Fig. 8
VCC = 1.2 V
[2]
-
19.3
7.6
4.8
5.2
4.5
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.2
15.8
8.1
7.6
6.7
2.0
1.5
1.5
1.2
18.2
9.3
8.7
7.7
VCC = 3.0 V to 3.6 V
tPHL
HIGH to LOW
propagation delay
SHR to Q7S; see Fig. 11
VCC = 1.2 V
-
12.0
5.0
3.8
3.9
3.3
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.2
1.2
15.8
8.1
7.6
6.7
2.0
1.5
1.2
1.2
18.2
9.3
8.7
7.7
VCC = 3.0 V to 3.6 V
STR to Qn; see Fig. 12
VCC = 1.2 V
-
20.0
7.7
5.0
5.3
4.4
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.2
1.2
15.8
8.1
7.6
6.7
2.0
1.5
1.2
1.2
18.2
9.3
8.7
7.7
VCC = 3.0 V to 3.6 V
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
7 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
tW
pulse width
SHCP, STCP HIGH or LOW;
see Fig. 7 and Fig. 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.0
5.0
4.5
4.0
2.5
2.0
1.5
1.5
-
-
-
-
7.0
5.5
5.0
4.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
SHR, STR LOW; see Fig. 11
and Fig. 12
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.0
4.0
2.5
2.5
2.5
2.0
1.5
1.5
-
-
-
-
5.5
4.5
3.0
3.0
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
DS to SHCP; see Fig. 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tsu
set-up time
5.0
4.0
2.0
2.0
1.0
0.8
0.6
0.6
-
-
-
-
5.5
4.5
2.5
2.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
SHR to STCP; see Fig. 10
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
8.0
5.0
4.0
4.0
3.5
2.1
1.8
1.7
-
-
-
-
8.5
5.5
4.5
4.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
SHCP to STCP; see Fig. 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
8.0
5.0
4.0
4.0
3.5
2.1
1.8
1.7
-
-
-
-
8.5
5.5
4.5
4.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
DS to SHCP; see Fig. 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
th
hold time
[3]
1.5
1.5
1.5
1.0
0.2
0.1
-
-
-
-
2.0
2.0
2.0
1.5
-
-
-
-
ns
ns
ns
ns
-0.1
-0.2
VCC = 3.0 V to 3.6 V
trec
recovery time
SHR to SHCP, STR to STCP;
see Fig. 11 and Fig. 12
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
5.0
4.0
2.0
2.0
-2.7
-1.5
-1.0
-1.0
-
-
-
-
5.5
4.5
2.5
2.5
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
fmax
maximum
frequency
SHCP or STCP; see Fig. 7
and Fig. 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
130
140
150
180
-
-
-
-
70
90
-
-
-
-
MHz
MHz
MHz
MHz
100
110
130
100
115
VCC = 3.0 V to 3.6 V
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
8 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
tsk(o)
CPD
output skew time VCC = 3.0 V to 3.6 V
[4]
[5]
-
-
1.0
-
1.5
ns
power dissipation VI = GND to VCC
capacitance
VCC = 1.65 V to 1.95 V
-
-
-
50
45
44
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
[3] Cascadability is guaranteed under identical VCC and temperature conditions.
.
[4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC 2 x fi x N + ∑(CL x VCC 2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL x VCC 2 x fo) = sum of outputs.
11.1. Waveforms and test circuit
1/f
max
V
I
SHCP input
GND
V
M
t
W
t
t
PHL
PLH
V
OH
V
Q7S output
V
M
OL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
9 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
V
I
SHCP input
GND
V
M
t
1/f
max
su
V
I
STCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
Qn output
M
V
OL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width
and the shift clock to storage clock set-up time
V
I
V
SHCP input
M
GND
t
t
su
su
M
t
t
h
h
V
I
V
DS input
GND
V
OH
V
Q7S output
M
V
OL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 9. The data set-up and hold times for the serial data input (DS)
©
74LVC594A_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
10 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
V
M
SHR input
STCP input
Qn outputs
t
su
V
M
V
M
mbc326
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 10. The shift reset (SHR) to storage clock (STCP) set-up times
V
M
SHR input
t
W
t
rec
V
M
SHCP input
t
PHL
V
Q7S output
M
mbc324
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 11. The shift reset (SHR) pulse width, the shift reset to serial data output (Q7S) propagation delays and the
shift reset to shift clock (SHCP) recovery time
V
M
STR input
t
W
t
rec
V
M
STCP input
t
PHL
V
M
Qn outputs
mbc325
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 12. The storage reset (STR) pulse width, the storage reset to parallel data output (Qn) propagation delays and
the storage reset to storage clock (STCP) recovery time
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Product data sheet
Rev. 3 — 3 September 2020
11 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
Table 8. Measurement points
Supply voltage
Input
VM
Output
VM
VCC
VCC < 2.7 V
VCC ≥ 2.7 V
0.5 x VCC
1.5 V
0.5 x VCC
1.5 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
r
f
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 13. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 x VCC
2 x VCC
2 x VCC
2 x VCC
2 x VCC
tPHZ, tPZH
GND
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
GND
open
GND
open
GND
3.0 V to 3.6 V
open
GND
©
74LVC594A_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
12 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 14. Package outline SOT109-1 (SO16)
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74LVC594A_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
13 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 15. Package outline SOT403-1 (TSSOP16)
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
14 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
h
e
e
y
D
D
E
L
v
w
y
1
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig. 16. Package outline SOT763-1 (DHVQFN16)
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
15 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MIL
Military
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74LVC594A_Q100 v.3
Modifications:
20200903
Product data sheet
-
74LVC594A_Q100 v.2
•
•
Section 1 and Section 2 updated.
Table 4: Derating values for Ptot total power dissipation updated.
74LVC594A_Q100 v.2
Modifications:
20170721
Product data sheet 74LVC594A_Q100 v.1
-
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 11: table note added for cascading purposes.
74LVC594A_Q100 v.1
20131115
Product data sheet
-
-
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
16 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
15. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
17 / 18
Nexperia
74LVC594A-Q100
8-bit shift register with output register
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................4
6.1. Pinning.........................................................................4
6.2. Pin description.............................................................4
7. Functional description................................................. 5
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................6
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit........................................ 9
12. Package outline........................................................ 13
13. Abbreviations............................................................16
14. Revision history........................................................16
15. Legal information......................................................17
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 3 September 2020
©
74LVC594A_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 3 September 2020
18 / 18
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