74LVCH16373ADGG [NEXPERIA]
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction;型号: | 74LVCH16373ADGG |
厂家: | Nexperia |
描述: | 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction |
文件: | 总15页 (文件大小:256K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 10 — 1 October 2021
Product data sheet
1. General description
The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs.
The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The
devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each
controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the
latches are transparent, a latch output will change each time its corresponding D-input changes.
When nLE is LOW the latches store the information that was present at the inputs a set-up time
preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features and benefits
•
Overvoltage tolerant inputs to 5.5 V
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
MULTIBYTE flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A only)
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
•
•
•
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
•
•
ESD protection:
•
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC16373ADGG
74LVCH16373ADGG
74LVC16373ADGV
74LVCH16373ADGV
-40 °C to +125 °C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
-40 °C to +125 °C
TVSOP48
plastic thin shrink small outline
package; 48 leads; body width 4.4 mm;
lead pitch 0.4 mm
SOT480-1
4. Functional diagram
1
1EN
C3
1OE
1LE
2OE
2LE
1
24
48
24
25
2EN
C4
1OE
2OE
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
3
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1
3D
5
6
5
8
6
9
8
11
12
13
14
16
17
19
20
22
23
9
11
12
13
14
16
17
19
20
22
23
4D
2
1LE
48
2LE
25
mgu768
mgu770
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
1D0
1Q0
2D0
2Q0
D
Q
D
Q
LATCH
1
LATCH
9
LE LE
LE LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
mgu769
Fig. 3. Logic diagram
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
2 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
V
CC
data input
to internal circuit
mgu771
Fig. 4. Bus hold circuit
5. Pinning information
5.1. Pinning
1
48
47
46
45
44
1LE
1D0
1D1
GND
1D2
1OE
2
1Q0
1Q1
GND
1Q2
1Q3
3
4
5
6
43 1D3
V
42
V
7
CC
CC
8
41 1D4
40 1D5
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
V
16373A
V
31
CC
CC
30 2D4
2Q4
2Q5
GND
2Q6
2Q7
2OE
2D5
29
28
GND
27 2D6
2D7
2LE
26
25
001aad112
Fig. 5. Pin configuration SOT362-1 (TSSOP48) and SOT480-1 (TSSOP48)
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
3 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1OE, 2OE
1LE, 2LE
GND
1, 24
output enable input (active LOW)
latch enable input (active HIGH)
ground (0 V)
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
VCC
supply voltage
1Q0 to 1Q7
2Q0 to 2Q7
1D0 to 1D7
2D0 to 2D7
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
data output
data output
data input
data input
6. Functional description
Table 3. Function table
Per section of eight bits.
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH to LOW LE transition
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH to LOW LE transition
Z = high-impedance OFF-state
Operating modes
Input
Internal latch
Output
nQ0 to nQ7
nOE
nLE
H
H
L
nDn
Enable and read register
(transparent mode)
L
L
L
L
L
H
l
L
L
H
L
H
L
Latch and read register
L
h
l
H
L
H
Z
Z
Latch register and disable outputs H
H
L
L
h
H
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
4 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0
mA
V
VI
[1]
+6.5
±50
IOK
VO
output clamping current
output voltage
VO > VCC or VO < 0
output HIGH or LOW state
output 3-state
mA
V
[2]
[2]
-0.5
-0.5
-
VCC + 0.5
+6.5
±50
V
IO
output current
VO = 0 V to VCC
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
-100
-65
-
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[3]
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SOT362-1 (TSSOP48) packages: Ptot derates linearly with 12.2 mW/K above 109 °C.
For SOT480-1 (TVSOP48) packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
1.65
1.2
0
Typ
Max Unit
VCC
supply voltage
-
-
-
-
-
-
-
-
3.6
3.6
5.5
VCC
5.5
V
V
V
V
V
functional
VI
input voltage
VO
output voltage
output HIGH or LOW state
output 3-state
0
0
Tamb
ambient temperature
in free air
-40
0
+125 °C
Δt/ΔV
input transition rise and fall rate
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
20
10
ns/V
ns/V
0
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
5 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
1.08
-
-
1.08
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
0.65VCC
-
-
-
-
-
-
-
-
0.65VCC
-
1.7
-
-
1.7
-
-
2.0
2.0
VIL
LOW-level
input voltage
-
-
-
-
0.12
0.35VCC
0.7
-
-
-
-
0.12
0.35VCC
0.7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
0.8
0.8
VOH
HIGH-level
output voltage
IO = -100 μA;
VCC - 0.2
-
-
VCC - 0.3
-
V
VCC = 1.65 V to 3.6 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -18 mA; VCC = 3.0 V
IO = -24 mA; VCC = 3.0 V
VI = VIH or VIL
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output voltage
IO = 100 μA;
-
-
0.2
-
0.3
V
VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
-
0.45
0.6
-
-
-
-
-
0.65
0.8
V
-
V
-
-
0.4
0.6
V
0.55
±5
0.8
V
II
input leakage VCC = 3.6 V;
[2]
[2]
±0.1
±20
μA
current
VI = 5.5 V or GND
IOZ
IOFF
OFF-state
VI = VIH or VIL; VCC = 3.6 V;
output current VO = 5.5 V or GND
-
-
±0.1
±0.1
±5
-
-
±20
±20
μA
μA
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
±10
ICC
supply current VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
-
0.1
5
20
-
-
80
μA
μA
ΔICC
additional
per input pin;
500
5000
supply current VCC = 2.7 V to 3.6 V;
VI = VCC - 0.6 V; IO = 0 A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
5.0
-
-
-
pF
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
6 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
10
Typ [1]
Max
Min
10
Max
IBHL
bus hold LOW VCC = 1.65; VI = 0.58 V
[3][4]
[3][4]
[3][5]
[3][5]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
current
VCC = 2.3; VI = 0.7 V
30
25
VCC = 3.0; VI = 0.8 V
75
60
IBHH
bus hold
HIGH current
VCC = 1.65; VI = 1.07 V
VCC = 2.3; VI = 1.7 V
VCC = 3.0; VI = 2.0 V
-10
-30
-75
200
300
500
-200
-300
-500
-10
-25
-60
200
300
500
-200
-300
-500
IBHLO
bus hold LOW VCC = 1.95 V
overdrive
current
VCC = 2.7 V
VCC = 3.6 V
IBHHO
bus hold
HIGH
overdrive
current
VCC = 1.95 V
VCC = 2.7 V
VCC = 3.6 V
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
[2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
[3] Valid for data inputs (74LVCH16373A) only; control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 10.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tpd
propagation delay Dn to Qn; see Fig. 6
VCC = 1.2 V
[2]
-
12
5.4
2.9
2.9
2.4
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
1.5
1.0
1.5
1.0
11.4
5.7
4.9
4.4
1.5
1.0
1.5
1.0
13.2
6.6
6.5
5.5
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
LE to Qn; see Fig. 7
VCC = 1.2 V
-
14
6.4
3.4
3.0
2.9
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.5
12.4
6.1
5.3
4.8
2.0
1.5
1.5
1.5
14.4
7.1
7.0
6.0
VCC = 3.0 V to 3.6 V
OE to Qn; see Fig. 8
VCC = 1.2 V
ten
enable time
[2]
-
18
5.5
3.1
3.3
2.5
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.5
1.0
12.4
6.6
5.7
4.9
1.5
1.0
1.5
1.0
14.3
7.6
7.5
6.5
VCC = 3.0 V to 3.6 V
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
7 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tdis
disable time
OE to Qn; see Fig. 8
VCC = 1.2 V
[2]
-
11
4.5
2.5
3.3
3.1
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.8
1.0
1.5
1.5
9.1
5.1
6.3
5.4
2.8
1.0
1.5
1.5
10.5
6.0
8.0
7.0
VCC = 3.0 V to 3.6 V
LE HIGH; see Fig. 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tW
tsu
th
pulse width
set-up time
hold time
5.0
4.0
3.0
3.0
-
-
-
-
-
-
5.0
4.0
3.0
3.0
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
Dn to LE; see Fig. 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
3.0
2.5
2.0
2.0
-
-
-
-
-
-
3.0
2.5
2.0
2.0
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
Dn to LE; see Fig. 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
2.5
2.0
0.9
+0.9
-
-
-
2.5
2.0
0.9
+0.9
-
-
ns
ns
ns
ns
ns
-
-
-
-
-
-
-1.0
-
VCC = 3.0 V to 3.6 V
-
-
tsk(o)
CPD
output skew time VCC = 3.0 V to 3.6 V
[3]
[4]
1.0
1.5
power dissipation per input; VI = GND to VCC
capacitance
VCC = 1.65 V to 1.95 V
-
-
-
10.8
13.0
15.0
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC 2 × fo) = sum of the outputs
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
8 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
10.1. Waveforms and test circuit
V
I
LE input
GND
V
t
V
V
t
M
M
M
V
I
t
W
V
V
M
Dn input
M
PHL
PLH
GND
V
OH
t
t
PLH
PHL
V
V
M
Qn output
M
V
OH
V
OL
mgu773
V
M
Qn output
Measurement points are given in Table 8.
mgu772
V
OL
VOL and VOH are typical output voltage levels that
occur with the output load.
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that
occur with the output load.
Fig. 7. Latch enable input (LE) pulse width, and the
latch enable input to output (Qn) propagation
delays
Fig. 6. Input (Dn) to output (Qn) propagation delays
V
I
OE input
V
V
M
M
GND
t
t
PZL
PLZ
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mgu775
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 8. 3-state enable and disable times
V
I
V
M
Dn input
GND
t
t
h
h
t
t
su
su
V
I
V
M
LE input
GND
mgu774
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 9. Data set-up and hold times for the Dn input to the LE input
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
9 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Table 8. Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.15 V
VOH - 0.15 V
VOH - 0.3 V
VOH - 0.3 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
1.5 V
1.5 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 10. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
GND
GND
GND
GND
GND
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
open
open
3.0 V to 3.6 V
open
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
10 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
11. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
max
(1)
(2)
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
0.4
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Fig. 11. Package outline SOT362-1 (TSSOP48)
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
11 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
TVSOP48: plastic thin shrink small outline package; 48 leads;
body width 4.4 mm; lead pitch 0.4 mm
SOT480-1
E
A
D
X
c
y
H
v
M
A
E
Z
25
48
Q
(A )
3
A
A
2
A
1
pin 1 index
θ
L
p
L
detail X
1
24
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.85
0.23
0.13
0.20
0.09
9.8
9.6
4.5
4.3
6.6
6.2
0.7
0.5
0.4
0.3
0.4
0.1
mm
1.1
0.4
0.2
0.07
0.08
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-02-18
19-12-11
SOT480-1
MO-153
Fig. 12. Package outline SOT480-1 (TVSOP48)
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
12 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
CMOS
DUT
ESD
HBM
MM
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date
20211001
Data sheet status
Change notice
Supersedes
74LVC_LVCH16373A v.10
Modifications:
Product data sheet
-
74LVC_LVCH16373A v.9
•
•
•
Type number 74LVC16373ADL (SOT370-1/SSOP48) removed.
Package outline drawing SOT480-1 updated.
Section 1 and Section 2 updated.
74LVC_LVCH16373A v.9
Modifications:
20190215
Product data sheet
-
74LVC_LVCH16373A v.8
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type numbers 74LVCH16373ADL (SOT370-1) removed.
Type numbers 74LVC16373ADGV and 74LVCH16373ADGV (SOT480-1) added.
74LVC_LVCH16373A v.8
Modifications:
20140106
General description corrected (errata).
20130118 Product data sheet
Product data sheet
-
74LVC_LVCH16373A v.7
•
74LVC_LVCH16373A v.7
Modifications:
-
74LVC_LVCH16373A v.6
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges.
74LVC_LVCH16373A v.6
74LVC_LVCH16373A v.5
74LVC_H16373A v.4
20031208
20021002
19980317
Product specification
Product specification
Product specification
-
-
-
74LVC_LVCH16373A v.5
74LVC_H16373A v.4
74LVC16373A_
74LVCH16373A v.3
74LVC16373A_
19980317
Product specification
-
74LVC16373A v.2
74LVCH16373A v.3
74LVC16373A v.2
74LVC16373A v.1
19970822
19960108
Product specification
-
-
-
74LVC16373A v.1
-
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
13 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
14 / 15
Nexperia
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................4
6. Functional description................................................. 4
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 9
11. Package outline........................................................ 11
12. Abbreviations............................................................13
13. Revision history........................................................13
14. Legal information......................................................14
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 1 October 2021
©
74LVC_LVCH16373A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 1 October 2021
15 / 15
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