74LVT02PW [NEXPERIA]

3.3 V Quad 2-input NOR gateProduction;


型号：	74LVT02PW
厂家：	Nexperia
描述：	3.3 V Quad 2-input NOR gateProduction 信息通信管理光电二极管逻辑集成电路
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74LVT02

3.3 V Quad 2-input NOR gate

Rev. 4 — 1 March 2021

Product data sheet

1. General description

The 74LVT02 is a quad 2-input NOR gate. This device is fully specified for partial power down

applications using I_OFF. The I_OFFcircuitry disables the output, preventing the potentially damaging

backflow current through the device when it is powered down.

2. Features and benefits

•

Wide supply voltage range from 2.7 V to 3.6 V

•

Output capability: +64 mA and -32 mA

Direct interface with TTL levels

Overvoltage tolerant inputs to 5.5 V

Power-up 3-state

No bus current loading when output is tied to 5 V bus

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Specified from -40 °C to 85 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

Version

74LVT02D

-40 °C to +85 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LVT02PW

-40 °C to +85 °C

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

4. Functional diagram

≥1

mna216

001aah084

mna215

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74LVT02

GND

aaa-026557

aaa-026558

Fig. 4. Pin configuration SOT108-1 (SO14)

Fig. 5. Pin configuration SOT402-1 (TSSOP14)

5.2. Pin description

Table 2. Pin description

Symbol

Description

data output

data input

1Y, 2Y, 3Y, 4Y

1A, 2A, 3A, 4A

1B, 2B, 3B, 4B

GND

1, 4, 10, 13

2, 5, 8, 11

3, 6, 9,12

data input

ground (0 V)

supply voltage

V_CC

74LVT02

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Product data sheet

Rev. 4 — 1 March 2021

2 / 10

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level

Input

Output

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

-0.5

-50

Max

+4.6

+7.0

Unit

V_CC

V_I

supply voltage

input voltage

[1]

V_O

I_IK

output voltage

output in OFF-state or HIGH-state

V_I< 0 V

input clamping current

output clamping current

output current

°C

I_OK

I_O

V_O< 0 V

output in LOW-state

output in HIGH-state

-32

-65

T_stg

T_j

storage temperature

junction temperature

total power dissipation

+150

150

500

[2]

[3]

°C

P_tot

T_amb= -40 to +85 °C

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability.

[3] For SOT402-1 (TSSOP14) package: P_totderates linearly with 7.3 mW/K above 81 °C.

8. Recommended operating conditions

Table 5. Operating conditions

Symbol Parameter

Conditions

Min

2.7

Typ

Max

3.6

5.5

Unit

V_CC

V_I

supply voltage

input voltage

I_OH

HIGH-level output current

LOW-level output current

ambient temperature

input transition rise and fall rate

-20

°C

I_OL

T_amb

Δt/ΔV

in free-air

-40

+85

outputs enabled

ns/V

74LVT02

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Product data sheet

Rev. 4 — 1 March 2021

3 / 10

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ[1]

Max

Unit

T_amb= -40 °C to +85 °C

V_IK

V_IH

V_IL

input clamping voltage

V_CC= 2.7 V; I_IK= -18 mA

-1.2

HIGH-level input voltage

LOW-level input voltage

2.0

0.8

V_OH

HIGH-level output

voltage

V_CC= 2.7 V to 3.6 V; I_OH= -100 μA

V_CC= 2.7 V; I_OH= -6 mA

V_CC- 0.2

2.4

V_CC= 3.0 V; I_OH= -20 mA

2.0

V_OL

LOW-level output voltage V_CC= 2.7 V; I_OL= 100 μA

V_CC= 2.7 V; I_OL= 24 mA

0.2

0.5

±1

±100

V_CC= 3.0 V; I_OL= 32 mA

I_I

input leakage current

V_CC= 0 V or 3.6 V; V_I= 5.5 V

V_CC= 3.6 V; V_I= V_CCor GND

V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

μA

I_OFF

I_CC

power-off leakage

current

supply current

V_CC= 3.6 V; V_I= GND or V_CC; I_O= 0 A

output HIGH

0.02

μA

output LOW

ΔI_CC

additional supply current per input pin; V_CC= 3.0 V to 3.6 V;

one input at V_CC- 0.6 V

[2]

0.2

and other inputs at V_CCor GND

C_I

input capacitance

V_I= 0 V or 3.0 V

[1] Typical values are measured at T_amb= 25 °C and V_CC= 3.3 V.

[2] This is the increase in supply current for each input at the specified voltage level other than V_CCor GND.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.

Symbol Parameter

Conditions

Min

Typ[1]

Max

Unit

T_amb= -40 °C to +85 °C

t_PLH

LOW to HIGH

propagation delay

nA or nB to nY; see Fig. 6

V_CC= 2.7 V

5.2

4.4

V_CC= 3.0 V to 3.6 V

nA or nB to nY; see Fig. 6

V_CC= 2.7 V

2.8

t_PHL

HIGH to LOW

propagation delay

3.4

3.6

V_CC= 3.0 V to 3.6 V

2.6

[1] Typical values are measured at T_amb= 25 °C and V_CC= 3.3 V.

74LVT02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 1 March 2021

4 / 10

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

10.1. Waveforms and test circuit

A, B input

GND

PHL

PLH

Y output

mna612

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 6. Input to output propagation delays

Table 8. Measurement points

Input

V_M

Output

V_I

V_M

1.5 V

2.7 V

1.5 V

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

PULSE

GENERATOR

DUT

001aaf615

Test data is given in Table 9.

Definitions test circuit:

R_T= termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= load capacitance including jig and probe capacitance.

R_L= load resistance.

Fig. 7. Test circuit for measuring switching times

Table 9. Test data

Input

Load

C_L

Test

V_I

f_i

t_W

t_r, t_f

R_L

2.7 V

≤ 10 MHz

500 ns

≤ 2.5 ns

50 pF

500 Ω

t_PLH, t_PHL

74LVT02

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Product data sheet

Rev. 4 — 1 March 2021

5 / 10

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

11. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

(A )

pin 1 index

detail X

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.75

1.27

0.05

1.05

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig. 8. Package outline SOT108-1 (SO14)

74LVT02

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Product data sheet

Rev. 4 — 1 March 2021

6 / 10

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.1

0.65

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig. 9. Package outline SOT402-1 (TSSOP14)

74LVT02

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Product data sheet

Rev. 4 — 1 March 2021

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Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

DUT

ESD

HBM

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20210301 Product data sheet

Change notice Supersedes

- 74LVT02 v.3

74LVT02 v.4

Modifications:

•

Type number 74LVT02DB (SOT337-1 / SSOP14) removed.

Section 1 and Section 2 updated.

Section 7: Derating value for P_tottotal power dissipation updated.

74LVT02 v.3

20170407

Product data sheet

74LVT02 v.2

Modifications:

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74LVT02 v.2

19960815

Product specification

74LVT02 v.1

74LVT02

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Product data sheet

Rev. 4 — 1 March 2021

8 / 10

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

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Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

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or problem which is based on any weakness or default in the customer’s

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Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

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74LVT02

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Product data sheet

Rev. 4 — 1 March 2021

9 / 10

Nexperia

74LVT02

3.3 V Quad 2-input NOR gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................2

5.1. Pinning.........................................................................2

5.2. Pin description.............................................................2

6. Functional description................................................. 3

7. Limiting values............................................................. 3

8. Recommended operating conditions..........................3

9. Static characteristics....................................................4

10. Dynamic characteristics............................................ 4

10.1. Waveforms and test circuit........................................ 5

11. Package outline.......................................................... 6

12. Abbreviations..............................................................8

13. Revision history..........................................................8

14. Legal information........................................................9

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 1 March 2021

74LVT02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 1 March 2021

10 / 10

74LVT02PW [NEXPERIA]

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