74LVT16374ADGG [NEXPERIA]

3.3 V 16-bit edge-triggered D-type flip-flop; 3-stateProduction;


型号：	74LVT16374ADGG
厂家：	Nexperia
描述：	3.3 V 16-bit edge-triggered D-type flip-flop; 3-stateProduction 驱动信息通信管理光电二极管逻辑集成电路
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中文：	中文翻译
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74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Rev. 12 — 6 August 2021

Product data sheet

1. General description

The 74LVT16374A; 74LVTH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs.

The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks

(1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops

will store the state of their individual D-inputs that meet the set-up and hold time requirements

on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a

high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops.

2. Features and benefits

•

16-bit edge-triggered flip-flop

3-state buffers

•

Output capability: +64 mA and -32 mA

Wide supply voltage range from 2.7 to 3.6 V

Overvoltage tolerant inputs to 5.5 V

BiCMOS high speed and output drive

Direct interface with TTL levels

Input and output interface capability to systems at 5 V supply

Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs.

(74LVTH16374A only)

•

Live insertion and extraction permitted

Power-up reset

Power-up 3-state

No bus current loading when output is tied to 5 V bus

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Specified from -40 °C to 85 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVT16374ADGG

74LVTH16374ADGG

-40 °C to +85 °C

TSSOP48

plastic thin shrink small outline package; 48 leads; SOT362-1

body width 6.1 mm

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

4. Functional diagram

47 46 44 43 41 40 38 37

EN1

1OE

1CP

2OE

2CP

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

EN2

1CP

1OE

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

11 12

36 35 33 32 30 29 27 26

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7

2CP

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

13 14 16 17 19 20 22 23

001aac369

001aaa254

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

nCP

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

001aac371

Fig. 3. Logic diagram

74LVT_LVTH16374A

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Product data sheet

Rev. 12 — 6 August 2021

2 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

5. Pinning information

5.1. Pinning

74LVT16374A

74LVTH16374A

1OE

1Q0

1Q1

GND

1Q2

1Q3

1CP

1D0

1D1

GND

1D2

1D3

1Q4

1Q5

GND

1Q6

1Q7

2Q0

2Q1

GND

2Q2

2Q3

1D4

1D5

GND

1D6

1D7

2D0

2D1

GND

2D2

2D3

2Q4

2Q5

GND

2Q6

2Q7

2OE

2D4

2D5

GND

2D6

2D7

2CP

001aak263

Fig. 4. Pin configuration SOT362-1 (TSSOP48)

5.2. Pin description

Table 2. Pin description

Symbol

Description

1OE, 2OE

1, 24

output enable input (active LOW)

clock input

1CP, 2CP

48, 25

1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7

2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7

GND

2, 3, 5, 6, 8, 9, 11, 12

data output

13, 14, 16, 17, 19, 20, 22, 23

4, 10, 15, 21, 28, 34, 39, 45

7, 18, 31, 42

data output

ground (0 V)

V_CC

supply voltage

data input

1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7

2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7

47, 46, 44, 43, 41, 40, 38, 37

36, 35, 33, 32, 30, 29, 27, 26

data input

74LVT_LVTH16374A

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Product data sheet

Rev. 12 — 6 August 2021

3 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;

NC = no change; X = don’t care;

Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition.

Operating mode

Input

Internal register

Output

nOE

nCP

↑

nDn

nQ0 to nQ7

Load and read register

↑

Hold

↑

nDn

Disable outputs

nDn

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

-0.5

-50

Max

+4.6

+7.0

Unit

V_CC

V_I

supply voltage

input voltage

[1]

V_O

I_IK

output voltage

output in OFF-state or HIGH-state

V_I< 0 V

input clamping current

output clamping current

output current

°C

I_OK

I_O

V_O< 0 V

output in LOW-state

output in HIGH-state

128

-64

-65

T_stg

T_j

storage temperature

junction temperature

total power dissipation

+150

150

500

[2]

°C

P_tot

T_amb= -40 °C to +85 °C

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability.

74LVT_LVTH16374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 12 — 6 August 2021

4 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter

Conditions

Min

2.7

Typ

Max Unit

V_CC

V_I

supply voltage

3.6

5.5

input voltage

V_IH

V_IL

I_OH

I_OL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output current

LOW-level output current

2.0

0.8

-32

°C

ns/V

none

+85

current duty cycle ≤ 50 %; f_i≥ 1 kHz

in free-air

T_amb

ambient temperature

-40

Δt/ΔV

input transition rise and fall rate

outputs enabled

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

T_amb= -40 °C to +85 °C

Unit

Min

-1.2

Typ [1]

-0.85

V_CC

Max

V_IK

input clamping voltage

V_CC= 2.7 V; I_IK= -18 mA

I_OH= -100 μA; V_CC= 2.7 V to 3.6 V

I_OH= -8 mA; V_CC= 2.7 V

I_OH= -32 mA; V_CC= 3.0 V

V_CC= 2.7 V

V_OH

HIGH-level output voltage

V_CC- 0.2

2.4

2.5

2.0

2.3

V_OL

LOW-level output voltage

I_OL= 100 μA

0.07

0.3

0.2

0.5

I_OL= 24 mA

V_CC= 3.0 V

I_OL= 16 mA

0.25

0.3

0.4

0.5

I_OL= 32 mA

I_OL= 64 mA

0.4

0.55

V_OL(pu)power-up LOW-level output

voltage

V_CC= 3.6 V; I_O= 1 mA;

V_I= V_CCor GND

[2]

[3]

0.1

I_I

input leakage current

control pins

V_CC= 3.6 V; V_I= V_CCor GND

V_CC= 0 V or 3.6 V; V_I= 5.5 V

input data pins

0.1

0.4

±1

μA

V_CC= 0 V or 3.6 V; V_I= 5.5 V

V_CC= 3.6 V; V_I= V_CC

V_CC= 3.6 V; V_I= 0 V

0.4

0.1

-0.4

0.1

135

-135

μA

-5

I_OFF

I_BHL

I_BHH

I_BHLO

power-off leakage current

bus hold LOW current

bus hold HIGH current

V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

V_CC= 3 V; V_I= 0.8 V

±100 μA

-75

μA

V_CC= 3 V; V_I= 2.0 V

bus hold LOW overdrive

current

input data pins; V_I= 0 V to 3.6 V;

V_CC= 3.6 V

[4]

500

74LVT_LVTH16374A

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Product data sheet

Rev. 12 — 6 August 2021

5 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Symbol Parameter

Conditions

T_amb= -40 °C to +85 °C

Unit

Min

Typ [1]

Max

I_BHHO

I_LO

bus hold HIGH overdrive

current

input data pins; V_I= 0 V to 3.6 V;

V_CC= 3.6 V

[4]

[5]

-500

μA

output leakage current

output in HIGH-state when V_O> V_CC

V_O= 5.5 V; V_CC= 3.0 V

;

125

I_O(pu/pd)power-up/power-down output V_CC≤ 1.2 V; V_O= 0.5 V to V_CC

;

±100 μA

current

V_I= GND or V_CC; nOE = don’t care

I_OZ

OFF-state output current

V_CC= 3.6 V; V_I= V_IHor V_IL

output HIGH: V_O= 3.0 V

output LOW: V_O= 0.5 V

0.5

μA

-5

I_CC

supply current

V_CC= 3.6 V; V_I= GND or V_CC; I_O= 0 A

outputs HIGH

0.07

4.0

0.12

6.0

outputs LOW

outputs disabled

[6]

[7]

0.07

0.1

0.12

0.2

ΔI_CC

additional supply current

per input pin; V_CC= 3.0 V to 3.6 V;

one input at V_CC- 0.6 V,

other inputs at V_CCor GND

C_I

input capacitance

output capacitance

input pins; V_I= 0 V or 3.0 V

C_O

output pins nQn; outputs disabled;

V_O= 0 V or V_CC

[1] Typical values are measured at V_CC= 3.3 V and at T_amb= 25 °C.

[2] For valid test results, data must not be loaded into the flips-flops (or latches) after applying power.

[3] Unused pins at V_CCor GND.

[4] This is the bus hold overdrive current required to force the input to the opposite logic state.

[5] This parameter is valid for any V_CCbetween 0 V and 1.2 V with a transition time of up to 10 ms.

From V_CC= 1.2 V to V_CC= 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for T_amb= 25 °C only.

[6] I_CCis measured with outputs pulled to V_CCor GND.

[7] This is the increase in supply current for each input at the specified voltage level other than V_CCor GND.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8.

Symbol Parameter

Conditions

T_amb= -40 °C to +85 °C

Unit

Min

Typ [1]

Max

f_max

t_PLH

maximum frequency

nCP; V_CC= 3.3 V ± 0.3 V; see Fig. 5

nCP to nQn; see Fig. 5

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

150

MHz

LOW to HIGH propagation

delay

1.5

2.9

5.0

5.6

t_PHL

t_PZH

t_PZL

HIGH to LOW propagation

delay

nCP to nQn; see Fig. 5

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

3.0

5.0

5.6

OFF-state to HIGH

propagation delay

nOE to nQn; see Fig. 6

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

3.2

4.8

6.0

OFF-state to LOW

propagation delay

nOE to nQn; see Fig. 6

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

3.0

4.6

5.2

74LVT_LVTH16374A

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Product data sheet

Rev. 12 — 6 August 2021

6 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Symbol Parameter

Conditions

T_amb= -40 °C to +85 °C

Unit

Min

Typ [1]

Max

t_PHZ

t_PLZ

t_su

HIGH to OFF-state

propagation delay

nOE to nQn; see Fig. 6

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

3.9

5.4

6.0

LOW to OFF-state

propagation delay

nOE to nQn; see Fig. 6

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

3.4

4.6

5.0

set-up time

hold time

nDn to nCP; HIGH or LOW; see Fig. 7

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

2.0

0.7

t_h

nDn to nCP; HIGH or LOW; see Fig. 7

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

0.8

0.1

t_W

pulse width

nCP HIGH; see Fig. 5

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

1.5

0.6

nCP LOW; see Fig. 5

V_CC= 3.3 V ± 0.3 V

V_CC= 2.7 V

3.0

1.6

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

10.1. Waveforms and test circuit

1/f

max

nCP input

GND

PHL

PLH

nQn output

001aaa256

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 5. Propagation delay clock input to output, clock pulse width and maximum clock frequency

74LVT_LVTH16374A

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Product data sheet

Rev. 12 — 6 August 2021

7 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

nOE input

nYn output

GND

3.0 V

PZL

PLZ

PHZ

PZH

0 V

001aae464

Measurements points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 6. Enable and disable times

nCP input

GND

nDn input

GND

nQn output

001aaa257

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 7. Data set-up and hold times

Table 8. Measurement points

Input

V_M

Output

V_M

V_X

V_Y

1.5 V

V_OL+ 0.3 V

V_OH- 0.3 V

74LVT_LVTH16374A

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Product data sheet

Rev. 12 — 6 August 2021

8 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

EXT

PULSE

GENERATOR

DUT

001aae235

Test data is given in Table 9.

Definitions test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= Test voltage for switching times.

Fig. 8. Test circuit for measuring switching times

Table 9. Test data

Input

V_I

Load

C_L

V_EXT

f_i

t_W

t_r, t_f

R_L

t_PHZ, t_PZH

GND

t_PLZ, t_PZL

t_PLH, t_PHL

2.7 V

≤ 10 MHz

500 ns

≤ 2.5 ns

50 pF

500 Ω

6 V

open

74LVT_LVTH16374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 12 — 6 August 2021

9 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

11. Package outline

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

(A )

pin 1 index

detail X

5 mm

2.5

scale

Dimensions (mm are the original dimensions)

Unit

max

(1)

(2)

0.15 1.05

0.05 0.85

0.28 0.2 12.6 6.2

0.17 0.1 12.4 6.0

8.3

7.9

0.8 0.50

0.4 0.35

0.8

0.4

mm nom 1.2

min

0.25

0.5

0.25 0.08 0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

sot362-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

03-02-19

13-08-05

SOT362-1

MO-153

Fig. 9. Package outline SOT362-1 (TSSOP48)

74LVT_LVTH16374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 12 — 6 August 2021

10 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

BiCMOS

DUT

Bipolar Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date

20210806

Data sheet status

Change notice Supersedes

- 74LVT_LVTH16374A v.11

74LVT_LVTH16374A v.12

Modifications:

Product data sheet

•

Type number 74LVT16374ADL (SOT370-1/SSOP48) removed.

Section 1 and Section 2 updated.

Section 7: Derating value for P_tottotal power dissipation removed.

74LVT_LVTH16374A v.11

Modifications:

20190205

Product data sheet

74LVT_LVTH16374A v.10

•

The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Type numbers 74LVT16374AEV (SOT702-1) and

74LVTH16374ABX (SOT1134-2) removed.

•

Package outline drawing SOT362-1 (TSSOP48) updated.

74LVT_LVTH16374A v.10

Modifications:

20120402

Product data sheet

74LVT_LVTH16374A v.9

•

For type number 74LVTH16374ABX the sot code has changed to SOT1134-2.

74LVT_LVTH16374A v.9

Modifications:

20111122

Product data sheet

74LVT_LVTH16374A v.8

•

Legal pages updated.

74LVT_LVTH16374A v.8

74LVT_LVTH16374A v.7

74LVT_LVTH16374A v.6

74LVT16374A v.5

20110620

20100322

20100118

20040916

20021101

19991018

19980219

Product data sheet

product data sheet

product specification

74LVT_LVTH16374A v.7

74LVT_LVTH16374A v.6

74LVT16374A v.5

74LVT16374A v.4

74LVT16374A v.3

74LVT16374A v.2

74LVT16374A v.4

74LVT16374A v.3

74LVT16374A v.2

74LVT_LVTH16374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 12 — 6 August 2021

11 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

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with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

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sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

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Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74LVT_LVTH16374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 12 — 6 August 2021

12 / 13

Nexperia

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description.............................................................3

6. Functional description................................................. 4

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................5

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 6

10.1. Waveforms and test circuit........................................ 7

11. Package outline........................................................ 10

12. Abbreviations............................................................11

13. Revision history........................................................11

14. Legal information......................................................12

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 6 August 2021

74LVT_LVTH16374A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 12 — 6 August 2021

13 / 13

74LVT16374ADGG [NEXPERIA]

相关型号：

74LVT16374ADGG,112

74LVT16374ADGG,118

74LVT16374ADGG,512

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74LVT16374ADL

74LVT16374ADL,112

74LVT16374ADL-T

74LVT16374AEV

74LVT16374AEV,118

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74LVT16374AEV/G,51