74LVTN16245BDGG [NEXPERIA]
3.3 V 16-bit transceiver; 3-stateProduction;型号: | 74LVTN16245BDGG |
厂家: | Nexperia |
描述: | 3.3 V 16-bit transceiver; 3-stateProduction 驱动 信息通信管理 光电二极管 逻辑集成电路 |
文件: | 总13页 (文件大小:207K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
Rev. 6 — 30 October 2018
Product data sheet
1. General description
The 74LVTN16245B is a high-performance BiCMOS product designed for VCC operation at 3.3 V.
This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both
send and receive directions. The control function implementation minimizes external timing
requirements. The device features an output enable input (nOE) for easy cascading and a direction
input (nDIR) for direction control.
2. Features and benefits
•
•
16-bit bus interface
3-state buffers
•
•
•
•
•
•
•
Output capability: +64 mA and -32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Power-up 3-state
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Latch-up protection
•
JESD78B Class II exceeds 500 mA
•
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVTN16245BDGG -40 °C to +85 °C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
4. Functional diagram
2DIR
1DIR
2OE
2B0
2B1
2B2
2B3
2B4
2B5
2B6
1OE
1B0
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B7
001aaa789
Fig. 1. Logic symbol
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
2 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
1OE
G3
1DIR
3EN1[BA]
3EN2[AB]
G6
2OE
2DIR
6EN4[BA]
6EN5[AB]
1A0
1
1B0
2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
4
5
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aak306
Fig. 2. IEC logic symbol
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
3 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
5. Pinning information
5.1. Pinning
74LVTN16245B
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B0
1B1
GND
1B2
1B3
1OE
1A0
1A1
GND
1A2
1A3
2
3
4
5
6
7
V
V
CC
CC
8
1B4
1B5
GND
1B6
1B7
2B0
2B1
GND
2B2
2B3
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CC
CC
2B4
2B5
2A4
2A5
GND
2A6
2A7
2OE
GND
2B6
2B7
2DIR
001aak307
Fig. 3. Pin configuration SOT362-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1DIR, 2DIR
1, 24
direction control input
data input/output
data input/output
ground (0 V)
1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7
2, 3, 5, 6, 8, 9, 11, 12
2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
GND
VCC
supply voltage
1OE, 2OE
48, 25
output enable input (active LOW)
data input/output
data input/output
2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7
1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7
36, 35, 33, 32, 30, 29, 27, 26
47, 46, 44, 43, 41, 40, 38, 37
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
4 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Control
Input/output
nOE
L
nDIR
nAn
nBn
L
output nAn = nBn
input
L
H
X
input
Z
output nBn = nAn
Z
H
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-0.5
-50
-50
-
Max
+4.6
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
[1]
[1]
V
VO
IIK
output voltage
output in OFF-state or HIGH-state
VI < 0 V
V
input clamping current
output clamping current
output current
mA
mA
mA
mA
°C
IOK
IO
VO < 0 V
-
output in LOW-state
output in HIGH-state
128
-
-64
-65
-
Tstg
Tj
storage temperature
junction temperature
total power dissipation
+150
150
500
[2]
[3]
°C
Ptot
Tamb = -40 °C to +85 °C
-
mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
2.7
0
Typ
Max
3.6
5.5
-
Unit
V
VCC
VI
supply voltage
-
-
-
-
-
-
-
input voltage
V
VIH
VIL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
2.0
-
V
0.8
-
V
-32
-
mA
mA
mA
none
32
64
current duty cycle ≤ 50 %;
fi ≥ 1 kHz
-
Tamb
ambient temperature
in free-air
-40
-
-
-
+85
10
°C
Δt/ΔV
input transition rise and fall rate
outputs enabled
ns/V
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
5 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; Tamb = -40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC = 2.7 V; IIK = -18 mA
HIGH-level output voltage IOH = -100 μA; VCC = 2.7 V to 3.6 V
IOH = -8 mA; VCC = 2.7 V
IOH = -32 mA; VCC = 3.0 V
LOW-level output voltage VCC = 2.7 V
IOL = 100 μA
Min
-1.2
Typ [1]
-0.85
VCC
Max
Unit
V
VIK
input clamping voltage
-
-
-
-
VOH
VCC - 0.2
2.4
V
2.5
V
2.0
2.3
V
VOL
-
-
0.07
0.3
0.2
0.5
V
V
IOL = 24 mA
VCC = 3.0 V
IOL = 16 mA
-
-
-
0.25
0.3
0.4
0.5
V
V
V
IOL = 32 mA
IOL = 64 mA
0.4
0.55
II
input leakage current
control pins
VCC = 3.6 V; VI = VCC or GND
-
-
0.1
0.1
±1
10
μA
μA
VCC = 0 V or 3.6 V; VI = 5.5 V
input/output data pins; VCC = 3.6 V
[2]
VI = 5.5 V
VI = VCC
VI = 0 V
-
-
0.1
0.5
-0.1
0.1
75
20
10
μA
μA
μA
μA
μA
-5
-
-
IOFF
ILO
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
±100
125
output leakage current
output in HIGH-state when VO > VCC
;
-
VO = 5.5 V; VCC = 3.0 V
IO(pu/pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC; nOE = don’t care
;
[3]
-
40
±100
μA
ICC
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
output HIGH
-
-
-
-
0.07
4.0
0.12
6.0
mA
mA
mA
mA
output LOW
outputs disabled
[4]
[5]
0.07
0.1
0.12
0.2
ΔICC
additional supply current per input pin; VCC = 3.0 V to 3.6 V;
one input at VCC - 0.6 V,
other inputs at VCC or GND
CI
input capacitance
pins nDIR and nOE, VO = 0 V or 3.0 V
-
-
3
9
-
-
pF
pF
Cio(off)
off-state input/output
capacitance
pins nAn and nBn, outputs disabled;
VO = GND or VCC
[1] Typical values are measured at VCC = 3.3 V and at Tamb = 25 °C.
[2] Unused pins at VCC or GND.
[3] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.
From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.
[4] ICC is measured with outputs pulled to VCC or GND.
[5] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
6 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); Tamb = -40 °C to +85 °C; for test circuit see Fig. 6.
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
LOW to HIGH
propagation delay
nAn to nBn or nBn to nAn; see Fig. 4
VCC = 2.7 V
-
-
3.5
3.3
ns
ns
VCC = 3.0 V to 3.6 V
nAn to nBn or nBn to nAn; see Fig. 4
VCC = 2.7 V
1.0
1.9
HIGH to LOW
propagation delay
-
-
3.5
3.3
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nAn or nBn; see Fig. 5
VCC = 2.7 V
1.0
1.7
OFF-state to HIGH
propagation delay
-
-
5.3
4.5
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nAn or nBn; see Fig. 5
VCC = 2.7 V
1.0
2.8
OFF-state to LOW
propagation delay
-
-
5.1
4.1
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nAn or nBn; see Fig. 5
VCC = 2.7 V
1.0
2.8
HIGH to OFF-state
propagation delay
-
-
5.7
5.1
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nAn or nBn; see Fig. 5
VCC = 2.7 V
1.5
3.2
LOW to OFF-state
propagation delay
-
-
4.6
4.6
ns
ns
VCC = 3.0 V to 3.6 V
1.5
3.0
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
7 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
10.1. Waveforms and test circuit
V
I
nAn, nBn
input
V
M
GND
t
t
PHL
PLH
V
OH
nBn, nAn
output
V
M
mna477
V
OL
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 4. Propagation delay input (nAn, nBn) to output (nBn, nAn)
V
I
nOE input
V
M
t
0 V
t
PZL
PLZ
3.0 V
nAn or nBn
output
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
nBn or nAn
output
V
M
0 V
001aaj658
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 5. Enable and disable times
Table 8. Measurement points
Input
Output
VM
VM
VX
VY
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
8 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 6. Test circuit for measuring switching times
Table 9. Test data
Input
VI
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH
GND
tPLZ, tPZL
tPLH, tPHL
2.7 V
≤ 10 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
6 V
open
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
9 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
11. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
max
(1)
(2)
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
0.4
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Fig. 7. Package outline SOT362-1 (TSSOP48)
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
10 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
BiCMOS
DUT
Bipolar Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date
20181030
Data sheet status
Change notice Supersedes
- 74LVTN16245B v.5
74LVTN16245B v.6
Modifications:
Product data sheet
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type numbers 74LVTN16245BBX (SOT1134-2) removed.
Package outline drawing SOT362-1 updated.
74LVTN16245B v.5
Modifications:
20120405
Product data sheet
-
74LVTN16245B v.4
•
For type number 74LVTN16245BBX the SOT code has changed to SOT1134-2
74LVTN16245B v.4
Modifications:
20111122
Product data sheet
-
74LVTN16245B v.3
•
Legal pages updated.
74LVTN16245B v.3
74LVTN16245B v.2
74LVTN16245B v.1
20110615
20100323
20090729
Product data sheet
Product data sheet
Product data sheet
-
-
-
74LVTN16245B v.2
74LVTN16245B v.1
-
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
11 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
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or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
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Trademarks
Suitability for use — Nexperia products are not designed, authorized or
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©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
12 / 13
Nexperia
74LVTN16245B
3.3 V 16-bit transceiver; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................4
5.1. Pinning.........................................................................4
5.2. Pin description.............................................................4
6. Functional description................................................. 5
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 8
11. Package outline........................................................ 10
12. Abbreviations............................................................11
13. Revision history........................................................11
14. Legal information......................................................12
© Nexperia B.V. 2018. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 30 October 2018
©
74LVTN16245B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 6 — 30 October 2018
13 / 13
相关型号:
74LVU04BQ
IC LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-762-1, DHVQFN-14, Gate
NXP
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