HEF4011BT [NEXPERIA]
Quad 2-input NAND gateProduction;
| 型号： | HEF4011BT |
| 厂家： | 
Nexperia |
| 描述： | Quad 2-input NAND gateProduction 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：969K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4011B
Quad 2-input NAND gate
Rev. 6 — 10 December 2015
Product data sheet
1. General description
The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the
highest noise immunity and pattern insensitivity to output impedance.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
Inputs and outputs are protected against electrostatic effects
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C
Type number Package
Name
Description
Version
HEF4011BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
4. Functional diagram
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Fig 1. Functional diagram
Fig 2. Logic diagram (one gate)
HEF4011B
Nexperia
Quad 2-input NAND gate
5. Pinning information
5.1 Pinning
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Fig 3. Pin configuration
5.2 Pin description
Table 2.
Symbol
nA
Pin description
Pin
Description
1, 5, 8, 12
2, 6, 9, 13
input
nB
input
nY
3, 4, 10, 11
output
VSS
7
ground (0 V)
supply voltage
VDD
14
6. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
L
nY
H
L
H
L
H
H
H
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level.
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
2 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min
0.5
-
Max
+18
Unit
V
VDD
IIK
supply voltage
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
10
mA
V
VI
0.5
-
VDD + 0.5
10
IOK
II/O
output clamping current
input/output current
supply current
mA
mA
mA
C
-
10
IDD
Tstg
Tamb
Ptot
-
50
storage temperature
ambient temperature
total power dissipation
65
40
+150
+125
C
Tamb = 40 C to + 125 C
SO14
[1]
-
-
500
100
mW
mW
P
power dissipation
per output
[1] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
supply voltage
3
-
-
-
-
-
-
V
VI
input voltage
0
VDD
+125
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
40
C
t/V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
s/V
s/V
s/V
0.08
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
3 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
9. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit
Min
Max
Min
Max
-
Min
Max
Min
Max
VIH
HIGH-level
input voltage
IO < 1 A
IO < 1 A
IO < 1 A
IO < 1 A
5 V
3.5
-
-
3.5
3.5
-
-
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V
15 V
5 V
7.0
7.0
-
7.0
7.0
11.0
-
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level
output voltage
4.95
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
14.95
-
LOW-level
output voltage
-
0.05
0.05
0.05
1.7
0.64
1.6
4.2
-
-
0.05
0.05
0.05
1.4
0.5
1.3
3.4
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
-
-
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
-
-
1.1 mA
0.36 mA
0.9 mA
2.4 mA
5 V
-
-
-
-
-
-
10 V
15 V
5 V
-
-
-
-
-
IOL
LOW-level
output current
0.64
1.6
4.2
-
0.5
1.3
3.4
-
0.36
0.9
2.4
-
0.36
0.9
2.4
-
-
-
-
mA
mA
mA
10 V
15 V
15 V
-
-
-
-
-
-
II
input leakage
current
0.1
0.1
1.0
1.0 A
IDD
supply current all valid input 5 V
combinations;
-
-
-
-
0.25
0.5
1.0
-
-
-
-
-
0.25
0.5
-
-
-
-
7.5
15.0
30.0
-
-
-
-
-
7.5 A
10 V
15 V
15.0 A
30.0 A
IO = 0 A
1.0
CI
input
7.5
-
pF
capacitance
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
4 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 C; for waveforms see Figure 4; for test circuit see Figure 5; unless otherwise specified.
Symbol Parameter
tpd propagation delay
Extrapolation formula[1]
28 + 0.55 CL
VDD
5 V
Min
Typ
55
25
20
60
30
20
60
30
20
Max Unit
110 ns
45 ns
35 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
[2]
-
-
-
-
-
-
-
-
-
14 + 0.23 CL
10 V
15 V
5 V
12 + 0.16 CL
tTHL
HIGH to LOW output transition time 10 + 1.00 CL
9 + 0.42 CL
10 V
15 V
5 V
6 + 0.28 CL
LOW to HIGH output transition time 10 + 1.00 CL
9 + 0.42 CL
tTLH
10 V
15 V
6 + 0.28 CL
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
[2]
t
pd is the same as tPLH and tPHL
.
Table 8.
Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD Typical formula
Where
PD
dynamic power dissipation
5 V PD = 1300 fi + (fo CL) VDD2 (W) fi = input frequency in MHz;
10 V PD = 6000 fi + (fo CL) VDD2 (W)
fo = output frequency in MHz;
15 V PD = 20100 fi + (fo CL) VDD2 (W)
CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
5 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
11. Waveforms
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Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4. Propagation delay, output transition time
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
9
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9
9
2
,
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Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 5. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
Input
Load
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
20 ns
50 pF
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
6 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
12. Package outline
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Fig 6. Package outline SOT108-1 (SO14)
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
7 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
Device Under Test
DUT
14. Revision history
Table 12. Revision history
Document ID
HEF4011B v.6
Modifications:
HEF4011B v.5
Modifications:
Release date
20151210
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4011B v.5
• Type number HEF4011BP (SOT27-1) removed.
20111121 Product data sheet
• Legal pages updated.
-
HEF4011B v.4
• Changes in “General description” and “Features and benefits”.
• Section “Applications” removed.
HEF4011B v.4
20110330
19950101
19950101
Product data sheet
Product specification
Product specification
-
-
-
HEF4011B_CNV v.3
HEF4011B_CNV v.3
HEF4011B_CNV v.2
HEF4011B_CNV v.2
-
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
8 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
Suitability for use — Nexperia products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
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malfunction of a Nexperia product can reasonably be expected
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the products or of the application or use by customer’s third party
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
9 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
HEF4011B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 10 December 2015
10 of 11
HEF4011B
Nexperia
Quad 2-input NAND gate
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
Functional description . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 8
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 10 December 2015
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