HEF4011UBPB [NXP]

IC 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDIP14, Gate;
HEF4011UBPB
型号: HEF4011UBPB
厂家: NXP    NXP
描述:

IC 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDIP14, Gate

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INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4011B  
gates  
Quadruple 2-input NAND gate  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
HEF4011B  
gates  
Quadruple 2-input NAND gate  
DESCRIPTION  
The HEF4011B provides the positive quadruple 2-input  
NAND function. The outputs are fully buffered for highest  
noise immunity and pattern insensitivity of output  
impedance.  
Fig.2 Pinning diagram.  
HEF4011BP(N):  
HEF4011BD(F):  
HEF4011BT(D):  
14-lead DIL; plastic  
(SOT27-1)  
14-lead DIL; ceramic (cerdip)  
(SOT73)  
Fig.1 Functional diagram.  
14-lead SO; plastic  
(SOT108-1)  
( ): Package Designator North America  
Fig.3 Logic diagram (one gate).  
FAMILY DATA, IDD LIMITS category GATES  
See Family Specifications  
January 1995  
2
Philips Semiconductors  
Product specification  
HEF4011B  
gates  
Quadruple 2-input NAND gate  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL  
TYP  
MAX  
Propagation delays  
5
55  
25  
20  
60  
30  
20  
60  
30  
20  
110  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
28 ns + (0,55 ns/pF) CL  
14 ns + (0,23 ns/pF) CL  
12 ns + (0,16 ns/pF) CL  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
10 ns + (1,0 ns/pF) CL  
9 ns + (0,42 ns/pF) CL  
6 ns + (0,28 ns/pF) CL  
In On  
10  
15  
5
tPHL; tPLH  
35  
Output transition times  
HIGH to LOW  
120  
60  
10  
15  
5
tTHL  
40  
120  
60  
LOW to HIGH  
10  
15  
tTLH  
40  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
1300 fi + ∑ (foCL) × VDD  
where  
2
10  
15  
6000 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
2
20 100 fi + ∑ (foCL) × VDD  
V
DD = supply voltage (V)  
January 1995  
3

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