HEF4015BT [NEXPERIA]
Dual 4-bit static shift registerProduction;
| 型号： | HEF4015BT |
| 厂家： | 
Nexperia |
| 描述： | Dual 4-bit static shift registerProduction 逻辑集成电路 |
| 文件： | 总11页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4015B
Dual 4-bit static shift register
Rev. 10 — 26 November 2021
Product data sheet
1. General description
The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each
shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs
(Q0 to Q3) and an overriding asynchronous master reset input (nMR). Information present on nD is
shifted to the first register position, and all the data in the register is shifted one position to the right
on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces Q0 to Q3 to
LOW, independent of nCP and nD. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VDD
.
2. Features and benefits
•
Wide supply voltage range from 3.0 V to 15.0 V
•
•
•
•
•
•
•
•
CMOS low power dissipation
High noise immunity
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
•
Specified from -40 °C to +85 °C
3. Applications
•
•
•
Serial-to-parallel converter
Buffer stores
General purpose register
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
-40 °C to +85 °C
Name
Description
Version
HEF4015BT
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
Nexperia
HEF4015B
Dual 4-bit static shift register
5. Functional diagram
1Q0
1Q1
1Q2
5
4
3
7
1D
SHIFT
REGISTER
4 BITS
9
6
1CP
1MR
1Q3 10
2Q0 13
2Q1 12
2Q2 11
15 2D
SHIFT
REGISTER
4 BITS
1
2CP
2Q3
2
14 2MR
001aae560
Fig. 1. Functional diagram
Q0
Q1
Q2
Q3
D
D
Q
D
Q
D
Q
D
Q
FF 1
CP
CD
FF 2
CP
CD
FF 3
FF 4
CP
CD
CP
CD
CP
MR
001aae562
Fig. 2. Logic diagram for one register
6. Pinning information
6.1. Pinning
HEF4015B
1
2
3
4
5
6
7
8
16
V
2CP
2Q3
1Q2
1Q1
1Q0
1MR
1D
DD
15
14
13
12
11
10
9
2D
2MR
2Q0
2Q1
2Q2
1Q3
1CP
V
SS
001aae561
Fig. 3. Pin configuration for SOT109-1 (SO16)
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
2 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
6.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
parallel output
parallel output
1Q0, 1Q1, 1Q2, 1Q3
2Q0, 2Q1, 2Q2, 2Q3
1MR, 2MR
1D, 2D
5, 4, 3, 10
13, 12, 11, 2
6, 14
7, 15
8
master reset input (active HIGH)
serial data input
VSS
ground supply voltage
1CP, 2CP
9, 1
16
clock input (LOW-to-HIGH edge-triggered)
supply voltage
VDD
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Dn = either HIGH or LOW;
↑ = positive-going transition; ↓= negative-going transition.
number of clock
pulse transitions
Input
Output
CP
↑
D
MR
L
Q0
Q1
Q2
Q3
1
2
3
4
D1
D2
D3
D4
X
D1
X
X
X
↑
L
D2
D1
X
X
↑
L
D3
D2
D1
X
↑
L
D4
D3
D2
D1
↓
L
no change
L
no change
L
no change
L
no change
L
X
X
H
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
Max
+18
Unit
supply voltage
-0.5
V
input clamping current
input voltage
VI < -0.5 V or VI > VDD + 0.5 V
VO < -0.5 V or VO > VDD + 0.5 V
-
±10
mA
V
VI
-0.5
VDD + 0.5
±10
IOK
output clamping current
input/output current
supply current
-
mA
mA
mA
°C
II/O
-
-
±10
IDD
50
Tstg
Tamb
Ptot
P
storage temperature
ambient temperature
total power dissipation
power dissipation
-65
-40
-
+150
+85
°C
Tamb = -40 °C to +85 °C
per output
500
mW
mW
-
100
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
3 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
VDD
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
0
-
-
-
-
-
-
VI
input voltage
VDD
+85
3.75
0.5
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
in free air
-40
-
°C
VDD = 5 V
VDD = 10 V
VDD = 15 V
μs/V
μs/V
μs/V
-
-
0.08
10. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = -40 °C
Tamb = 25 °C
Tamb = 85 °C Unit
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level input voltage
|IO| < 1 μA
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V
15 V
5 V
7.0
-
7.0
-
7.0
11.0
-
11.0
-
11.0
-
VIL
LOW-level input voltage
|IO| < 1 μA
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level output voltage |IO| < 1 μA
LOW-level output voltage |IO| < 1 μA
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
-
0.05
0.05
0.05
-1.7
-0.52
-1.3
-3.6
-
-
0.05
0.05
0.05
-1.4
-0.44
-1.1
-3.0
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
HIGH-level output current VO = 2.5 V
-
-
-
-1.1 mA
-0.36 mA
-0.9 mA
-2.4 mA
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
5 V
-
-
-
10 V
15 V
5 V
-
-
-
-
-
-
IOL
LOW-level output current
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
0.52
0.44
0.36
-
-
-
mA
mA
mA
10 V
15 V
15 V
5 V
1.3
-
1.1
-
0.9
3.6
-
3.0
-
2.4
II
input leakage current
supply current
-
-
-
-
-
±0.3
20
40
80
-
-
-
-
-
-
±0.3
20
40
80
7.5
-
-
-
-
-
±1.0 μA
150 μA
300 μA
600 μA
IDD
IO = 0 A
10 V
15 V
-
CI
input capacitance
-
pF
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
4 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
11. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; CL = 50 pF; Tamb = 25 °C; for test circuit see Fig. 7.
Symbol Parameter
Conditions
VDD
Extrapolation formula [1] Min
Typ
130
55
40
105
45
35
120
55
40
60
30
20
-15
-10
-5
Max Unit
260 ns
110 ns
80 ns
210 ns
90 ns
70 ns
240 ns
110 ns
80 ns
120 ns
60 ns
40 ns
tPHL
HIGH to LOW
nCP to Qn;
see Fig. 4
5 V
103 ns + (0.55 ns/pF)CL
-
-
propagation delay
10 V 44 ns + (0.23 ns/pF)CL
15 V 32 ns + (0.16 ns/pF)CL
-
nMR to Qn;
see Fig. 6
5 V
78 ns + (0.55 ns/pF)CL
-
10 V 34 ns + (0.23 ns/pF)CL
15 V 27 ns + (0.16 ns/pF)CL
-
-
tPLH
LOW to HIGH
nCP to Qn;
see Fig. 4
5 V
93 ns + (0.55 ns/pF)CL
-
propagation delay
10 V 44 ns + (0.23 ns/pF)CL
15 V 32 ns + (0.16 ns/pF)CL
-
-
tt
transition time
set-up time
hold time
see Fig. 4
5 V
10 ns + (1.00 ns/pF)CL
-
10 V 9 ns + (0.42 ns/pF)CL
-
15 V 6 ns + (0.28 ns/pF)CL
-
tsu
nD to nCP;
see Fig. 5
5 V
+25
+25
+20
40
20
15
60
30
20
80
30
24
50
30
20
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
10 V
15 V
5 V
ns
ns
th
nD to nCP;
see Fig. 5
20
10
8
ns
10 V
15 V
5 V
ns
ns
tW
pulse width
nCP LOW;
minimum width;
see Fig. 5
30
15
10
40
15
12
20
10
5
ns
10 V
15 V
5 V
ns
ns
nMR HIGH;
minimum width;
see Fig. 6
ns
10 V
15 V
ns
ns
trec
recovery time
pin nMR; see Fig. 6 5 V
10 V
ns
ns
15 V
5 V
ns
fmax
maximum frequency see Fig. 5
15
30
44
MHz
MHz
MHz
10 V
15 V
15
22
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (μW)
PD = 1500 × fi + Σ(fo × CL) × VDD
PD = 6300 × fi + Σ(fo × CL) × VDD
where:
2
2
PD
dynamic power
dissipation
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
10 V
15 V
2
PD = 17000 × fi + Σ(fo × CL) × VDD
Σ(CL × fo) = sum of the outputs.
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
5 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
11.1. Waveforms and test circuit
V
I
V
nCP input
M
V
SS
t
t
PLH
PHL
V
OH
90 %
V
nQn output
M
10 %
V
OL
t
t
t
t
001aaj464
Measurement points are given in Table 9.
Fig. 4. Waveforms showing nCP propagation delays and nQn transition times
t
W
V
I
nCP input
V
V
V
M
M
M
V
SS
1/f
max
t
t
h
h
V
I
nD input
V
V
V
V
M
M
M
M
V
SS
t
t
su
su
001aae563
The shaded area indicates where the input is permitted to change for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Fig. 5. Waveforms showing set-up times, hold times, and minimum clock pulse width
V
I
V
V
M
nMR input
nCP input
M
V
V
SS
t
W
t
rec
V
I
V
M
SS
t
PHL
V
OH
nQn output
V
M
V
OL
001aae564
Measurement points are given in Table 9.
Fig. 6. Waveforms showing MR recovery time, propagation delay and minimum pulse width
Table 9. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
6 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
t
W
V
I
90 %
90 %
negative
pulse
V
V
V
M
M
10 %
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
90 %
positive
pulse
V
M
M
10 %
10 %
0 V
t
W
001aaj781
a. Input waveforms
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance;
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig. 7. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
7 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 8. Package outline SOT109-1 (SO16)
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
8 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MM
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
14. Revision history
Table 12. Revision history
Document ID
HEF4015B v.10
Modifications:
Release date
20211126
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4015B v.9
•
Section 1 and Section 2 updated.
HEF4015B v.9
Modifications:
20160321 Product data sheet
-
HEF4015B v.8
HEF4015B v.7
•
Type number HEF4015BP (SOT38-4) removed.
20111121 Product data sheet
Legal pages updated.
Changes in "General description" and "Features and benefits".
HEF4015B v.8
Modifications:
-
•
•
HEF4015B v.7
20110914
20091103
20090624
20090127
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
-
-
HEF4015B v.6
HEF4015B v.5
HEF4015B v.4
HEF4015B_CNV v.3
HEF4015B_CNV v.2
-
HEF4015B v.6
HEF4015B v.5
HEF4015B v.4
HEF4015B_CNV v.3
HEF4015B_CNV v.2
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
9 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
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and products using Nexperia products, and Nexperia accepts no liability for
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Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
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or problem which is based on any weakness or default in the customer’s
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[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
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the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
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with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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data sheet shall define the specification of the product as agreed between
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to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
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accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
10 / 11
Nexperia
HEF4015B
Dual 4-bit static shift register
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 6
12. Package outline.......................................................... 8
13. Abbreviations..............................................................9
14. Revision history..........................................................9
15. Legal information......................................................10
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 26 November 2021
©
HEF4015B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 10 — 26 November 2021
11 / 11
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