HEF4027BT [NEXPERIA]
Dual JK flip-flopProduction;型号: | HEF4027BT |
厂家: | Nexperia |
描述: | Dual JK flip-flopProduction 光电二极管 逻辑集成电路 触发器 |
文件: | 总11页 (文件大小:215K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HEF4027B
Dual JK flip-flop
Rev. 11 — 7 December 2021
Product data sheet
1. General description
The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD),
clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted
when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The
asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK,
and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower
clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VDD
.
2. Features and benefits
•
Wide supply voltage range from 3.0 V to 15.0 V
•
•
•
•
•
•
•
CMOS low power dissipation
High noise immunity
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
•
Specified from -40 °C to +85 °C
3. Applications
•
•
•
Registers
Counters
Control circuits
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
-40 °C to +85 °C
Name
Description
Version
HEF4027BT
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
Nexperia
HEF4027B
Dual JK flip-flop
5. Functional diagram
FF 1
1SD
9
10
13
11
1J
1Q
1Q
15
14
1CP
1K
1CD
12
7
FF 2
2SD
6
3
5
2J
2Q
2Q
1
2
2CP
2K
2CD
4
001aae593
Fig. 1. Functional diagram
CP
Q
C
C
C
C
C
C
C
C
C
J
C
Q
K
CD
SD
001aae595
Fig. 2. Logic diagram of one flip-flop
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
2 / 11
Nexperia
HEF4027B
Dual JK flip-flop
6. Pinning information
6.1. Pinning
HEF4027B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Q
2Q
V
DD
1Q
2CP
2CD
2K
1Q
1CP
1CD
1K
2J
2SD
1J
V
1SD
SS
001aae594
Fig. 3. Pin configuration SOT109-1 (SO16)
6.2. Pin description
Table 2. Pin description
Symbol
VSS
Pin
Description
ground supply voltage
8
1SD, 2SD
1J, 2J
9, 7
asynchronous set-direct input (active HIGH)
synchronous input
10, 6
11, 5
12, 4
13, 3
14, 2
15, 1
16
1K, 2K
1CD, 2CD
1CP, 2CP
1Q, 2Q
1Q, 2Q
VDD
synchronous input
asynchronous clear-direct input (active HIGH)
clock input (LOW-to-HIGH edge-triggered)
complement output
true output
supply voltage
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.; ↑ = positive-going transition.
Inputs
Outputs
nSD
H
L
nCD
L
nCP
X
nJ
X
X
X
L
nK
X
nQ
nQ
H
L
H
H
L
X
X
L
H
H
L
X
X
H
H
↑
L
no change
no change
L
L
↑
H
L
L
H
L
L
L
↑
H
H
L
H
L
L
↑
H
nQ
nQ
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
3 / 11
Nexperia
HEF4027B
Dual JK flip-flop
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
Max
+18
Unit
V
supply voltage
-0.5
input clamping current
input voltage
VI < -0.5 V or VI > VDD + 0.5 V
VO < -0.5 V or VO > VDD + 0.5 V
-
±10
mA
V
VI
-0.5
VDD + 0.5
±10
IOK
output clamping current
input/output current
supply current
-
mA
mA
mA
°C
II/O
-
-
±10
IDD
50
Tstg
Tamb
Ptot
P
storage temperature
ambient temperature
total power dissipation
power dissipation
-65
-40
-
+150
+85
in free air
°C
Tamb -40 °C to +85 °C
per output
500
mW
mW
-
100
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
VDD
Parameter
Conditions
Min
Max
15
Unit
V
supply voltage
3
0
VI
input voltage
VDD
+85
3.75
0.5
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
in free air
-40
-
°C
VDD = 5 V
VDD = 10 V
VDD = 15 V
μs/V
μs/V
μs/V
-
-
0.08
10. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit
Min
Max
Min
Max
Min
Max
VIH
HIGH-level input voltage
|IO| < 1 μA
5 V
3.5
-
-
3.5
-
-
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
10 V
15 V
5 V
7.0
7.0
7.0
11.0
-
11.0
-
11.0
-
VIL
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
VOL
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
10 V
15 V
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
4 / 11
Nexperia
HEF4027B
Dual JK flip-flop
Symbol Parameter
Conditions
VDD
Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit
Min
Max
-1.7
-0.52
-1.3
-3.6
-
Min
Max
-1.4
-0.44
-1.1
-3.0
-
Min
Max
IOH
HIGH-level output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
5 V
-
-
-
-1.1 mA
-0.36 mA
-0.9 mA
-2.4 mA
5 V
-
-
-
10 V
15 V
5 V
-
-
-
-
-
-
IOL
LOW-level output current
0.52
0.44
0.36
-
-
-
mA
mA
mA
10 V
15 V
15 V
5 V
1.3
-
1.1
-
0.9
3.6
-
3.0
-
2.4
II
input leakage current
supply current
-
-
-
-
-
±0.3
4.0
8.0
16.0
-
-
-
-
-
-
±0.3
4.0
8.0
16.0
7.5
-
-
-
-
-
±1.0 μA
30 μA
60 μA
120 μA
IDD
IO = 0 A
10 V
15 V
-
CI
input capacitance
-
pF
11. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C unless otherwise specified; for test circuit see Fig. 7.
Symbol Parameter
tPHL HIGH to LOW
Conditions
VDD
5 V
Extrapolation formula [1]
78 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
22 ns + (0.16 ns/pF)CL
93 ns + (0.55 ns/pF)CL
33 ns + (0.23 ns/pF)CL
27 ns + (0.16 ns/pF)CL
113 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
58 ns + (0.55 ns/pF)CL
27 ns + (0.23 ns/pF)CL
22 ns + (0.16 ns/pF)CL
48 ns + (0.55 ns/pF)CL
24 ns + (0.23 ns/pF)CL
17 ns + (0.16 ns/pF)CL
43 ns + (0.55 ns/pF)CL
19 ns + (0.23 ns/pF)CL
17 ns + (0.16 ns/pF)CL
[2] 10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min
Typ
Max Unit
210 ns
80 ns
60 ns
240 ns
90 ns
70 ns
280 ns
110 ns
80 ns
170 ns
70 ns
60 ns
150 ns
70 ns
50 ns
140 ns
60 ns
50 ns
120 ns
60 ns
40 ns
CP → Q, Q;
-
-
105
40
30
120
45
35
140
55
40
85
35
30
75
35
25
70
30
25
60
30
20
25
10
5
propagation delay see Fig. 4
10 V
15 V
5 V
-
CD → Q;
see Fig. 4
-
10 V
15 V
5 V
-
-
SD → Q;
see Fig. 4
-
10 V
15 V
5 V
-
-
tPLH
LOW to HIGH
CP → Q, Q;
-
propagation delay see Fig. 4
10 V
15 V
5 V
-
-
CD → Q;
see Fig. 4
-
10 V
15 V
5 V
-
-
SD → Q;
see Fig. 4
-
10 V
15 V
5 V
-
-
tt
transition time
set-up time
see Fig. 4
-
10 V
15 V
5 V
-
-
tsu
J, K → CP;
see Fig. 5
50
30
20
-
-
-
ns
ns
ns
10 V
15 V
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
5 / 11
Nexperia
HEF4027B
Dual JK flip-flop
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula [1]
Min
25
Typ
0
Max Unit
th
hold time
J, K → CP;
see Fig. 5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
10 V
15 V
5 V
20
0
ns
15
5
ns
tW
pulse width
CP LOW;
minimum width;
see Fig. 5
80
40
15
12
45
20
15
-15
-10
-5
ns
10 V
15 V
5 V
30
ns
24
ns
SD, CD HIGH;
minimum width;
see Fig. 6
90
ns
10 V
15 V
40
ns
30
ns
trec
recovery time
SD, CD inputs; 5 V
see Fig. 6
+20
+15
+10
4
ns
10 V
ns
15 V
5 V
ns
fmax
maximum
frequency
CP input;
J = K = HIGH;
see Fig. 5
8
MHz
MHz
MHz
10 V
15 V
12
25
30
15
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] tt is the same as tTLH and tTHL
.
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (μW)
Where:
2
PD
dynamic power
dissipation
PD = 900 × fi + Σ(fo × CL) × VDD
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VDD = supply voltage in V
2
10 V
15 V
PD = 4500 × fi + Σ(fo × CL) × VDD
2
PD = 13200 × fi + Σ(fo × CL) × VDD
Σ(fo × CL) = sum of the outputs
11.1. Waveforms and test circuit
t
r
t
f
V
I
90 %
SD, CD or CP
INPUT
V
M
10 %
0 V
t
t
PHL
PLH
V
OH
90 %
Q or Q
OUTPUT
V
M
10 %
V
OL
t
t
TLH
THL
001aah863
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Fig. 4. Waveforms showing rise, fall, and transition times, and propagation delays
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
6 / 11
Nexperia
HEF4027B
Dual JK flip-flop
1/f
max
t
W
CP INPUT
J,K INPUT
V
M
t
h
V
M
t
su
001aae596
Measurement points are given in Table 9.
Fig. 5. Waveforms showing set-up times, hold times, and minimum clock pulse width
V
I
SD INPUT
0 V
V
M
t
W
V
I
V
CD INPUT
0 V
M
t
W
t
t
rec
rec
V
I
CP INPUT
0 V
V
M
V
OH
Q OUTPUT
V
OL
001aae597
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Fig. 6. Waveforms showing pulse widths and recovery times
Table 9. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data is given in Table 10.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig. 7. Test circuit
Table 10. Test data
Supply voltage
Input
Load
CL
VDD
VI
tr, tf
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
7 / 11
Nexperia
HEF4027B
Dual JK flip-flop
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 8. Package outline SOT109-1 (SO16)
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
8 / 11
Nexperia
HEF4027B
Dual JK flip-flop
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MM
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
14. Revision history
Table 12. Revision history
Document ID
HEF4027B v.11
Modifications:
Release date
20211207
Data sheet status
Change notice
Supersedes
HEF4027B v.10
Product data sheet
-
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Section 13 added.
HEF4027B v.10
Modifications:
20160321
Product data sheet
-
HEF4027B v.9
HEF4027B v.8
•
Type number HEF4027BP (SOT38-4) removed.
HEF4027B v.9
Modifications:
20111118
Product data sheet
-
•
•
Legal pages updated.
Changes in Section 1 and Section 2
HEF4027B v.8
20111010
20091125
20090624
20081110
20080703
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
-
-
-
-
-
-
-
HEF4027B v.7
HEF4027B v.6
HEF4027B v.5
HEF4027B v.4
HEF4027B_CNV v.3
HEF4027B_CNV v.2
-
HEF4027B v.7
HEF4027B v.6
HEF4027B v.5
HEF4027B v.4
HEF4027B_CNV v.3
HEF4027B_CNV v.2
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
9 / 11
Nexperia
HEF4027B
Dual JK flip-flop
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
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Suitability for use — Nexperia products are not designed, authorized or
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©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
10 / 11
Nexperia
HEF4027B
Dual JK flip-flop
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................5
11.1. Waveforms and test circuit........................................ 6
12. Package outline.......................................................... 8
13. Abbreviations..............................................................9
14. Revision history..........................................................9
15. Legal information......................................................10
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 7 December 2021
©
HEF4027B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 11 — 7 December 2021
11 / 11
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