NCA9535PW [NEXPERIA]

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registersProduction;


型号：	NCA9535PW
厂家：	Nexperia
描述：	Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registersProduction
文件：	总29页 (文件大小：418K)
中文：	中文翻译
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NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander

with interrupt output and configuration registers

Rev. 1 — 31 March 2023

Product data sheet

1. General description

The NCA9535 provides 16 bits of General Purpose Input/Output (GPIO) expansion for

I²C-bus/SMBus applications. It is designed for a wide voltage range of 1.65 V to 5.5 V with

interrupt. Nexperia GPIO expanders provide an elegant solution when additional IOs are

needed while keeping the interconnections to a minimum, for example, in ACPI power switches,

sensors, push buttons, LEDs and fan control. The NCA9535 contains a set of 8 bit input, output,

configuration and polarity inversion registers. At power up all IOs default to inputs. Each IO can be

configured as either input or output by changing the corresponding bit in the configuration register.

The data for each input or output is stored in the corresponding input or output register. The polarity

inversion register can be programmed to invert the polarity of the input register. The NCA9535

has an open-drain interrupt output which is activated when any one of the GPIO changes from its

corresponding input port register state. The power on reset sets the registers to default values and

initializes the device state machine. The NCA9535 has three address pins A0, A1 and A2 which

can be used to configure the I²C bus slave address of the device. It allows up-to eight devices to

share the same I²C-bus/SMBus.

2. Features and benefits

•

I²C-bus to parallel port expander

•

Operating power supply voltage range of 1.65 V to 5.5 V

Low standby current consumption:

•

2.5 µA (maximum)

•

Schmitt-trigger action allows slow input transition and better switching noise immunity at the

SCL and SDA inputs

•

V_hys= 0.10 × V_CC(typical)

Noise filter on SCL and SDA inputs

•

5 V tolerant I/Os

16 I/O pins which power up configured in input state

Open-drain active LOW interrupt output (INT)

400 kHz Fast-mode I²C-bus

Internal power-on reset

No glitch on power-up

Latched outputs with 25 mA drive maximum capability for directly driving LEDs

Latch-up performance exceeds 100 mA per JESD78, Class II

ESD protection:

•

HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V

CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V

•

Package offered: TSSOP24

Specified from -40 °C to +85 °C

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

NCA9535PW

-40 °C to +85 °C

TSSOP24

plastic thin shrink small outline package; 24 leads;

body width 4.4 mm

SOT355-1

4. Block diagram

NCA9535

P1_0

P1_1

P1_2

8-bit

INPUT/

write pulse

P1_3

P1_4

P1_5

P1_6

OUTPUT

PORTS

read pulse

P1_7

SCL

SDA

INPUT

FILTER

I C-BUS/SMBus

CONTROL

P0_0

P0_1

P0_2

8-bit

INPUT/

OUTPUT

PORTS

P0_3

P0_4

P0_5

P0_6

POWER-ON

RESET

write pulse

read pulse

P0_7

GND

INT

FILTER

aaa-036326

Remark: All I/Os are set to inputs at reset.

Fig. 1. Block diagram of NCA9535

NCA9535

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Product data sheet

Rev. 1 — 31 March 2023

2 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

5. Pinning information

5.1. Pinning

PW package

SOT355-1 (TSSOP24)

INT

SDA

SCL

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

P0_6

P0_7

GND

P1_7

P1_6

P1_5

P1_4

P1_3

P1_2

P1_1

P1_0

aaa-035811

Fig. 2. Pin configuration SOT355-1 (TSSOP24)

5.2. Pin description

Table 2. Pin description

Symbol Pin

Type

Description

INT

Interrupt output. Connect to V_CCthrough a pull-up resistor

Address input 1. Connect directly to V_CCor GND

Address input 2. Connect directly to V_CCor GND

P0_0 [1]

P0_1 [1]

P0_2 [1]

P0_3 [1]

P0_4 [1]

P0_5 [1]

I/O

Parallel port I/O. Push-pull driver. At power on, P0_0 is configured as input

Parallel port I/O. Push-pull driver. At power on, P0_1 is configured as input

Parallel port I/O. Push-pull driver. At power on, P0_2 is configured as input

Parallel port I/O. Push-pull driver. At power on, P0_3 is configured as input

Parallel port I/O. Push-pull driver. At power on, P0_4 is configured as input

Parallel port I/O. Push-pull driver. At power on, P0_5 is configured as input

Parallel port I/O. Push-pull driver. At power on, P0_6 is configured as input

Parallel port I/O. Push-pull driver. At power on, P0_7 is configured as input

P0_6 [1] 10

P0_7 [1] 11

GND

power Ground

P1_0 [2] 13

P1_1 [2] 14

P1_2 [2] 15

P1_3 [2] 16

P1_4 [2] 17

P1_5 [2] 18

P1_6 [2] 19

P1_7 [2] 20

I/O

Parallel port I/O. Push-pull driver. At power on, P1_0 is configured as input

Parallel port I/O. Push-pull driver. At power on, P1_1 is configured as input

Parallel port I/O. Push-pull driver. At power on, P1_2 is configured as input

Parallel port I/O. Push-pull driver. At power on, P1_3 is configured as input

Parallel port I/O. Push-pull driver. At power on, P1_4 is configured as input

Parallel port I/O. Push-pull driver. At power on, P1_5 is configured as input

Parallel port I/O. Push-pull driver. At power on, P1_6 is configured as input

Parallel port I/O. Push-pull driver. At power on, P1_7 is configured as input

Address input 0. Connect directly to V_CCor GND

NCA9535

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Product data sheet

Rev. 1 — 31 March 2023

3 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

Symbol Pin

Type

Description

SCL

SDA

V_CC

Serial clock bus. Connect to V_CCthrough a pull-up resistor

Serial data bus. Connect to V_CCthrough a pull-up resistor.

I/O

power Supply voltage.

[1] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance inputs.

[2] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance inputs.

6. Functional description

For the block diagram of the NCA9535 see Fig. 1.

6.1. Device address

slave address

A2 A1 A0 R/W

fixed

hardware

selectable

002aaf819

Fig. 3. NCA9535 device address

A2, A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)

or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit of the slave

address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a

read operation, while a LOW (logic 0) selects a write operation.

6.2. Registers

6.2.1. Pointer register and command byte

Following the successful acknowledgement of the address byte, the bus master sends a command

byte, which is stored in the address pointer register of the NCA9535. The lower three bits of this

data byte state the operation (read or write) and the internal registers (Input, Output, Polarity

Inversion, or Configuration) that will be affected. This register is write only.

B7 B6 B5 B4 B3 B2 B1 B0

002aaf540

Fig. 4. Pointer register bits

NCA9535

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Product data sheet

Rev. 1 — 31 March 2023

4 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

Table 3. Command byte

Pointer register bits

B7 B6 B5 B4 B3 B2 B1 B0

Command byte Register

(hexadecimal)

Protocol

Power-up

default

00h

01h

02h

03h

04h

05h

06h

07h

Input port 0

read byte

xxxx xxxx [1]

xxxx xxxx

Input port 1

Output port 0

read/write byte 1111 1111

read/write byte 0000 0000

read/write byte 1111 1111

Output port 1

Polarity Inversion port 0

Polarity Inversion port 1

Configuration port 0

Configuration port 1

[1] The default value ‘X’ is determined by the externally applied logic level.

6.2.2. Input port register pair (00h, 01h)

The Input port registers (registers 0 and 1) reflect the logic levels of the pins, regardless of whether

the pin is defined as an input or an output by the Configuration register. The Input port registers

are read only; writes to these registers have no effect. The default value ‘X’ is determined by the

externally applied logic level. An Input port register read operation is performed as described in

Section 7.2.

Table 4. Input port 0 register (address 00h)

Bit

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

Symbol

Default

Table 5. Input port 1 register (address 01h)

Bit

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

Symbol

Default

6.2.3. Output port register pair (02h, 03h)

The Output port registers (registers 2 and 3) define the outgoing logic levels of the pins defined as

outputs by the Configuration register. Bit values in these registers have no effect on pins defined

as inputs. In turn, reads from these registers reflect the value that was written to these registers,

not the actual pin value. A register pair write is described in Section 7.1 and a register pair read is

described in Section 7.2.

Table 6. Output port 0 register (address 02h)

Bit

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

Symbol

Default

Table 7. Output port 1 register (address 03h)

Bit

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

Symbol

Default

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

6.2.4. Polarity inversion register pair (04h, 05h)

The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs

by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding

port pin’s polarity is inverted in the Input register. If a bit in this register is cleared (written with a ‘0’),

the corresponding port pin’s polarity is retained. A register pair write is described in Section 7.1 and

a register pair read is described in Section 7.2.

Table 8. Polarity inversion port 0 register (address 04h)

Bit

N0.7

N0.6

N0.5

N0.4

N0.3

N0.2

N0.1

N0.0

Symbol

Default

Table 9. Polarity inversion port 1 register (address 05h)

Bit

N1.7

N1.6

N1.5

N1.4

N1.3

N1.2

N1.1

N1.0

Symbol

Default

6.2.5. Configuration register pair (06h, 07h)

The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in

these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit

in these registers is cleared to 0, the corresponding port pin is enabled as an output. A register pair

write is described in Section 7.1 and a register pair read is described in Section 7.2.

Table 10. Configuration port 0 register (address 06h)

Bit

C0.7

C0.6

C0.5

C0.4

C0.3

C0.2

C0.1

C0.0

Symbol

Default

Table 11. Configuration port 1 register (address 07h)

Bit

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Symbol

Default

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

6.3. I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance

input. The input voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port

The external voltage applied to this I/O pin should not exceed the recommended levels for proper

operation.

data from

shift register

output port

configuration

data from

shift register

write configuration

pulse

P0_0 to P0_7

P1_0 to P1_7

write pulse

output port

GND

input port

read pulse

to INT

polarity inversion

data from

shift register

polarity inversion

write polarity

pulse

aaa-036319

At power-on reset, all registers return to default values.

Fig. 5. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

6.4. Power-on reset

When power (from 0 V) is applied to V_CCand starts rising, an internal power-on reset holds the

NCA9535 in a reset condition until V_CChas reached V_PORR. At that time, the reset condition is

released and the NCA9535 registers and I²C-bus/SMBus state machine initializes to their default

states. After that, V_CCmust be lowered to below V_PORFand back up to the operating voltage for a

power-reset cycle. See Section 8.2.

6.5. Interrupt output

An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After

time t_v(INT), the signal INT is valid. The interrupt is reset when data on the port changes back

to the original value or when data is read form the port that generated the interrupt (see Fig. 9

and Fig. 10). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge

(NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK

clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Any

change of the I/Os after resetting is detected and is transmitted as INT.

A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an

input may cause a false interrupt to occur, if the state of the pin does not match the contents of the

Input Port register.

7. Bus transactions

The NCA9535 is an I²C-bus slave device. Data is exchanged between the master and NCA9535

through write and read commands using I²C-bus. The two communication lines are a serial data

line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a

pull-up resistor when connected to the output stages of a device. Data transfer may be initiated

only when the bus is not busy.

7.1. Writing to the port registers

Data is transmitted to the NCA9535 by sending the start condition, device address and setting the

read-write bit to a logic 0 (see Fig. 3). The command byte is sent after the address and determines

which register will receive the data following the command byte.

Eight registers within the NCA9535 are configured to operate as four register pairs. The four

pairs are input port, output port, polarity inversion, configuration registers. After sending data to

one register, the next data byte is sent to the other register in the pair (see Fig. 6 and Fig. 7). For

example, if the first byte is sent to output port 1 (register 3), the next byte is stored in output port 0

(register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this way, the

host can continuously update a register pair independently of the other registers, or the host can

simply update a single register.

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

SCL

SDA

slave address

A2 A1 A0

command byte

data to port 0

DATA 0

data to port 1

DATA 1

0.7

0.0

1.7

1.0

START condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

STOP

condition

write to port

v(Q)

data out

from port 0

v(Q)

data out

from port 1

DATA VALID

002aah344

Fig. 6. Write to output port registers

SCL

STOP

condition

slave address

A2 A1 A0

command byte

0/1 0/1 0/1

data to register

DATA 0

data to register

DATA 1

SDA

MSB

LSB

MSB

LSB

START condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

aaa-035814

Fig. 7. Write to Control registers

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

7.2. Reading the port registers

In order to read data from the NCA9535, the bus master must first send the start condition,

NCA9535 address with the read-write bit set to a logic 0 (see Fig. 3). The command byte is sent

after the address and determines which register will be accessed. After a start or restart, the device

address is sent again, but this time the least significant bit is set to a logic 1. Data from the register

defined by the command byte is sent by the NCA9535 (see Fig. 8, Fig. 9 and Fig. 10). Data is

clocked into the register on the rising edge of the acknowledge clock pulse. After the first byte is

read, additional bytes may be read but the data now reflects the information in the other register in

the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. There is no limit on

the number of data bytes received in one read transmission, but on the final byte received the bus

master must not acknowledge the data.

After a subsequent start or restart, the command byte contains the value of the next register to be

read in the pair. For example, if Input Port 1 was read last before the restart, the register that is

read after the restart is the Input Port 0.

command byte

0/1 0/1 0/1 A

slave address

A2 A1 A0

(cont.)

SDA

START condition

R/W

acknowledge

from slave

acknowledge

from slave

data from lower or

upper byte of register

data from upper or

lower byte of register

slave address

A2 A1 A0

MSB

LSB

MSB

LSB

(cont.)

DATA (first byte)

DATA (last byte)

NA P

(repeated)

START condition

R/W

acknowledge

from master

no acknowledge STOP

from master condition

acknowledge

from slave

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

aaa-035815

Remark: Transfer can be stopped at any time by a STOP condition.

Fig. 8. Read from register

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

data into port 0

data into port 1

INT

rst(INT)

v(INT)

SCL

SDA

R/W

STOP condition

slave address

A2 A1 A0

I0.x

I1.x

I0.x

I1.x

START condition

acknowledge

from slave

acknowledge

from master

acknowledge

from master

acknowledge

from master

non acknowledge

from master

read from port 0

read from port 1

aaa-036333

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is

assumed that the command byte has previously been set to ‘00h’ (read input port register).

This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Fig. 8).

Fig. 9. Read input port register, scenario 1

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

data into port 0

data into port 1

INT

DATA 00

DATA 01

DATA 02

DATA 03

su(D)

h(D)

DATA 10

DATA 11

DATA 12

su(D)

h(D)

rst(INT)

v(INT)

SCL

SDA

R/W

STOP condition

slave address

A2 A1 A0

I0.x

I1.x

DATA 10

I0.x

DATA 03

I1.x

DATA 00

DATA 12

START condition

acknowledge

from slave

acknowledge

from master

acknowledge

from master

acknowledge

from master

non acknowledge

from master

read from port 0

read from port 1

aaa-036327

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is

assumed that the command byte has previously been set to ‘00h’ (read input port register).

This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Fig. 8).

Fig. 10. Read input port register, scenario 2

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

8. Application design-in information

(3.3 V)

(1)

SUB-SYSTEM 1

(e.g., temp sensor)

10 k

2 k

100 k

(×3)

INT

MASTER

CONTROLLER

NCA9535

SCL

SDA

INT

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

SUB-SYSTEM 2

(e.g., counter)

SDA

INT

RESET

GND

controlled

switch

(e.g., CBT device)

enable

P0_6

P0_7

P1_0

P1_1

P1_2

P1_3

P1_4

P1_5

P1_6

P1_7

(1)

SUB-SYSTEM 3

(e.g., alarm system)

10 DIGIT

NUMERIC

KEYPAD

ALARM

GND

aaa-036320

Device address configured as 0100 000X for this example.

P0_0, P0_2, P0_3 configured as outputs.

P0_1, P0_4, P0_5 configured as inputs.

P0_6, P0_7 and (P1_0 to P1_7) configured as inputs.

(1) External pull-up and pull-down resistors are required for inputs IO P ports that may float. If a driver to an input

will never let the input float, a resistor is not needed. If an output in the P port is configured as a push-pull output

there is no need for external pull-up resistors. If an output in the P port is configured as an open-drain output,

external pull-up resistors are required.

Fig. 11. Typical application

8.1. Minimizing I_CCwhen the I/Os are used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V_CCthrough a resistor as

shown in Fig. 11. Since the LED acts as a diode, when the LED is off the I/O V_Iis about 1.2 V less

than V_CC. The supply current, I_CC, increases as V_Ibecomes lower than V_CC

Designs needing to minimize current consumption, such as battery power applications, should

consider maintaining the I/O pins greater than or equal to V_CCwhen the LED is off. Fig. 12 shows a

high value resistor in parallel with the LED. Fig. 13 shows V_CCless than the LED supply voltage by

at least 1.2 V. Both of these methods maintain the I/O V_Iat or above V_CCand prevents additional

supply current consumption when the LED is off.

NCA9535

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NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

3.3 V

5 V

100 k

LED

aaa-035816

aaa-035817

Fig. 12. High value resistor in parallel with

the LED

Fig. 13. Device supplied by a lower voltage

8.2. Power-on reset requirements

In the event of a glitch or data corruption, NCA9535 can be reset to its default conditions by using

the power-on reset feature. Power-on reset requires that the device go through a power cycle to

be completely reset. This reset also happens when the device is powered on for the first time in an

application.

The two types of power-on reset are shown in Fig. 14 and Fig. 15.

ramp-up

ramp-down

re-ramp-up

d(rst)

time

time to re-ramp

when V drops

(V )

rise CC

fall CC

)

t (V )

rise CC

below 0.2 V or to GND

aaa-035819

Fig. 14. V_CCis lowered below 0.2 V or to 0 V and then ramped up to V_CC

ramp-down

ramp-up

d(rst)

V drops below POR levels

time

time to re-ramp

fall CC

)

(V )

rise CC

when V

drops

to V

- 50 mV

PORF(min)

aaa-035820

Fig. 15. V_CCis lowered below the POR threshold, then ramped back up to V_CC

Table 12 specifies the performance of the power-on reset feature for NCA9535 for both types of

power-on reset.

NCA9535

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Product data sheet

Rev. 1 — 31 March 2023

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

Table 12. Recommended supply sequencing and ramp rates

T_amb= 25 °C (unless otherwise noted). Not tested; specified by design.

Symbol

Parameter

Condition

T_amb= 25 °C

Unit

Min

0.1

Typ

Max

t_rise(V

supply ramp up time

supply ramp down time

reset delay time

Fig. 14

2000 ms

)

t_fall(V

)

t_d(rst)

Fig. 14; re-ramp time when V_CC

drops below 0.2 V or to GND

µs

Fig. 15; re-ramp time when V_CC

drops to V_POR(min)- 50 mV

µs

ΔV_CC(gl)

glitch supply voltage difference

Fig. 16

V_{CC_MIN(gl)}minimum glitch supply voltage

minimum voltage that V_CCcan

glitch down to, but not cause

functional disruption when t_w(gl)V

Fig. 16

1.5

t_w(gl)V

supply voltage glitch pulse width

Fig. 16

μs

Glitches in the power supply can also affect the power-on reset performance of this device. The

glitch width (t_w(gl)V) and glitch height (ΔV_CC(gl)) are dependent on each other. The glitch on

power supply should never go below V_{CC_MIN(gl)}in order to properly guarantee functionality. The

bypass capacitance, source impedance, and device impedance are factors that affect power-

on reset performance. Fig. 16 and Table 12 provide more information on how to measure these

specifications.

CC(gl)

CC_MIN(gl)

time

w(gl)V

aaa-035821

Fig. 16. Glitch width and glitch height

V_PORRand V_PORFare critical to the power-on reset. V_PORRis the voltage level of V_CCat which the

reset condition is released and all the registers and the I²C-bus/SMBus state machine are initialized

to their default states. V_PORFis the voltage level of V_CCbelow which NCA9535 enters reset state.

Fig. 17 and Section 12 provide more details on this specification.

(rising V

(falling V

)

PORR

PORF

time

POR

time

aaa-035822

Fig. 17. Power-on reset voltage (V_POR

)

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

9. Limiting values

Table 13. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

V_I

Parameter

Conditions

Min

Max

Unit

supply voltage

-0.5

input voltage

[1]

-0.5

V_O

output voltage

-0.5

I_IK

input clamping current

output clamping current

input/output clamping current

A0, A1, A2, SCL; V_I< 0 V

INT; V_O< 0 V

-20

±20

-20

°C

I_OK

I_IOK

P port; V_O< 0 V or V_O> V_CC

SDA; V_O< 0 V

I_OL

LOW-level output current

continuous; I/O port

continuous; SDA, INT

continuous; P port

I_OH

HIGH-level output current

supply current

I_CC

160

250

200

+150

100

I_GND

P_tot

T_stg

T_j(max)

ground supply current

total power dissipation

storage temperature

-65

maximum junction temperature

°C

[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

10. Recommended operating conditions

Table 14. Operating conditions

Symbol

V_CC

Parameter

Conditions

Min

1.65

Max

5.5

Unit

supply voltage

V_IH

HIGH-level input voltage

SCL, SDA

0.7 × V_CC

-0.5

5.5

P1_7 to P0_0

A0, A1, A2,

5.5

V_CC

V_IL

LOW-level input voltage

SCL, SDA

0.3 × V_CC

A0, A1, A2, P1_7 to P0_0

P1_7 to P0_0

operating in free air

-0.5

I_OH

HIGH-level output current

LOW-level output current

ambient temperature

°C

I_OL

T_amb

-40

+85

11. Thermal characteristics

Table 15. Thermal characteristics

Symbol

Parameter

transient thermal impedance from junction to ambient

Conditions

TSSOP24 package

Max

Unit

K/W

Z_th(j-a)

[1]

100

[1] The package thermal impedance is calculated in accordance with JESD 51-7.

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Product data sheet

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NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

12. Static characteristics

Table 16. Static characteristics

V_CC= 1.65 V to 5.5 V; unless otherwise specified.

Symbol Parameter

Conditions

T_amb= -40 °C to +85 °C Unit

Min

-1.2

0.85

Typ [1]

Max

V_IK

input clamping voltage

I_I= -18 mA

V_PORFpower-on reset trip voltage; V_I= V_CCor GND; I_O= 0 mA

V_CCfalling

1.1

V_PORRpower-on reset trip voltage; V_I= V_CCor GND; I_O= 0 mA

V_CCrising

1.25

1.55

I_OL

LOW-level output current

V_OL= 0.4 V; V_CC= 1.65 V to 5.5 V

SDA

INT

28 [2]

P port

V_OL= 0.5 V; V_CC= 1.65 V

V_OL= 0.7 V; V_CC= 1.65 V

V_OL= 0.5 V; V_CC= 2.3 V

V_OL= 0.7 V; V_CC= 2.3 V

V_OL= 0.5 V; V_CC= 3.0 V

V_OL= 0.7 V; V_CC= 3.0 V

V_OL= 0.5 V; V_CC= 4.5 V

V_OL= 0.7 V; V_CC= 4.5 V

P port

[3]

V_OH

HIGH-level output voltage

I_OH= -8 mA; V_CC= 1.65 V

I_OH= -10 mA; V_CC= 1.65 V

I_OH= -8 mA; V_CC= 2.3 V

I_OH= -10 mA; V_CC= 2.3 V

I_OH= -8 mA; V_CC= 3.0 V

I_OH= -10 mA; V_CC= 3.0 V

I_OH= -8 mA; V_CC= 4.5 V

I_OH= -10 mA; V_CC= 4.5 V

P port; I_OL= 8 mA

[4]

1.2

1.1

2.0

1.9

2.6

2.5

4.1

4.0

V_OL

LOW-level output voltage

V_CC= 1.65 V

0.45

0.30

0.25

0.2

V_CC= 2.3 V

V_CC= 3.0 V

V_CC= 4.5 V

I_I

input current

V_CC= 1.65 V to 5.5 V

SCL, SDA; V_I= V_CCor GND

A0, A1, A2; V_I= V_CCor GND

P port; V_I= V_CC; V_CC= 1.65 V to 5.5 V

P port; V_I= GND; V_CC= 1.65 V to 5.5 V

±1

μA

I_IH

I_IL

HIGH-level input current

LOW-level input current

-1

NCA9535

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

Symbol Parameter

Conditions

T_amb= -40 °C to +85 °C Unit

Min

Typ [1]

Max

I_CC

supply current

SDA, P port, A0, A1, A2;

V_Ion SDA = V_CCor GND;

V_Ion P port and A0, A1, A2 = V_CC

;

I_O= 0 mA; I/O = inputs; f_SCL= 400 kHz

(t_r‚ =‚ 30‚ ns)

V_CC= 3.6 V to 5.5 V

V_CC= 2.3 V to 3.6 V

V_CC= 1.65 V to 2.3 V

6.4

μA

5.5

SCL, SDA, P port, A0, A1, A2;

V_Ion SCL, SDA = V_CCor GND;

V_Ion P port and A0, A1, A2 = V_CC

;

I_O= 0 mA; I/O = inputs; f_SCL= 0 kHz

V_CC= 3.6 V to 5.5 V

1.5

0.95

0.5

2.5

1.6

1.2

μA

V_CC= 2.3 V to 3.6 V

V_CC= 1.65 V to 2.3 V

Active mode; P port, A0, A1, A2;

V_Ion P port, A0, A1, A2 = V_CC

;

I_O= 0 mA; I/O = inputs;

f_SCL= 400 kHz (t_r‚ =‚ 30‚ ns), continuous

V_CC= 3.6 V to 5.5 V

V_CC= 2.3 V to 3.6 V

V_CC= 1.65 V to 2.3 V

7.4

3.5

μA

ΔI_CC

additional quiescent supply SCL, SDA; one input at V_CC- 0.6 V, other

4.5

current

inputs at V_CCor GND; V_CC= 1.65 V to 5.5 V

P port, A0, A1, A2; one input at V_CC- 0.6 V,

other inputs at V_CCor GND;

μA

V_CC= 1.65 V to 5.5 V

C_i

input capacitance

V_I= V_CCor GND; V_CC= 1.65 V to 5.5 V

V_I/O= V_CCor GND; V_D= 1.65 V to 5.5 V

1.5

2.5

4.5

C_io

input/output capacitance

[1] For I_CC, all typical values are at nominal supply voltage (1.8 V, 3.3 V or 5 V V_CC) and T_amb= 25 °C. Except for I_CC, the typical values

are at V_CC= 3.3 V and T_amb= 25 °C.

[2] Typical value for T_amb= 25 °C. V_OL= 0.4 V and V_CC= 3.3 V.

[3] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 200 mA.

[4] The total current sourced by all I/Os must be limited to 160 mA.

NCA9535

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Product data sheet

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18 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

12.1. Typical characteristics

aaa-035825

aaa-035824

1.6

1.2

0.8

0.4

(µA)

(μA)

(8)

(7)

(6)

(5)

(4)

(3)

(2)

(1)

(8)

(7)

(6)

(5)

(4)

(3)

(2)

(1)

-40

-15

(°C)

-15

(°C)

amb

f_SCL= 400 kHz

(1) V_CC= 1.65 V

(2) V_CC= 1.8 V

(3) V_CC= 2.3 V

(4) V_CC= 2.5 V

(5) V_CC= 3.3 V

(6) V_CC= 3.6 V

(7) V_CC= 5.0 V

(8) V_CC= 5.5 V

(1) V_CC= 1.65 V

(2) V_CC= 1.8 V

(3) V_CC= 2.3 V

(4) V_CC= 2.5 V

(5) V_CC= 3.3 V

(6) V_CC= 3.6 V

(7) V_CC= 5.0 V

(8) V_CC= 5.5 V

Fig. 19. Standby supply current versus ambient

temperature

Fig. 18. Supply current versus ambient temperature

aaa-035826

(μA)

1.5

2.5

3.5

4.5

(V)

5.5

T_amb= 25 °C; f_SCL= 400 kHz

Fig. 20. Supply current versus supply voltage

NCA9535

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Product data sheet

Rev. 1 — 31 March 2023

19 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

aaa-035828

aaa-035829

sink

(mA)

(1)

(2)

(3)

(1)

(2)

(3)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(V)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(V)

a. V_CC= 1.65 V

b. V_CC= 1.8 V

aaa-035830

aaa-035831

sink

(mA)

(1)

(2)

(3)

(1)

(2)

(3)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(V)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(V)

c. V_CC= 2.5 V

d. V_CC= 3.3 V

aaa-035833

aaa-035834

sink

(mA)

(1)

(2)

(3)

(1)

(2)

(3)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(V)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(V)

e. V_CC= 5.0 V

f. V_CC= 5.5 V

(1) T_amb= -40 °C

(2) T_amb= 25 °C

(3) T_amb= 85 °C

Fig. 21. I/O sink current versus LOW-level output voltage

NCA9535

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Product data sheet

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20 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

aaa-035835

aaa-035836

source

(mA)

(1)

(2)

(3)

(1)

(2)

(3)

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0.1

0.2

0.3

0.4

0.5

(V)

0.6

- V

a. V_CC= 1.65 V

b. V_CC= 1.8 V

aaa-035837

aaa-035838

source

(mA)

(1)

(2)

(3)

(1)

(2)

(3)

0.1

0.3

0.4

0.5

(V)

0.6

0.1

0.3

0.4

0.5

(V)

0.6

- V

c. V_CC= 2.5 V

d. V_CC= 3.3 V

aaa-035839

aaa-035840

source

(mA)

source

(mA)

(1)

(2)

(3)

(1)

(2)

(3)

0.1

0.3

0.4

0.5

(V)

0.6

0.1

0.3

0.4

- V

CC OH

0.5

(V)

0.6

- V

e. V_CC= 5.0 V

f. V_CC= 5.5 V

(1) T_amb= -40 °C

(2) T_amb= 25 °C

(3) T_amb= 85 °C

Fig. 22. I/O source current versus HIGH-level output voltage

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

aaa-035841

aaa-035842

250

300

CC - VOH

(mV)

250

200

150

100

200

150

100

(1)

(2)

(3)

(4)

(1)

(2)

(3)

(4)

-40

-15

(°C)

-15

(°C)

amb

(1) V_CC= 1.8 V; I_sink= 10 mA

(2) V_CC= 5 V; I_sink= 10 mA

(3) V_CC= 1.8 V; I_sink= 1 mA

(4) V_CC= 5 V; I_sink= 1 mA

(1) V_CC= 1.8 V; I_source= -10 mA

(2) V_CC= 5 V; I_source= -10 mA

(3) V_CC= 1.8 V; I_source= -1 mA

(4) V_CC= 5 V; I_source= -1 mA

Fig. 23. LOW-level output voltage versus temperature

Fig. 24. I/O high voltage versus temperature

13. Dynamic characteristics

Table 17. I²C-bus interface timing requirements

Over recommended operating free air temperature range, unless otherwise specified. See Fig. 25.

Symbol Parameter

Conditions

Standard-mode

I²C-bus

Fast-mode

I²C-bus

Unit

Min

Max

100

Min

Max

f_SCL

t_HIGH

t_LOW

t_SP

SCL clock frequency

400 kHz

HIGH period of the SCL clock

LOW period of the SCL clock

0.6

1.3

μs

4.7

pulse width of spikes that must

be suppressed by the input filter

t_SU;DAT

data set-up time

250

100

t_HD;DAT

data hold time

t_r

t_f

rise time of both SDA and SCL signals

fall time of both SDA and SCL signals

1000

300

300 ns

20 ×

(V_CC/ 5.5 V)

t_BUF

bus free time between a STOP and

START condition

4.7

1.3

μs

t_SU;STA

set-up time for a repeated START

condition

0.6

t_HD;STA

t_SU;STO

t_VD;DAT

hold time (repeated) START condition

set-up time for STOP condition

data valid time

0.6

μs

SCL LOW to SDA

output valid

3.45

0.9 μs

t_VD;ACK

data valid acknowledge time

ACK signal from

SCL LOW to SDA

(out) LOW

3.45

0.9 μs

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Product data sheet

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Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

Table 18. Switching characteristics

Over recommended operating free air temperature range; C_L≤ 100 pF; unless otherwise specified. See Fig. 26.

Symbol Parameter

Conditions

Standard-mode

I²C-bus

Fast-mode

I²C-bus

Unit

Min

Max

Min

Max

t_v(INT)

t_rst(INT)

t_v(Q)

valid time on pin INT

from P port to INT

from SCL to INT

μs

reset time on pin INT

data output valid time

data input set-up time

data input hold time

from SCL to P port

from P port to SCL

300

t_su(D)

t_h(D)

-50

240

-50

240

14. Parameter measurement information

= 1 k

SDA

DUT

= 50 pF

aaa-035847

a. SDA load configuration

(1)

two bytes for read Input port register

R/W

STOP

condition condition

(P) (S)

START

Address

Bit 7

(MSB)

Data

Bit 7

(MSB)

Data

STOP

condition

(P)

Address

Bit 1

ACK

(A)

Bit 0

(LSB)

002aag952

b. Transaction format

HIGH

LOW

0.7 × V

0.3 × V

SCL

SDA

VD;DAT

SU;STO

BUF

SU;STA

VD;ACK

f(o)

0.7 × V

0.3 × V

VD;ACK

HD;DAT

HD;STA

SU;DAT

repeat START condition

STOP condition

aaa-035843

c. Voltage waveforms

C_Lincludes probe and jig capacitance.

All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z_o= 50 Ω;

t_r/t_f≤ 30 ns.

All parameters and waveforms are not applicable to all devices.

Byte 1 = I²C-bus address; Byte 2, byte 3 = P port data.

(1) See Fig. 9.

Fig. 25. I²C-bus interface load circuit and voltage waveforms

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Product data sheet

Rev. 1 — 31 March 2023

23 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

= 4.7 k

INT

DUT

= 100 pF

aaa-035848

a. Interrupt load configuration

acknowledge

from slave

acknowledge

from slave

no acknowledge

from master

START condition

slave address

R/W

STOP

8 bits (one data byte)

from port

condition

data from port

DATA 2

SDA

A2 A1 A0

DATA 1

SCL

rst(INT)

INT

v(INT)

su(D)

data into

port

ADDRESS

DATA 1

SCL

DATA 2

0.7 × V

0.3 × V

INT

0.5 × V

R/W

v(INT)

rst(INT)

INT

0.5 × V

View A - A

View B - B

aaa-035844

b. Voltage waveforms

C_Lincludes probe and jig capacitance.

All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z_o= 50 Ω;

t_r/t_f≤ 30 ns.

All parameters and waveforms are not applicable to all devices.

Fig. 26. Interrupt load circuit and voltage waveforms

NCA9535

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Product data sheet

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24 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

500

DUT

2 × V

= 50 pF

500

aaa-036323

a. P port load configuration

0.7 × V

0.3 × V

SCL

SDA

v(Q)

last stable bit

unstable

data

aaa-035845

b. Write mode (R/W = 0)

0.7 × V

0.3 × V

SCL

h(D)

su(D)

aaa-035846

c. Read mode (R/W = 1)

C_Lincludes probe and jig capacitance.

t_v(Q)is measured from 0.7 × V_CCon SCL to 50 % I/O (Pn) output.

All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z_o= 50 Ω;

t_r/t_f≤ 30 ns.

The outputs are measured one at a time, with one transition per measurement.

All parameters and waveforms are not applicable to all devices.

Fig. 27. P port load circuit and voltage waveforms

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Product data sheet

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NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

15. Package outline

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

1.1

0.65

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT355-1

MO-153

Fig. 28. Package outline SOT355-1 (TSSOP24)

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Product data sheet

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NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

16. Abbreviations

Table 19. Abbreviations

Acronym

ACPI

CBT

Description

Advanced Configuration and Power Interface

Cross-Bar Technology

CDM

CMOS

ESD

Charged-Device Model

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Field-Effect Transistor

FET

Flip-Flop

GPIO

HBM

I²C-bus

I/O

General Purpose Input/Output

Human Body Model

Inter-Integrated Circuit bus

Input/Output

LED

Light Emitting Diode

SMBus

System Management Bus

17. Revision history

Table 20. Revision history

Document ID

Release date Data sheet status

20230331 Product data sheet

Change notice Supersedes

NCA9535 v.1

NCA9535

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 31 March 2023

27 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

18. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

Data sheet status

document, and as such is not complete, exhaustive or legally binding.

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

NCA9535

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 31 March 2023

28 / 29

Nexperia

NCA9535

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration

registers

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................2

4. Block diagram...............................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description.............................................................3

6. Functional description................................................. 4

6.1. Device address............................................................4

6.2. Registers......................................................................4

6.2.1. Pointer register and command byte..........................4

6.2.2. Input port register pair (00h, 01h).............................5

6.2.3. Output port register pair (02h, 03h).......................... 5

6.2.4. Polarity inversion register pair (04h, 05h)................. 6

6.2.5. Configuration register pair (06h, 07h).......................6

6.3. I/O port........................................................................ 7

6.4. Power-on reset............................................................ 8

6.5. Interrupt output............................................................ 8

7. Bus transactions.......................................................... 8

7.1. Writing to the port registers......................................... 8

7.2. Reading the port registers.........................................10

8. Application design-in information.............................13

8.1. Minimizing I_CCwhen the I/Os are used to control

LEDs...................................................................................13

8.2. Power-on reset requirements.................................... 14

9. Limiting values........................................................... 16

10. Recommended operating conditions......................16

11. Thermal characteristics............................................16

12. Static characteristics................................................17

12.1. Typical characteristics..............................................19

13. Dynamic characteristics.......................................... 22

14. Parameter measurement information..................... 23

15. Package outline........................................................ 26

16. Abbreviations............................................................27

17. Revision history........................................................27

18. Legal information......................................................28

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 31 March 2023

NCA9535

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 31 March 2023

29 / 29

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