PBSS4160PANP [NEXPERIA]
60 V, 1 A NPN/PNP low VCEsat (BISS) transistorProduction;
| 型号： | PBSS4160PANP |
| 厂家： | 
Nexperia |
| 描述： | 60 V, 1 A NPN/PNP low VCEsat (BISS) transistorProduction |
| 文件： | 总21页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
20 December 2017
Product data sheet
1. General description
NPN/PNP low VCEsat Breakthrough In Small Signal (BISS) transistor in a leadless medium power
DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package.
NPN/NPN complement: PBSS4160PAN. PNP/PNP complement: PBSS5160PAP.
2. Features and benefits
•
Very low collector-emitter saturation voltage VCEsat
•
•
•
•
•
High collector current capability IC and ICM
High collector current gain hFE at high IC
Reduced Printed-Circuit Board (PCB) requirements
High efficiency due to less heat generation
AEC-Q101 qualified
3. Applications
•
•
•
•
•
Load switch
Battery-driven devices
Power management
Charging circuits
Power switches (e.g. motors, fans)
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor; for the PNP transistor with negative polarity
VCEO
collector-emitter
voltage
open base
-
-
60
V
IC
collector current
-
-
-
-
1
A
A
ICM
peak collector current single pulse; tp ≤ 1 ms
1.5
TR1 (NPN)
RCEsat
collector-emitter
saturation resistance
IC = 0.5 A; IB = 50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-
-
-
240
360
mΩ
mΩ
TR2 (PNP)
RCEsat
collector-emitter
saturation resistance
IC = -0.5 A; IB = -50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
E1
B1
C2
E2
B2
C1
C1
C2
emitter TR1
base TR1
C1 B2
E2
6
5
4
2
TR2
7
8
3
collector TR2
emitter TR2
base TR2
TR1
4
E1
B1 C2
sym139
1
2
3
5
Transparent top view
6
collector TR1
collector TR1
collector TR2
DFN2020-6 (SOT1118)
7
8
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
PBSS4160PANP
DFN2020-6
DFN2020-6: plastic thermal enhanced ultra thin small outline
package; no leads; 6 terminals; body 2 x 2 x 0.65 mm
SOT1118
7. Marking
Table 4. Marking codes
Type number
Marking code
PBSS4160PANP
2M
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
2 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
Per transistor; for the PNP transistor with negative polarity
Min
Max
Unit
VCBO
VCEO
VEBO
IC
collector-base voltage
open emitter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60
V
collector-emitter voltage open base
60
V
emitter-base voltage
collector current
open collector
7
V
1
A
ICM
peak collector current
base current
single pulse; tp ≤ 1 ms
1.5
0.3
1
A
IB
A
IBM
peak base current
total power dissipation
single pulse; tp ≤ 1 ms
Tamb ≤ 25 °C
A
Ptot
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
370
570
530
700
450
760
700
1450
mW
mW
mW
mW
mW
mW
mW
mW
Per device
Ptot
total power dissipation
Tamb ≤ 25 °C
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
-
510
780
730
960
620
1040
960
2000
150
150
150
mW
mW
mW
mW
mW
mW
mW
mW
°C
-
-
-
-
-
-
-
Tj
junction temperature
ambient temperature
storage temperature
-
Tamb
Tstg
-55
-65
°C
°C
[1] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
[4] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[5] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
[6] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[7] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
[8] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
3 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad165
1.5
(1)
P
tot
(W)
1.0
(2)
(3) (4)
(5)
(6)
(7)
(8)
0.5
0
-75
-25
25
75
125
175
(°C)
T
amb
(1) 4-layer PCB 70 µm, mounting pad for collector 1 cm2
(2) FR4 PCB 70 µm, mounting pad for collector 1 cm2
(3) 4-layer PCB 70 µm, standard footprint
(4) 4-layer PCB 35 µm, mounting pad for collector 1 cm2
(5) FR4 PCB 35 µm, mounting pad for collector 1 cm2
(6) 4-layer PCB 35 µm, standard footprint
(7) FR4 PCB 70 µm, standard footprint
(8) FR4 PCB 35 µm, standard footprint
Fig. 1. Per transistor: power derating curves
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor
Rth(j-a)
thermal resistance
from junction to
ambient
in free air
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
338
219
236
179
278
164
179
86
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
Rth(j-sp)
thermal resistance
from junction to solder
point
30
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
4 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
Symbol
Per device
Rth(j-a)
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance
from junction to
ambient
in free air
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
245
160
171
130
202
120
130
63
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
[1] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
[4] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[5] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
[6] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
[7] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
[8] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2.
006aad166
3
10
Z
duty cycle = 1
th(j-a)
(K/W)
0.75
0.5
2
0.33
10
0.2
0.1
0.05
10
0.02
0.01
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 35 µm, standard footprint
Fig. 2. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
5 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad167
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
2
10
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 35 µm, mounting pad for collector 1 cm2
Fig. 3. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aad168
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
2
0.5
10
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 35 µm, standard footprint
Fig. 4. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
6 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad169
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
2
10
0.5
0.33
0.2
0.1
0.05
10
0.02
0
0.01
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 35 µm, mounting pad for collector 1 cm2
Fig. 5. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aac610
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
0.5
0.33
2
10
0.2
0.1
0.05
10
0.02
0.01
0
1
10
- 5
- 4
- 3
10
- 2
- 1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 70 µm, standard footprint
Fig. 6. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
7 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aac611
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
2
0.75
0.5
10
0.33
0.2
0.1
10
0.05
0.02
0.01
0
1
10
- 5
- 4
- 3
10
- 2
- 1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 70 µm, mounting pad for collector 1 cm2
Fig. 7. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aad170
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
0.5
2
10
0.33
0.2
0.1
0.05
10
0.02
0
0.01
-4
1
-5
10
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 70 µm, standard footprint
Fig. 8. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
8 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad171
2
10
duty cycle = 1
0.75
0.5
0.2
Z
th(j-a)
(K/W)
0.33
10
0.1
0.05
0.02
0.01
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 70 µm, mounting pad for collector 1 cm2
Fig. 9. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
9 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
10. Characteristics
Table 7. Characteristics
Symbol
TR1 (NPN)
ICBO
Parameter
Conditions
Min
Typ
Max
Unit
collector-base cut-off
current
VCB = 48 V; IE = 0 A; Tamb = 25 °C
VCB = 48 V; IE = 0 A; Tj = 150 °C
VEB = 5 V; IC = 0 A; Tamb = 25 °C
-
-
-
-
-
-
100
50
nA
µA
nA
IEBO
hFE
emitter-base cut-off
current
100
DC current gain
VCE = 2 V; IC = 100 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
290
150
70
430
220
110
-
-
-
VCE = 2 V; IC = 500 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
VCE = 2 V; IC = 1 A; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
VCEsat
collector-emitter
saturation voltage
IC = 500 mA; IB = 50 mA; Tamb = 25 °C
-
-
90
120
240
mV
mV
IC = 1 A; IB = 50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
185
IC = 1 A; IB = 100 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-
175
-
220
240
mV
mΩ
RCEsat
VBEsat
collector-emitter
saturation resistance
IC = 0.5 A; IB = 50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
base-emitter saturation IC = 500 mA; IB = 50 mA; Tamb = 25 °C
voltage
-
-
-
-
1
V
V
IC = 1 A; IB = 50 mA; tp ≤ 300 µs;
1.1
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
IC = 1 A; IB = 100 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-
-
-
1.1
0.9
V
V
VBEon
base-emitter turn-on
voltage
VCE = 2 V; IC = 0.5 A; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
td
tr
delay time
VCC = 10 V; IC = 0.5 A; IBon = 25 mA;
IBoff = -25 mA; Tamb = 25 °C
-
15
-
-
-
-
-
-
-
ns
rise time
-
90
ns
ton
ts
turn-on time
storage time
fall time
-
105
410
130
540
175
ns
-
ns
tf
-
ns
toff
fT
turn-off time
transition frequency
-
ns
VCE = 10 V; IC = 50 mA; f = 100 MHz;
Tamb = 25 °C
90
MHz
Cc
collector capacitance
VCB = 10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
-
4
6
pF
TR2 (PNP)
ICBO
collector-base cut-off
current
VCB = -48 V; IE = 0 A
-
-
-
-
-
-
-100
-50
nA
µA
nA
VCB = -48 V; IE = 0 A; Tj = 150 °C
VEB = -5 V; IC = 0 A
IEBO
emitter-base cut-off
current
-100
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
10 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
hFE
DC current gain
VCE = -2 V; IC = -100 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
170
245
-
VCE = -2 V; IC = -500 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
120
170
-
VCE = -2 V; IC = -1 A; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
70
-
100
-
VCEsat
collector-emitter
saturation voltage
IC = -500 mA; IB = -50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-125
-180
-550
-340
360
-1
mV
mV
mV
mΩ
V
IC = -1 A; IB = -50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-390
IC = -1 A; IB = -100 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-240
RCEsat
VBEsat
collector-emitter
saturation resistance
IC = -0.5 A; IB = -50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-
-
-
-
-
base-emitter saturation IC = -500 mA; IB = -50 mA; tp ≤ 300 µs;
voltage
-
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
IC = -1 A; IB = -50 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-1
V
IC = -1 A; IB = -100 mA; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
-1.1
-0.9
V
VBEon
base-emitter turn-on
voltage
VCE = -2 V; IC = -0.5 A; tp ≤ 300 µs;
pulsed; δ ≤ 0.02 ; Tamb = 25 °C
-
V
td
tr
delay time
VCC = -10 V; IC = -0.5 A; IBon = -25 mA;
IBoff = 25 mA; Tamb = 25 °C
-
15
-
-
-
-
-
-
-
ns
rise time
-
40
ns
ton
ts
turn-on time
storage time
fall time
-
55
ns
-
95
ns
tf
-
40
ns
toff
fT
turn-off time
transition frequency
-
135
125
ns
VCE = -10 V; IC = -50 mA; f = 100 MHz;
Tamb = 25 °C
65
MHz
Cc
collector capacitance
VCB = -10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
-
9.5
13
pF
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
11 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad204
006aad205
800
1.50
I
= 15 mA
13.5 12 10.5
B
I
C
h
FE
(A)
(1)
(2)
1.00
9
7.5
6
600
0.75
0.50
0.25
0
4.5
3
400
200
0
(3)
1.5
-1
10
2
3
4
1
10
10
10
10
(mA)
0
1
2
3
4
5
I
V
CE
(V)
C
VCE = 2 V
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 11. TR1 (NPN): Collector current as a function of
collector-emitter voltage; typical values
Fig. 10. TR1 (NPN): DC current gain as a function of
collector current; typical values
006aad206
006aad207
1.2
1.2
V
BEsat
(V)
V
BE
(V)
1.0
0.8
0.6
0.4
0.2
(1)
(2)
(3)
0.8
(1)
(2)
(3)
0.4
0
-1
10
2
3
4
-1
10
2
3
4
1
10
10
10
10
(mA)
1
10
10
10
10
I (mA)
C
I
C
VCE = 2 V
IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb= 100 °C
Fig. 12. TR1 (NPN): Base-emitter voltage as a function
of collector current; typical values
Fig. 13. TR1 (NPN): Base-emitter saturation voltage as
a function of collector current; typical values
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
12 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad208
006aad209
1
10
V
CEsat
(V)
V
CEsat
(V)
1
(1)
-1
10
10
10
(2)
-1
-2
-3
10
10
10
(1)
(2)
(3)
-2
(3)
-3
-1
10
2
3
4
-1
2
3
4
1
10
10
10
10
(mA)
10
1
10
10
10
10
I (mA)
C
I
C
IC/IB = 20
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 14. TR1 (NPN): Collector-emitter saturation voltage Fig. 15. TR1 (NPN): Collector-emitter saturation voltage
as a function of collector current; typical
values
as a function of collector current; typical
values
006aad210
006aad211
3
3
10
10
R
CEsat
(Ω)
R
CEsat
(Ω)
2
2
10
10
10
10
(1)
(1)
(2)
(2)
1
1
-1
-1
10
10
10
10
(3)
(3)
-2
-2
-1
2
3
4
-1
2
3
4
10
1
10
10
10
10
(mA)
10
1
10
10
10
10
I (mA)
C
I
C
IC/IB = 20
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 16. TR1 (NPN): Collector-emitter saturation
resistance as a function of collector current;
typical values
Fig. 17. TR1 (NPN): Collector-emitter saturation
resistance as a function of collector current;
typical values
©
PBSS4160PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
13 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad212
006aad213
500
-1.50
I
= -20 mA
-18 -16
-14
B
h
I
C
FE
(A)
400
-1.00
-12
-10
-8
(1)
(2)
(3)
300
200
100
0
-0.75
-0.50
-0.25
0
-6
-4
-2
-1
-10
2
3
4
-1
-10
-10
-10
-10
(mA)
0
-1
-2
-3
-4
-5
I
C
V
(V)
CE
VCE = −2 V
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 19. TR2 (PNP): Collector current as a function of
collector-emitter voltage; typical values
Fig. 18. TR2 (PNP): DC current gain as a function of
collector current; typical values
006aad214
006aad215
-1.2
-1.2
V
BEsat
(V)
V
BE
(V)
-1.0
-0.8
-0.6
-0.4
-0.2
-0.8
(1)
(2)
(3)
(1)
(2)
(3)
-0.4
0
-1
-10
2
3
4
-1
-10
2
3
4
-1
-10
-10
-10
-10
(mA)
-1
-10
-10
-10
-10
I (mA)
C
I
C
VCE = −2 V
IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 20. TR2 (PNP): Base-emitter voltage as a function
of collector current; typical values
Fig. 21. TR2 (PNP): Base-emitter saturation voltage as a
function of collector current; typical values
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PBSS4160PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
14 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
006aad216
006aad217
-10
-10
V
V
CEsat
(V)
CEsat
(V)
-1
-1
(1)
(2)
-1
-2
-3
-1
-2
-3
(1)
-10
-10
-10
-10
-10
-10
(2)
(3)
(3)
-1
2
3
4
-1
2
3
4
-10
-1
-10
-10
-10
-10
(mA)
-10
-1
-10
-10
-10
-10
I (mA)
C
I
C
IC/IB = 20
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB = 10
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 22. TR2 (PNP): Collector-emitter saturation voltage Fig. 23. TR2 (PNP): Collector-emitter saturation voltage
as a function of collector current; typical
values
as a function of collector current; typical
values
006aad218
006aad219
3
3
10
10
R
CEsat
(Ω)
R
CEsat
(Ω)
2
10
2
10
(1)
10
(2)
10
(1)
(2)
1
1
-1
10
10
(3)
(3)
-1
-2
10
-1
2
3
4
-1
2
3
4
-10
-1
-10
-10
-10
-10
(mA)
-10
-1
-10
-10
-10
-10
I (mA)
C
I
C
IC/IB = 20
Tamb = 25 °C
(1) IC/IB = 100
(2) IC/IB = 50
(3) IC/IB= 10
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig. 24. TR2 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
Fig. 25. TR2 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
15 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
11. Test information
I
B
input pulse
90 %
(idealized waveform)
I
(100 %)
Bon
10 %
I
Boff
output pulse
(idealized waveform)
I
C
90 %
I
(100 %)
C
10 %
t
t
t
f
t
t
r
s
d
t
t
off
on
006aaa003
Fig. 26. TR1 (NPN): BISS transistor switching time definition
V
V
CC
BB
R
B
R
C
V
o
(probe)
450 Ω
(probe)
450 Ω
oscilloscope
oscilloscope
R2
V
I
DUT
R1
mlb826
Fig. 27. TR1 (NPN): Test circuit for switching times
©
PBSS4160PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
16 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
-
I
B
input pulse
90 %
(idealized waveform)
-
I
(100 %)
Bon
10 %
-
I
Boff
output pulse
-
(idealized waveform)
I
C
90 %
-
I
(100 %)
C
10 %
t
t
t
f
t
t
r
s
d
006aaa266
t
t
off
on
Fig. 28. TR2 (PNP): BISS transistor switching time definition
V
V
CC
BB
R
B
R
C
V
o
(probe)
450 Ω
(probe)
450 Ω
oscilloscope
oscilloscope
R2
V
I
DUT
R1
mgd624
Fig. 29. TR2 (PNP): Test circuit for switching times
Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC)
standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in
automotive applications.
©
PBSS4160PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
17 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
12. Package outline
2.1
1.9
0.65
max
1.1
0.9
0.04
max
0.77
0.57
(2×)
3
4
6
0.65
(4×)
2.1
1.9
0.54
0.44
(2×)
0.35
0.25
(6×)
1
0.3
0.2
Dimensions in mm
10-05-31
Fig. 30. Package outline DFN2020-6 (SOT1118)
13. Soldering
2.1
0.65
0.49
0.65
0.49
0.3 0.4
(6×) (6×)
solder lands
0.875
0.875
solder paste
1.05 1.15
2.25
(2×) (2×)
solder resist
occupied area
Dimensions in mm
0.35
(6×)
0.72
(2×)
0.45
(6×)
0.82
(2×)
sot1118_fr
Fig. 31. Reflow soldering footprint for DFN2020-6 (SOT1118)
©
PBSS4160PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
18 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
14. Revision history
Table 8. Revision history
Data sheet ID
Release date
20171220
Data sheet status
Change notice
Supersedes
PBSS4160PANP v.2
Modifications:
Product data sheet
-
PBSS4160PANP v.1
•
Characteristics: Fig. 22 corrected
PBSS4160PANP v.1
20130114
Product data sheet
-
-
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
19 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
15. Legal information
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Data sheet status
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Document
status [1][2] status [3]
Product
Definition
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nexperia.com.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
Nexperia does not give any representations or warranties as to the accuracy
or completeness of information included herein and shall have no liability for
the consequences of use of such information.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Disclaimers
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’ aggregate and cumulative liability towards customer
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
20 / 21
Nexperia
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
16. Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking..........................................................................2
8. Limiting values............................................................. 3
9. Thermal characteristics............................................... 4
10. Characteristics..........................................................10
11. Test information....................................................... 16
12. Package outline........................................................ 18
13. Soldering................................................................... 18
14. Revision history........................................................19
15. Legal information..................................................... 20
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 20 December 2017
©
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
20 December 2017
21 / 21
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