PSMN013-60HL [NEXPERIA]
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technologyProduction;型号: | PSMN013-60HL |
厂家: | Nexperia |
描述: | N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technologyProduction |
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PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in
LFPAK56D using TrenchMOS technology
30 September 2022
Product data sheet
1. General description
Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using
TrenchMOS technology.
2. Features and benefits
•
Dual MOSFET
•
•
•
•
Repetitive avalanche rated
High reliability LFPAK56D package
Copper-clip, solder die attach
Qualified to 175 °C
3. Applications
•
•
•
•
Brushless DC motor control
DC-to-DC converters
High-performance synchronous rectification
High performance and high efficiency server power supply
4. Quick reference data
Table 1. Quick reference data
Symbol
VDS
ID
Parameter
Conditions
Min
Typ
Max
60
Unit
V
drain-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
VGS = 5 V; Tmb = 25 °C; Fig. 2
-
-
-
-
-
[1]
-
40
A
Ptot
total power dissipation Tmb = 25 °C; Fig. 1
junction temperature
-
64
W
Tj
-55
175
°C
Static characteristics FET1 and FET2
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 11
-
-
10
22
12.5
28.3
mΩ
mΩ
VGS = 5 V; ID = 10 A; Tj = 175 °C;
Fig. 11; Fig. 12
Dynamic characteristics FET1 and FET2
QGD
gate-drain charge
total gate charge
ID = 10 A; VDS = 48 V; VGS = 5 V;
Tj = 25 °C; Fig. 13; Fig. 14
-
-
7.9
-
-
nC
nC
QG(tot)
22.4
Avalanche Ruggedness FET1 and FET2
EDS(AL)S
non-repetitive drain-
source avalanche
energy
ID = 40 A; Vsup ≤ 60 V; RGS = 50 Ω;
VGS = 5 V; Tj(init) = 25 °C; unclamped;
Fig. 4
[2] [3]
-
-
82
mJ
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode FET1 and FET2
Qr recovered charge
IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 30 V; Tj = 25 °C
-
18.9
-
nC
[1] Continuous current is limited by package
[2] Refer to application note AN10273 for further information
[3] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol
S1
Description
source1
gate1
Simplified outline
Graphic symbol
8
7
6
5
2
G1
D1
D2
D2
D1
3
S2
source2
gate2
4
G2
5
D2
drain2
6
D2
drain2
S1
G1
S2
G2
mbk725
7
D1
drain1
1
2
3
4
8
D1
drain1
LFPAK56D; Dual
LFPAK (SOT1205)
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
PSMN013-60HL
LFPAK56D;
Dual LFPAK
plastic, single ended surface mounted package
(LFPAK56D); 8 leads
SOT1205
7. Marking
Table 4. Marking codes
Type number
Marking code
13RL60H
PSMN013-60HL
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
25 °C ≤ Tj ≤ 175 °C
RGS = 20 kΩ
-
60
60
10
15
64
V
V
V
V
W
VDGR
VGS
-
DC; Tj ≤ 175 °C
Pulsed; Tj ≤ 175 °C
Tmb = 25 °C; Fig. 1
-10
[1] [2] -15
-
Ptot
total power dissipation
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
2 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
Symbol
Parameter
Conditions
Min
Max
40
Unit
A
ID
drain current
VGS = 5 V; Tmb = 25 °C; Fig. 2
VGS = 5 V; Tmb = 100 °C; Fig. 2
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
[3]
-
-
33
A
IDM
peak drain current
storage temperature
junction temperature
-
190
175
175
260
A
Tstg
Tj
-55
-55
-
°C
°C
°C
Tsld(M)
peak soldering
temperature
Source-drain diode FET1 and FET2
IS
source current
Tmb = 25 °C
[3]
-
-
40
A
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
190
Avalanche Ruggedness FET1 and FET2
EDS(AL)S non-repetitive drain-
ID = 40 A; Vsup ≤ 60 V; RGS = 50 Ω;
[4] [5]
-
82
mJ
source avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped;
Fig. 4
[1] Accumulated Pulse duration up to 50 hours delivers zero defect ppm
[2] Significantly longer life times are achieved by lowering Tj and or VGS
.
[3] Continuous current is limited by package
[4] Refer to application note AN10273 for further information
[5] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
03aa16
003aak109
120
50
40
30
20
10
0
I
D
(A)
P
der
(%)
(1)
80
40
0
0
50
100
150
200
0
25
50
75 100 125 150 175 200
(°C)
T
mb
T
(°C)
mb
(1) Capped at 40 A due to package
VGS ≥ 5 V
Fig. 2. Continuous drain current as a function of
mounting base temperature
Fig. 1. Normalized total power dissipation as a
function of mounting base temperature
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
3 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
003aak108
3
10
I
D
(A)
Limit R
= V / I
DS
DSon
D
2
10
t
p
= 10 us
100 us
10
DC
1 ms
1
10 ms
100 ms
-1
10
-1
2
3
10
1
10
10
10
V
DS
(V)
Tmb = 25 °C; IDM is a single pulse
Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
003aak110
2
10
I
AL
(A)
(1)
10
(2)
(3)
1
-1
10
-3
-2
-1
10
10
10
1
AL
10
t
(ms)
(1) Tj (init) = 25 °C; (2) Tj (init) = 150 °C; (3) Repetitive Avalanche
Fig. 4. Avalanche rating; avalanche current as a function of avalanche time
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from Fig. 5
junction to mounting
base
-
-
2.36
K/W
Rth(j-a)
thermal resistance from Minimum footprint; mounted on a
-
95
-
K/W
junction to ambient
printed circuit board
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
4 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
003aaj748
10
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
0.02
t
p
-1
P
10
δ =
T
single shot
t
t
p
T
-2
10
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
t
p
(s)
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics FET1 and FET2
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
54
60
1.4
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9;
1.7
2.1
voltage
Fig. 10
ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 9
ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 9
VDS = 60 V; VGS = 0 V; Tj = 25 °C
VDS = 60 V; VGS = 0 V; Tj = 175 °C
VGS = -10 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; VDS = 0 V; Tj = 25 °C
VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 11
0.5
-
-
V
-
-
-
-
-
-
-
-
2.45
1
V
IDSS
drain leakage current
gate leakage current
0.02
-
µA
µA
nA
nA
mΩ
mΩ
500
100
100
12.5
28.3
IGSS
2
2
RDSon
drain-source on-state
resistance
10
22
VGS = 5 V; ID = 10 A; Tj = 175 °C;
Fig. 11; Fig. 12
VGS = 10 V; ID = 10 A; Tj = 25 °C;
Fig. 11
-
9
11.2
mΩ
Dynamic characteristics FET1 and FET2
QG(tot)
QGS
QGD
Ciss
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
ID = 10 A; VDS = 48 V; VGS = 5 V;
Tj = 25 °C; Fig. 13; Fig. 14
-
-
-
-
-
-
22.4
5.2
-
-
-
nC
nC
nC
7.9
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 15
2215 2953 pF
Coss
Crss
225
116
270
159
pF
pF
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 48 V; RL = 5 Ω; VGS = 5 V;
RG(ext) = 5 Ω; Tj = 25 °C
-
-
-
13
-
-
-
ns
ns
ns
22.1
30.5
td(off)
turn-off delay time
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
5 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tf
fall time
-
21.8
-
ns
Source-drain diode FET1 and FET2
VSD
trr
source-drain voltage
IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 16
-
-
-
0.8
1.2
V
reverse recovery time IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
22.7
18.9
-
-
ns
nC
VDS = 30 V; Tj = 25 °C
Qr
recovered charge
003aak102
003aak101
40
32
24
16
8
50
I
D
R
(mΩ)
10 V
4.5 V
2.8 V
DSon
(A)
40
30
20
10
0
V
= 2.6 V
GS
2.4 V
2.2 V
0
0
1
2
3
4
0
2
4
6
8
GS
10
V
DS
(V)
V
(V)
Tj = 25 °C; tp = 300 μs
Tj = 25 °C; ID = 10 A
Fig. 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
aaa-016783
003aah025
120
3
VGS(th)
(V)
I
D
(A)
100
80
60
40
20
0
2.5
max
2
typ
1.5
min
1
175°C
T = 25°C
j
0.5
0
-60
0
60
120
180
0
1
2
3
4
5
T ( C)
°
j
V
(V)
GS
VDS = 10 V
ID = 1 mA; VDS = VGS
Fig. 8. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
Fig. 9. Gate-source threshold voltage as a function of
junction temperature
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
6 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
003aah026
003aak107
10-1
50
R
(mΩ)
DSon
ID
(A)
2.6 V
2.8 V
10-2
10-3
10-4
10-5
40
30
20
10
0
min
typ
max
3 V
4.5 V
V
= 10 V
GS
10-6
0
1
2
3
0
5
10
15
20
25
30
35
(A)
40
VGS (V)
I
D
Tj = 25 °C; tp = 300 μs
Tj = 25 °C; VDS = 5 V
Fig. 11. Drain-source on-state resistance as a function
of drain current; typical values
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
003aaj816
2.4
V
DS
a
I
D
1.6
V
V
GS(pl)
GS(th)
0.8
V
GS
Q
GS2
Q
GS1
0
-60
Q
Q
0
60
120
180
GS
GD
Tj °C)
(
Q
G(tot)
003aaa508
Fig. 13. Gate charge waveform definitions
Fig. 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
7 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
003aak104
003aak105
4
3
2
10
10
V
GS
C
(V)
(pF)
C
iss
8
6
4
2
0
V
DS
= 14 V
10
C
C
oss
48 V
10
rss
10
10
-1
2
0
10
20
30
40
(nC)
50
1
10
10
Q
G
V
(V)
DS
Tj = 25 °C; ID = 10 A
VGS = 0 V; f = 1 MHz
Fig. 14. Gate-source voltage as a function of gate
charge; typical values
Fig. 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aak106
40
I
S
(A)
30
20
10
0
175°C
0.4
T = 25°C
j
0
0.2
0.6
0.8
1
1.2
V
SD
(V)
VGS = 0 V
Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
©
PSMN013-60HL
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Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
8 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
11. Package outline
Plastic single ended surface mounted package LFPAK56D; 8 leads
SOT1205
E
A
A
b
c
1
1
L
1
mounting
base
D
1
D
2
D
H
L
1
2
3
4
X
b
(8x)
e
c
E
1
w
A
E
2
C
A
1
θ
L
p
y
C
detail X
0
2.5
5 mm
scale
Dimensions
Unit
D
(ref)
2
(1)
(1)
(1)
E
(1)
A
A
b
b
c
c
D
D
1
E
E
e
H
L
L
L
p
w
y
θ
1
1
1
1
2
1
°
8
0
max 1.05 0.1 0.50 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85
nom
min 1.02 0.0 0.35 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60
6.2 1.3 0.55 0.85
5.9 0.8 0.30 0.40
mm
1.27
0.25 0.1
°
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot1205_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
JEITA
14-08-21
14-10-28
SOT1205
Fig. 17. Package outline LFPAK56D; Dual LFPAK (SOT1205)
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
9 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
12. Soldering
Footprint information for reflow soldering of LFPAK56D package
SOT1205
5.85
0.57
0.57
0.7
1.97
1.27
0.65
0.025
1.9
3.325
3.175
3.2
2.0
1.275
0.8
1.0
1.875
2.1
2.7
3.85
3.975
0.025
1.1
1.15
0.65
1.27
1.44
0.7
1.1
solder land
solder land plus solder paste
solder paste deposit
occupied area
14-07-28
solder resist
Dimensions in mm
sot1205_fr
Issue date
20-04-20
Fig. 18. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205)
©
PSMN013-60HL
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Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
10 / 12
Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
13. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
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and products using Nexperia products, and Nexperia accepts no liability for
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minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
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or problem which is based on any weakness or default in the customer’s
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[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
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intended for quick reference only and should not be relied upon to contain
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full data sheet, which is available on request via the local Nexperia sales
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©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
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Nexperia
PSMN013-60HL
N-channel 60 V, 12.5 mOhm, logic level MOSFET in LFPAK56D using TrenchMOS technology
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking..........................................................................2
8. Limiting values............................................................. 2
9. Thermal characteristics............................................... 4
10. Characteristics............................................................5
11. Package outline.......................................................... 9
12. Soldering................................................................... 10
13. Legal information......................................................11
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 30 September 2022
©
PSMN013-60HL
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
30 September 2022
12 / 12
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