PSMN4R2-40VSH [NEXPERIA]
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)Production;
| 型号： | PSMN4R2-40VSH |
| 厂家： | 
Nexperia |
| 描述： | Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)Production |
| 文件： | 总12页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in
LFPAK56D (half-bridge configuration)
16 August 2021
Product data sheet
1. General description
D1
Dual, standard level N-channel MOSFET in an LFPAK56D package (half-
bridge configuration), using NextpowerS3 technology.
G1
An internal connection is made between the source (S1) of the high-side
FET to the drain (D2) of the low-side FET, making the device ideal to use
as a half-bridge switch in high-performance PWM and space constrained
motor drive applications
S1, D2
G2
S2
aaa-028081
2. Features and benefits
•
LFPAK56D package with half-bridge configuration enables:
•
•
•
•
•
Reduced PCB layout complexity
Module shrinkage through reduced component count
Improved system level Rth(j-amb) due to optimized package design
Lower parasitic inductance to support higher efficiency
Footprint compatibility with LFPAK56D Dual package
•
•
•
•
•
•
NextpowerS3 technology
Low power losses, high power density
Superior avalanche performance
Repetitive avalanche rated
LFPAK copper clip packaging provides high robustness and reliability
Gull wing leads support high manufacturability and Automated Optical Inspection (AOI)
3. Applications
•
•
•
•
Handheld power tools, portable appliance and space constrained applications
Brushless or brushed DC motor drive
DC-to-DC systems
LED lighting
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Limiting values FET1 and FET2
VDS
ID
drain-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
-
-
-
-
-
40
V
VGS = 10 V; Tmb = 25 °C; Fig. 2
[1]
-
98
A
Ptot
Tj
total power dissipation Tmb = 25 °C; Fig. 1
junction temperature
-
85
W
°C
-55
175
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics FET1 and FET2
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 20 A; Tj = 25 °C; Fig. 8
-
3.5
4.2
mΩ
Dynamic characteristics FET1 and FET2
QGD
gate-drain charge
total gate charge
ID = 20 A; VDS = 32 V; VGS = 10 V;
Fig. 10; Fig. 11
1.4
17
4.7
26
9.4
37
nC
nC
QG(tot)
[1] 98A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol
S2
Description
source2
Simplified outline
Graphic symbol
8
7
6
5
D1
2
G2
gate2
3
S1
source1
G1
G2
4
G1
gate1
S1, D2
5
D1
drain1
6
D1
drain1
7
S1, D2
S1, D2
source1, drain2
source1, drain2
1
2
3
4
S2
aaa-028081
8
LFPAK56D; Dual
LFPAK (SOT1205)
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
PSMN4R2-40VSH
LFPAK56D;
Dual LFPAK
plastic, single ended surface mounted package
(LFPAK56D); 8 leads
SOT1205
7. Marking
Table 4. Marking codes
Type number
Marking code
4H2S40V
PSMN4R2-40VSH
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Limiting values FET1 and FET2
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
-
40
45
V
V
VDSM
peak drain-source
voltage
tp = 20 ns; f = 500 kHz; EDS(AL) = 200 nJ;
pulsed
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PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
2 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
VDGR
VGS
Parameter
Conditions
Min
Max
40
Unit
V
drain-gate voltage
gate-source voltage
total power dissipation
drain current
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
Tj ≤ 175 °C
-
-20
20
V
Ptot
Tmb = 25 °C; Fig. 1
-
85
W
A
ID
VGS = 10 V; Tmb = 25 °C; Fig. 2
VGS = 10 V; Tmb = 100 °C; Fig. 2
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
[1]
-
98
-
69.5
393
175
175
260
A
IDM
peak drain current
storage temperature
junction temperature
-
A
Tstg
Tj
-55
-55
-
°C
°C
°C
Tsld(M)
peak soldering
temperature
Source-drain diode FET1 and FET2
IS
source current
Tmb = 25 °C
-
-
85
A
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
393
Avalanche ruggedness FET1 and FET2
EDS(AL)S non-repetitive drain-
ID = 82.6 A; Vsup ≤ 40 V; RGS = 50 Ω;
-
-
42.3
82.6
mJ
A
source avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped;
tp = 20 µs
IAS
non-repetitive avalanche Vsup = 40 V; VGS = 10 V; Tj(init) = 25 °C;
[2]
current
RGS = 50 Ω
[1] 98A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
[2] Protected by 100% test
03aa16
aaa-032380
120
100
80
60
40
20
0
I
D
(A)
P
der
(%)
80
40
0
0
50
100
150
200
0
25
50
75 100 125 150 175 200
T
mb
(°C)
T
(°C)
mb
VGS ≥ 10 V
(1) 98A continuous current has been successfully
demonstrated during application tests. Practically
the current will be limited by PCB, thermal design
and operating temperature.
Fig. 1. Normalized total power dissipation as a
function of mounting base temperature
Fig. 2. Continuous drain current as a function of
mounting base temperature, FET1 and FET2
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PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
3 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
aaa-032382
3
2
10
I
D
(A)
Limit R
= V / I
DS D
DSon
t
p
= 10 µs
10
100 µs
10
DC
1 ms
1
10 ms
100 ms
-1
10
-1
2
10
1
10
10
V
DS
(V)
Tmb = 25 °C; IDM is a single pulse
Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from Fig. 4
junction to mounting
base
-
1.64
1.76
K/W
aaa-032383
10
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
t
p
-1
P
10
0.05
δ =
T
0.02
single shot
t
t
p
T
-2
10
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
t
p
(s)
Fig. 4. Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and
FET2
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PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
4 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics FET1 and FET2
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
40
36
2.4
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS=VGS; Tj = 25 °C
voltage
3
3.6
ΔVGS(th)/ΔT
gate-source threshold 25 °C ≤ Tj ≤ 150 °C
voltage variation with
-
-6.2
-
mV/K
temperature
IDSS
drain leakage current
gate leakage current
VDS = 40 V; VGS = 0 V; Tj = 25 °C
VDS = 16 V; VGS = 0 V; Tj = 125 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 20 A; Tj = 25 °C; Fig. 8
-
-
-
-
-
-
0.01
0.3
2
1
µA
µA
nA
10
IGSS
100
100
4.2
8.8
2
nA
RDSon
drain-source on-state
resistance
3.5
-
mΩ
mΩ
VGS = 10 V; ID = 20 A; Tj = 175 °C;
Fig. 9
RG
gate resistance
f = 1 MHz; Tj = 25 °C
0.72
17
1.8
26
4.5
37
Ω
Dynamic characteristics FET1 and FET2
QG(tot)
total gate charge
ID = 20 A; VDS = 32 V; VGS = 10 V;
Fig. 10; Fig. 11
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
13
-
nC
nC
nC
QGS
gate-source charge
ID = 20 A; VDS = 32 V; VGS = 10 V;
Fig. 10; Fig. 11
4.7
3
7.8
5.1
12
7.7
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
1.6
2.7
4
nC
QGD
gate-drain charge
1.4
-
4.7
4.4
9.4
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 20 A; VDS = 32 V; Fig. 10; Fig. 11
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 12
1202 1850 2590 pF
367
27
565
91
791
200
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 30 V; RL = 1.5 Ω; VGS = 10 V;
RG(ext) = 5 Ω
-
-
-
-
-
7
-
-
-
-
-
ns
ns
ns
ns
nC
9
turn-off delay time
fall time
19
11.8
22
Qoss
output charge
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Tj = 25 °C
Source-drain diode FET1 and FET2
VSD
source-drain voltage
IS = 20 A; VGS = 0 V; Tj = 25 °C; Fig. 13
-
0.81
1
V
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PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
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Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
Parameter
Conditions
Min
Typ
18.6
9.2
Max
Unit
ns
trr
Qr
ta
reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
-
-
-
-
-
VDS = 20 V; Fig. 14
recovered charge
[1]
nC
ns
reverse recovery rise
time
10.3
tb
reverse recovery fall
time
-
8.2
-
ns
[1] includes capacitive recovery
aaa-032384
aaa-032385
80
10
I
R
(mΩ)
D
V
GS
= 5.5 V
DSon
5 V
(A)
64
48
32
16
0
8
6
4
2
0
10 V
4.5 V
4 V
0
1
2
3
DS
4
0
4
8
12
16
V (V)
GS
20
V
(V)
Tj = 25 °C
Tj = 25 °C; ID = 20 A
Fig. 5. Output characteristics; drain current as a
function of drain-source voltage; typical values,
FET1 and FET2
Fig. 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values, FET1 and
FET2
aaa-033171
aaa-032387
160
20
I
R
(mΩ)
D
DSon
4.5 V
5 V
(A)
16
12
8
120
80
40
0
5.5 V
4
175°C
25°C
5
V
GS
= 10 V
6 V 8 V
32
0
0
1
2
3
4
6
(V)
7
0
16
48
64
I (A)
D
80
V
GS
VDS = 8 V
Tj = 25 °C
Fig. 7. Transfer characteristics; drain current as a
function of gate-source voltage; typical values,
FET1 and FET2
Fig. 8. Drain-source on-state resistance as a function
of drain current; typical values, FET1 and FET2
©
PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
6 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
aaa-032388
aaa-032389
2.4
1.8
1.2
0.6
0
10
8
a
V
GS
(V)
6
32 V
= 14 V
4
V
DS
2
0
-60 -30
0
30
60
90 120 150 180
0
4
8
12
16
20
24
28
Q (nC)
G
32
T (°C)
j
Tj = 25 °C; ID = 20 A
Fig. 10. Gate-source voltage as a function of gate
charge; typical values, FET1 and FET2
Fig. 9. Normalized drain-source on-state resistance
factor as a function of junction temperature,
FET1 and FET2
aaa-032390
4
10
C
(pF)
V
DS
I
D
C
C
iss
3
2
10
10
oss
V
V
GS(pl)
GS(th)
C
rss
V
GS
Q
GS2
Q
GS1
10
10
Q
Q
-1
2
GS
GD
1
10
10
V
DS
(V)
Q
G(tot)
003aaa508
VGS = 0 V; f = 1 MHz
Fig. 11. Gate charge waveform definitions
Fig. 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values, FET1 and FET2
©
PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
7 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
003aal160
aaa-033170
2
10
I
S
I
D
(A)
(A)
t
rr
t
t
b
a
0
10
0.25 I
RM
175°C
0.4
T = 25°C
j
I
RM
1
t (s)
0
0.2
0.6
0.8
1
(V)
1.2
V
SD
Fig. 14. Reverse recovery timing definition
VGS = 0 V
Fig. 13. Source-drain (diode forward) current as a
function of source-drain (diode forward)
voltage; typical values, FET1 and FET2
©
PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
8 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
11. Package outline
Plastic single ended surface mounted package LFPAK56D; 8 leads
SOT1205
E
A
A
b
c
1
1
L
1
mounting
base
D
1
D
2
D
H
L
1
2
3
4
X
b
(8x)
e
c
E
1
w
A
E
2
C
A
1
θ
L
p
y
C
detail X
0
2.5
5 mm
scale
Dimensions
Unit
D
(ref)
2
(1)
(1)
(1)
E
(1)
A
A
b
b
c
c
D
D
1
E
E
e
H
L
L
L
p
w
y
θ
1
1
1
1
2
1
°
8
0
max 1.05 0.1 0.50 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85
nom
min 1.02 0.0 0.35 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60
6.2 1.3 0.55 0.85
5.9 0.8 0.30 0.40
mm
1.27
0.25 0.1
°
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot1205_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
JEITA
14-08-21
14-10-28
SOT1205
Fig. 15. Package outline LFPAK56D; Dual LFPAK (SOT1205)
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PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
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Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
12. Soldering
Footprint information for reflow soldering of LFPAK56D package
SOT1205
5.85
0.57
0.57
0.7
1.97
1.27
0.65
0.025
1.9
3.325
3.175
3.2
2.0
1.275
0.8
1.0
1.875
2.1
2.7
3.85
3.975
0.025
1.1
1.15
0.65
1.27
1.44
0.7
1.1
solder land
solder land plus solder paste
solder paste deposit
occupied area
14-07-28
solder resist
Dimensions in mm
sot1205_fr
Issue date
20-04-20
Fig. 16. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205)
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PSMN4R2-40VSH
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Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
10 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
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13. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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Document status Product
Definition
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products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
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data sheet
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the objective specification for
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Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
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Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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©
PSMN4R2-40VSH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
11 / 12
Nexperia
PSMN4R2-40VSH
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking..........................................................................2
8. Limiting values............................................................. 2
9. Thermal characteristics............................................... 4
10. Characteristics............................................................5
11. Package outline.......................................................... 9
12. Soldering................................................................... 10
13. Legal information......................................................11
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 16 August 2021
©
PSMN4R2-40VSH
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
12 / 12
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