DP7112 [NIDEC]
32-Tap Digital Potentiometer;
| 型号： | DP7112 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | 32-Tap Digital Potentiometer |
| 文件： | 总10页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7112
32-Tap Digital Potentiometer (DP)
with Buffered Wiper
Description
The DP7112 is
a
single digital potentiometer (DP)
designed as an electronic replacement for mechanical
potentiometers. Ideal for automated adjustments on high volume
production lines, they are also well suited for applications where
equipment requiring periodic adjustment is either difficult to access or
located in a hazardous or remote environment.
SOICï8
The DP7112 contains a ꢀꢁïWDS series resistor array connected
MSOPï8
between two terminals R and R . An up/down counter and decoder
H
L
that are controlled by three input pins, determines which tap is
connected to the wiper, R . The DP7112 wiper is buffered by an op
WB
amp that operates rail to rail. The wiper setting, stored in nonïvolatile
memory, is not lost when the device is powered down and is
automatically recalled when power is returned. The wiper can be
adjusted to test new system values without effecting the stored setting.
Wiperïcontrol of the DP7112 is accomplished with three input
control pins, CS, U/D, and INC. The INC input increments the wiper
in the direction which is determined by the logic state of the U/D input.
The CS input is used to select the device and also store the wiper
position prior to power down.
The digital potentiometer can be used as a buffered voltage
divider. For applications where the potentiometer is used as a
2ïterminal variable resistor, please refer to the DP7114. The
buffered wiper of the DP7112 is not compatible with that
application.
TSSOPï8
PIN CONFIGURATIONS
1
V
INC
U/D
H
GND
CC
CS
L
WB
R
R
R
SOIC (V),
MSOP (Z)
1
R
R
CS
L
Features
V
CC
INC
U/D
WB
GND
v 32ïposition Linear Taper Potentiometer
v Nonïvolatile EEPROM Wiper Storage; Buffered Wiper
v Low Power CMOS Technology
R
H
TSSOP (Y)
(Top Views)
v Single Supply Operation: 2.5 V ï 6.0 V
v Increment Up/Down Serial Interface
PIN FUNCTION
v Resistance Values: 10 k , 50 k and 100 k
v Available in SOIC, TSSOP and MSOP Packages
Pin Name
INC
Function
Increment Control
Up/Down Control
v These Devices are PbïFree, Halogen Free/BFR Free and are RoHS
U/D
Compliant
R
Potentiometer High Terminal
Ground
H
Applications
GND
v Automated Product Calibration
v Remote Control Adjustments
v Offset, Gain and Zero Control
v Tamperïproof Calibrations
v Contrast, Brightness and Volume Controls
v Motor Controls and Feedback Systems
v Programmable Analog Functions
R
WB
Buffered Wiper Terminal
Potentiometer Low Terminal
Chip Select
R
L
CS
V
CC
Supply Voltage
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
¢ NIDEC COPAL ELECTRONICS CORP
August, 2010 ï Rev. 14
1
Publication Order Number:
DP7112/D
DP7112
DEVICE MARKING INFORMATION
MSOP
SOIC
TSSOP
CPL-E RR
DP7112VI
YYWWP
AAPN
YMP
YMPR
7112YI
RR = Resistance:
Y = Production Year (Last Digit)
M = Production Month
(ꢀï9, A, B, C or O, N, D)
P = Product Revision
R = Resistance:
10 = 10 k
AAPN = DP7112ZIï10ïGT3
AAPP = DP7112ZIï50ïGT3
Y = Production Year (Last Digit)
M = Production Month
50 = 50 k
00 = 100 k
DP7112V = Device Code (SOIC)
I = Temperature Range (Industrial)
YY = Production Year (Last two Digit)
WW = Production Week
A = Product Revision
1 = 10 k
(ꢀï9, A, B, C or O, N, D)
P = Product Revision
5 = 50 k
0 = 100 k
7112Y = Device Code (TSSOP)
I = Temperature Range (Industrial)
R
H
V
CC
R
H
U/D
Control
and
+
–
INC
CS
+
–
R
R
WB
Memory
R
R
WB
Power On Recall
GND
L
L
Figure 1. Functional Diagram
Figure 2. Electronic Potentiometer Implementation
2
DP7112
Pin Description
INC: Increment Control Input
The INC input (on the falling edge) moves the wiper in the
up or down direction determined by the condition of the U/D
input.
Device Operation
The DP7112 operates like a digital potentiometer
with R and R equivalent to the high and low
H
L
WB
terminals and
R
equivalent to the mechanical
potentiometer·s wiper. There are 32 available tap positions
including the resistor end points, R and R . There are 31
H
L
U/D: Up/Down Control Input
resistor elements connected in series between the R and R
H
L
The U/D input controls the direction of the wiper movement.
When in a high state and CS is low, any highïtoïlow
transition on INC will cause the wiper to move one
terminals. The wiper terminal is connected to one of the 32
taps and controlled by three inputs, INC, U/D and CS. These
inputs control a fiveïbit up/down counter whose output is
decoded to select the wiper position. The selected wiper
position can be stored in nonvolatile memory using the INC
and CS inputs.
increment toward the R terminal. When in a low state and
H
CS is low, any highïtoïlow transition on INC will cause the
wiper to move one increment towards the R terminal.
L
With CS set LOW the DP7112 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC will increment or decrement the wiper
(depending on the state of the U/D input and fiveïbit
counter). The wiper, when at either fixed terminal, acts like
its mechanical equivalent and does not move beyond the last
position. The value of the counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
LVꢂDOVRꢂ+,*+ꢃꢂ:KHQꢂWKHꢂ'3ꢄꢅꢅꢁꢂLVꢂSRZHUHGïGRZQꢆꢂWKHꢂODVW
stored wiper counter position is maintained in the
nonvolatile memory. When power is restored, the contents
of the memory are recalled and the counter is set to the value
stored.
R : High End Potentiometer Terminal
H
R
is the high end terminal of the potentiometer. It is not
H
required that this terminal be connected to a potential greater
than the R terminal. Voltage applied to the R terminal
L
H
cannot exceed the supply voltage, V or go below ground,
CC
GND.
R : Wiper Potentiometer Terminal (Buffered)
WB
R
is the buffered wiper terminal of the potentiometer. Its
WB
position on the resistor array is controlled by the control
inputs, INC, U/D and CS.
R : Low End Potentiometer Terminal
L
R is the low end terminal of the potentiometer. It is not
L
With INC set low, the DP7112 may be deselected and
powered down without storing the current wiper position in
nonvolatile memory. This allows the system to always
power up to a preset value stored in nonvolatile memory.
required that this terminal be connected to a potential less
than the R terminal. Voltage applied to the R terminal
H
L
cannot exceed the supply voltage, V or go below ground,
CC
GND. R and R are electrically interchangeable.
L
H
CS: Chip Select
The chip select input is used to activate the control input of
the DP7112 and is active low. When in a high state, activity
on the INC and U/D inputs will not affect or change the
position of the wiper.
3
DP7112
Table 1. OPERATION MODES
INC
High to Low
High to Low
High
CS
U/D
High
Low
X
Operation
Low
Wiper toward R
H
Low
Wiper toward R
L
Low to High
Low to High
High
Store Wiper Position
No Store, Return to Standby
Standby
Low
X
X
X
R
H
C
H
R
WI
R
WB
C
W
C
L
R
L
Figure 3. Potentiometer Equivalent Circuit
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Supply Voltage
V
V
to GND
ï0.5 to +7
CC
Inputs
V
CS to GND
INC to GND
U/D to GND
ï0.5 to V +0.5
CC
ï0.5 to V +0.5
V
V
V
V
V
CC
ï0.5 to V +0.5
CC
R
to GND
ï0.5 to V +0.5
CC
H
R to GND
L
ï0.5 to V +0.5
CC
R
WB
to GND
ï0.5 to V +0.5
CC
Operating Ambient Temperature
,QGXVWULDOꢁꢂ¶,·ꢁVXffix)
ï40 to +85
+150
oC
oC
oC
oC
Junction Temperature
Storage Temperature
Lead Soldering (10 s max)
ï65 to +150
+300
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
Parameter
ESD Susceptibility
LatchïUp
Test Method
Min
2000
Typ
Max
Units
V
V
(Note 1)
MILïSTDï883, Test Method 3015
JEDEC Standard 17
ZAP
I
(Notes 1, 2)
100
mA
LTH
T
Data Retention
Endurance
MILïSTDï883, Test Method 1008
MILïSTDï883, Test Method 1003
100
Years
Stores
DR
N
1,000,000
END
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to V + 1 V
CC
4
DP7112
Table 4. DC ELECTRICAL CHARACTERISTICS (V = +2.5 V to +6 V unless otherwise specified)
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
V
I
Operating Voltage Range
Supply Current (Increment)
2.5
–
–
–
6
V
A
A
A
A
A
CC
V
V
= 6 V, f = 1 MHz, I = 0
200
100
1000
500
150
CC1
CC2
CC
W
= 6 V, f = 250 kHz, I = 0
–
–
CC
W
I
Supply Current (Write)
Programming, V = 6 V
–
–
CC
V
CC
= 3 V
–
–
I
(Note 4)
Supply Current (Standby)
CS = V ï 0.3 V
–
75
SB1
CC
U/D, INC = V ï 0.3 V or GND
CC
LOGIC INPUTS
I
Input Leakage Current
V
V
= V
CC
–
–
2
0
–
–
–
–
–
–
10
A
A
V
V
V
V
IH
IN
I
Input Leakage Current
= 0 V
ï10
IL
IN
V
IH1
TTL High Level Input Voltage
TTL Low Level Input Voltage
CMOS High Level Input Voltage
CMOS Low Level Input Voltage
4.5 V b V b 5.5 V
V
CC
CC
V
0.8
+ 0.3
IL1
V
IH2
2.5 V b V b 6 V
V
CC
x 0.7
V
CC
CC
V
ï0.3
V
x 0.2
IL2
CC
POTENTIOMETER CHARACTERISTICS
R
Potentiometer Resistance
ï10 Device
ï50 Device
ï00 Device
10
50
k
POT
100
Pot. Resistance Tolerance
p20
%
V
V
RH
Voltage on R pin
0
0
V
CC
V
CC
H
V
RL
Voltage on R pin
V
L
Resolution
1
%
INL
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
I
I
b 2
b 2
A
A
0.5
0.25
1
LSB
LSB
W
DNL
0.5
1
W
R
0.05 V b V
b 0.95 V
b 0.95 V
,
,
OUT
CC
WB
CC
V
= 5 V
CC
I
Buffer Output Current
0.05 V b V
3
mA
OUT
CC
WB
CC
V
= 5 V
CC
TC
TC of Pot Resistance
Ratiometric TC
300
20
ppm/oC
ppm/oC
pF
RPOT
TC
RATIO
C
/C /C
RH RL RW
Potentiometer Capacitances
Frequency Response
Output Voltage Range
8/8/25
1.7
fc
Passive Attenuator, 10 k
b 100 A, V = 5 V
MHz
V
I
0.01 V
0.99 V
CC
WB(SWING)
OUT
CC
CC
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to V + 1 V
CC
5. I = source or sink
W
6. These parameters are periodically sampled and are not 100% tested.
5
DP7112
Table 5. AC TEST CONDITIONS
V
CC
Range
2.5 V b V b 6 V
CC
Input Pulse Levels
0.2 V to 0.7 V
CC
CC
Input Rise and Fall Times
Input Reference Levels
10 ns
0.5 V
CC
Table 6. AC OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, V = V , V = 0 V, unless otherwise specified)
CC
H
CC
L
Symbol
Parameter
Min
100
50
100
250
250
1
Typ (Note 7)
Max
Units
ns
ns
ns
ns
ns
s
t
CI
t
DI
t
ID
CS to INC Setup
U/D to INC Setup
U/D to INC Hold
INC LOW Period
INC HIGH Period
ï
ï
ï
ï
ï
ï
ï
ï
1
ï
ï
–
5
ï
ï
ï
t
ï
IL
IH
IC
t
t
ï
INC Inactive to CS Inactive
CS Deselect Time (NO STORE)
CS Deselect Time (STORE)
ï
t
t
100
10
ï
ï
ns
ms
s
CPH
CPH
ï
t
IW
INC to V
Change
5
OUT
t
INC Cycle Time
1
ï
s
CYC
t , t (Note 8) INC Input Rise and Fall Time
ï
500
1
s
R
F
t
(Note 8)
Powerïup to Wiper Stable
–
ms
ms
PU
t
Store Cycle
–
10
WR
7. Typical values are for T = 25oC and nominal supply voltage.
A
8. This parameter is periodically sampled and not 100% tested.
9. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
CS
(store)
CPH
t
CYC
t
t
IC
t
CI
t
IL
t
IH
90%
90%
10%
INC
U/D
t
DI
t
ID
t
F
t
R
(Note 9)
t
IW
MI
R
WB
Figure 4. A.C. Timing
6
DP7112
PACKAGE DIMENSIONS
SOIC 8, 150 mils
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
Q
TOP VIEW
D
h
A1
Q
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
7
DP7112
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
Q
e
TOP VIEW
D
c
A2
A
1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
8
DP7112
PACKAGE DIMENSIONS
MSOP 8, 3x3
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
Q
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
9
DP7112
Example of Ordering Information (Note 12)
Prefix
Device #
Suffix
DP
7112
V
I
ï10
ï G
T3
Temperature Range
I = Industrial (ï40oC to +85oC)
Lead Finish (Note 13)
Tape & Reel
T: Tape & Reel
3: 3,000 Units / Reel
Company ID
(Optional)
G: NiPdAu
Blank: MatteïTin
Product Number
7112
Resistance
ï10: 10 k
ï50: 50 k
ï00: 100 k
Package
V: SOIC
Y: TSSOP
Z: MSOP
Table 7. ORDERING INFORMATION
Orderable Part Number
DP7112VI ï10ïGT3
DP7112VI ï50ïGT3
DP7112VI ï00ïGT3
DP7112YI ï10ïGT3
DP7112YI ï50ïGT3
DP7112YI ï00ïGT3
DP7112ZI ï10ïGT3
DP7112ZI ï50ïGT3
DP7112ZI ï00ïGT3
Resistance (k )
PackageïPins
SOICï8
Lead Finish (Note 13)
10
50
100
10
50
TSSOPï8
MSOPï8
NiPdAu
100
10
50
100
10.All packages are RoHSïcompliant (Leadïfree, Halogenïfree).
11. The standard lead finish is NiPdAu.
12.The device used in the above example is a DP7112VIï10ïGT3 (SOIC, Industrial Temperature, 10 k , NiPdAu, Tape & Reel, 3,000/Reel).
13.Contact factory for MatteïTin finish.
NIDEC COPAL reserves the right to make changes without further notice to any products herein.
NIDEC COPAL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NIDEC COPAL assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in NIDEC COPAL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
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NIDEC COPAL does not convey any license under its patent rights nor the rights of others.
NIDEC COPAL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the NIDEC COPAL product could create a situation where personal injury or death may occur.
Should Buyer purchase or use NIDEC COPAL products for any such unintended or unauthorized application, Buyer shall indemnify and hold NIDEC COPAL and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NIDEC COPAL was negligent regarding the design or
manufacture of the part.
DP7112/D
10
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