DP7140 [NIDEC]

Single Channel 256 Tap;


型号：	DP7140
厂家：	NIDEC COMPONENTS
描述：	Single Channel 256 Tap
文件：	总11页 (文件大小：144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP7140

Single Channel 256 Tap

DP with Integrated

EEPROM and I²C Control

The DP7140 is a single channel non-volatile ꢀꢁꢂïWDS digital

SRWHQWLRPHWHU (DP). This DP is FRPSULVHG of a VHULHs of equal

value UHVLVWRU HOHPHQWV connected between two H[WHUQDOOy

accessible end SRLQWVꢃ The WDS SRLQWV between each UHVLVWLYe

HOHPHQt can be selectively connected to the ZLSHU RXWSXW via LQWHUQDO

CMOSꢄVZLWFKHVꢄIRUPLQJꢄDꢄOLQHDUꢄWDSHUꢄHOHFWURQLFꢄSRWHQWLRPHWHU.

The DP7140 contains a volatile ZLSHU UHJLVWHU (WR) and an ꢅïELW

nonïvolatile EEPROM foU wiSeU SRVition and 5 additional

nonïvolatile UHJLVWHUV IRU JHQHUDO SXUSRVH data VWRUDJHꢃ 3URJUDPPLQJ

MSOPï8 3x3

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MSOPꢄSDFNDJHꢆ and oSHUates oveUꢄthe industUial WHPSeUatuUeꢄUange of

ï40oC to +85oC.

MARKING DIAGRAM

Features

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ABTJ

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v ꢀꢁꢂꢄ3RVLWLRQꢄ/LQHDUꢄTDSHUꢄ3RWHQWLRPHWHU

v EndïtoïEnd Resistance = 50 k / 100 k

v 7&5ꢄ ꢄꢉꢊꢊꢄSSP/o&ꢄꢇW\SLFDOꢈ

ABTV = 100 k Resistance

ABTJ = 50 k Resistance

Y = Production Year

Y = (Last Digit)

M = Production Month

M = (1 ï 9, A, B, C)

X = Production Revision

v SWDQGE\ꢄ&XUUHQWꢄ ꢄꢀꢄ $ꢄꢇPD[ꢈ

v T\SLFDOꢄWLSHUꢄ5HVLVWDQFHꢄ ꢄꢋꢊ @ 3.3 9

v OSHUDWLQJꢄ9oltage = 2.5 9 to 5.5 9

v ꢂꢄ5HJLVWHUVꢄ8ïbit Nonïvolatile EEPROM

v ꢀꢆꢊꢊꢊꢆꢊꢊꢊꢄData WULWHꢄSWRUHV

v 100 YeaUꢄ'ata Retention

PIN CONNECTIONS

v 8ïLead MSOP Package

v PbïIUHHꢄ5R+6ꢄ&RPSOLDQWꢌꢄ1L3G$Xꢄ3ODWLQg

SCL

SDA

GND

VCC

Volatile

VCC

ACR

SCL

SDA

GND

WIPER

(Top View)

IVR

ORDERING INFORMATION

NonïVolatile

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Figure 1. Functional Block Diagram

¢ 2009 NIDEC COPAL ELECTRONICS CORP.

May, 2009 ï Rev. 0

Publication Order Number:

DP7140/D

DP7140

Table 1. ORDERING INFORMATION

Part Number

Resistance

Temperature Range

Package

Shipping

DP7140ZIï50ïGT3

DP7140ZIï00ïGT3

50 k

3000/Tape & Reel

MSOPï8 3x3

(PbïFree)

ï40oC to 85oC

100 k

Table 2. PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

Description

Memory Write Protect: Active Low

Serial Clock

SCL

SDA

Serial Data

GND

Ground

Wiper Terminal

Potentiometer Low Terminal

Potentiometer High Terminal

Supply Voltage

WP: Write Protect Input

open drain output and can be wire-Ored with the other open

drain or open collector I/Os.

The WP pin when tied low prevents any write operations

within the device.

R_H, R_L: Resistor End Points

SCL: Serial Clock

The DP7140 serial clock input pin is used to clock all

data transfers into or out of the device.

The set of R and R pins is equivalent to the terminal

connections on a mechanical potentiometer.

R_W: Wiper

SDA: Serial Data

The DP7140 bidirectional serial data pin is used to

transfer data into and out of the device. The SDA pin is an

The R pin is equivalent to the wiper terminal of a

mechanical potentiometer and its position is controlled by

the WR register.

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Unit

Supply Voltage V to Ground (Note 1)

ï0.5 to +7

Terminal voltages: R , R , R , SDA, SCL, WP

ï0.5 to V + 0.5

Wiper Current

Storage Temperature Range

p6.0

ï65 to +150

ï40 to +150

300

Junction Temperature Range

Lead Soldering Temperature (10 seconds)

ESD Rating HBM (Human Body Model)

ESD Rating MM (Machine Model)

2000

200

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.

Table 4. RECOMMENDED OPERATING CONDITIONS

Parameter

Rating

2.5 to 5.5

Unit

Wiper Current

Temperature Range

ï40 to +85

DP7140

Table 5. POTENTIOMETER CHARACTERISTICS (Note 2) (V = +2.5 V to +5.5 V, ï40 C to +85 C unless otherwise specified.)

Limits

Min

Typ

Max

Parameter

Potentiometer Resistance ¶ï50·

Potentiometer Resistance ¶ï00·

Potentiometer Resistance Tolerance

Power Rating

Test Conditions

Symbol

Units

POT

100

(20

25$C

Wiper Current

Wiper Resistance

= (3 mA

200

= 3.3 V

Integral NonïLinearity

Differential NonïLinearity

Integral NonïLinearity

Differential NonïLinearity

Voltage Divider Mode

INL

DNL

(0.5

LSB (Note 3)

Resistor Mode

RINL

RDNL

(0.5

Voltage on R or R

= 0 V

TERM

Resolution

0.4

0.5

Zero Scale Error

Full Scale Error

LSB (Note 4)

ppm/$C

ï2

ï0.5

(100

Temperature Coefficient of R

(Notes 5, 6)

POT

RPOT

Ratiometric Temp. Coefficient

Potentiometer Capacitances

Frequency Response

(Notes 5, 6)

ppm/$C

RATIO

(Notes 5, 6)

C /C /C

10/10/25

0.4

= 50 k (Note 7)

MHz

POT

2. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to V +1 V.

3. LSB = R

/ 255 or (R ï R ) / 255, single pot.

H L

TOT

4. V(R ) ïV(R ) ]/255 (R )

= 0xFF, (R ) = 0x00.

W 0

W 255

W 0

W 255

5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

6. Relative linearity is a measure of the error in step size. It is determined by the actual change in voltage between two successive tap positions

when used as a potentiometer.

7. This parameter is tested initially and after a design or process change that affects the parameter.

Table 6. D.C. OPERATING CHARACTERISTICS (V = +2.5 V to +5.5 V, ï40$C to +85$C unless otherwise specified.)

Parameter

Test Conditions

Symbol

Min

Max

Units

Power Supply Current

Volatile Write & Read

= 400 kHz

SCL

CC1

CC2

= 5.5 V, Inputs = GND

Power Supply Current

Nonïvolatile Write

= 400 kHz

SCL

= 5.5 V, Inputs = GND

Standby Current

= 5.0 V

Input Leakage Current

Output Leakage Current

Input Low Voltage

= GND to V

ï10

ï1

+10

= GND to V

OUT

x 0.3

Input High Voltage

x 0.7

+ 1.0

SDA Output Buffer Low Voltage

PowerïOn Recall

= 2.5 V, I = 4 mA

OL1

0.4

2.0

Minimum V for memory recall

POR

1.4

DP7140

Table 7. CAPACITANCE (T = 25$C, f = 1.0 MHz, V = 5 V)

Test

Test Conditions

Symbol

(Note 8)

Max

Units

Input/Output Capacitance (SDA)

Input Capacitance (SCL, WP)

I/O

= 0 V

I/O

(Note 8)

Table 8. POWER UP TIMING (Notes 8 and 9)

Parameter

Symbol

Max

Units

Powerïup to Read Operation

Powerïup to Write Operation

PUR

PUW

8. This parameter is tested initially and after a design or process change that affects the parameter.

9. t and t are delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

Table 9. DP TIMING

Parameter

Symbol

Min

Max

Units

Wiper Response Time After Power Supply Stable

WRPO

Wiper Response Time: SCL falling edge after last bit of wiper position data

byte to wiper change

Table 10. ENDURANCE

Parameter

Endurance

Data Retention

Reference Test Method

Symbol

Min

2,000,000

100

Max

Units

Cycles

Years

MILïSTDï883, Test Method 1033

MILïSTDï883, Test Method 1008

END

Table 11. A.C. CHARACTERISTICS (V = +2.5 V to +5.5 V, ï40 C to +85 C unless otherwise specified.)

Parameter

Symbol

Min

Typ

Max

Units

Clock Frequency

Clock High Period

Clock Low Period

400

kHz

SCL

600

1300

600

100

HIGH

LOW

Start Condition Setup Time (for a Repeated Start Condition)

Start Condition Hold Time

SU:STA

HD:STA

SU:DAT

HD:DAT

SU:STO

Data in Setup Time

Data in Hold Time

Stop Condition Setup Time

600

1300

Time the bus must be free before a new transmission can start

WP Setup Time

BUF

SU:WP

HD:WP

WP Hold Time

2.5

SDA and SCL Rise Time

300

SDA and SCL Fall Time

Data Out Hold Time

100

Noise Suppression Time Constant at SCL, SDA Inputs

SLC Low to SDA Data Out and ACK Out

NonïVolatile Write Cycle Time

DP7140

SCL

SDA

Start

Condition

Stop

Condition

Figure 2. Start and STOP Timing

HIGH

LOW

SCL

HD:DAT

SU:STA

SU:DAT

SU:STO

HD:STA

SDA IN

BUF

SDA OUT

Figure 3. Bus Timing

Bus Release

Delay (Receiver)

Bus Release Delay (Transmitter)

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

ACK Setup (* t

)

SU:DAT

Start

ACK Delay () t

)

Figure 4. Acknowledge Timing

Start

Stop

SCL

HD:STO, HD:STO:NV

CLK1

SDA IN

HD:WP

SU:WP

Figure 5. WP Timing

DP7140

Device Operation

START Condition

The DP7140 is a resistor array integrated with a I C

serial interface logic, an 8ïbit volatile wiper register, and six

8ïbit, nonïvolatile memory data registers. The resistor

array contains 255 separate resistive elements connected in

series. The physical ends of the array are equivalent to the

The START condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The DP7140 monitors the SDA and

SCL lines and will not respond until this condition is met.

STOP Condition

fixed terminals of a mechanical potentiometer (R and R ).

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

The tap positions between and at the ends of the series

resistors are connected to the output wiper terminal (R ) by

CMOS transistor switches. Only one tap point for the

potentiometer is connected to the wiper terminal at a time

and is determined by the value of an 8ïbit Wiper Register

(WR).

Device Addressing

The bus Master begins a transmission by sending a

START condition. The Master then sends the address of the

particular slave device it is requesting. DP7140 has a fixed

7 bit slave address: 0101000. The 8 bit (LSB) is the

Read/Write instruction bit. For a Read the value is “1” and

for Write the value is “0”.

After the Master sends a START condition and the slave

address byte, the DP7140 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address.

FFh

FEh

80h

Table 12. SALVE ADDRESS BIT FORMAT

MSB

LSB

01h

00h

R/W

Acknowledge (ACK)

After a successful data transfer, each receiving device is

required to generate an acknowledge. The Acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

When power is first applied to DP7140 the wiper is set

to midscale; Wiper Register = 80h. When the power supply

becomes sufficient to read the nonïvolatile memory the

value stored in the Initial Value Register (IVR) is transferred

into the Wiper Register and the wiper moves to this new

position. Five additional 8ïbit nonïvolatile memory data

registers are provided for general purpose data storage. Data

can be read or written to the volatile or the nonïvolatile

DP7140 responds with an acknowledge after receiving

a START condition and its slave address. If the device has

been selected along with a write operation, it responds with

an acknowledge after receiving each 8ïbit byte. When the

DP7140 is in a READ mode it transmits 8 bits of data,

releases the SDA line, and monitors the line for an

acknowledge. Once it receives this acknowledge, the

DP7140 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition.

memory data registers via the I C bus.

Serial Bus Protocol

The following defines the features of the 2ïwire bus

protocol:

1. Data transfer may be initiated only when the bus is

not busy.

WRITE Operation

In the Write mode, the Master device sends the START

condition and the slave address information to the Slave

device. In '3ꢋꢉꢍꢊ·s case the slave address also contains a

Read/Write command (R/W) on the last bit of the 1st byte.

After receiving an acknowledge from the Slave, the Master

device transmits a second byte containing a Memory

Address to select an available register. After a second

acknowledge is received from the Slave, the Master device

sends the data to be written into the selected register. The

DP7140 acknowledges once more and the Master

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high

will be interpreted as a START or STOP condition.

The device controlling the transfer is a master, typically a

processor or controller, and the device being controlled is the

slave. The master will always initiate data transfers and

provide the clock for both transmit and receive operations.

Therefore, the DP7140 will be considered a slave device

in all applications.

DP7140

READ Operation

generates the STOP condition, at which time if a nonvolatile

data register is being selected, the device begins an internal

programming cycle to nonïvolatile memory. If the STOP

condition is not sent immediately after the last ACK the

internal nonïvolatile programming cycle doesn·t start.

While this internal cycle is in progress, the device will not

respond to any request from the Master device.

Write operations to volatile memory are completed during

the last bit of the data byte before the slave·s acknowledge.

The device will be ready for another command only after a

STOP condition sent by Master.

A Read operation with a designated address consists of a

three byte instruction followed by one or more Data Bytes

(See Figure 3). The master initiates the operation issuing a

START, an Identification byte with the R/W bit set to “0”, an

Address Byte. Then the master sends a second START, and

a second Identification byte with the R/W bit set to “1”. After

each of the three bytes, the DP7140 responds with an ACK.

Then DP7140 transmits the Data Byte. The master then can

continue the read operation with the content of the next

operation by issuing a NoACK followed by a STOP

condition after the last bit of a Data Byte.

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host·s write operation, the

DP7140 initiates the internal write cycle. ACK polling can

be initiated immediately. This involves issuing the start

condition followed by the slave address. If the DP7140 is

still busy with the write operation, no ACK will be returned.

If the DP7140 has completed the write operation, an

acknowledge will be returned and the host can then proceed

with the next instruction operation.

Table 13. MEMORY MAP

Nonïvolatile

Default

Value

Volatile

Address

ACR

Reserved

00h

General Purpose

Device ID (read only)

IVR

N/A

00h

D0h

80h

WRITE Protection

The Write Protection feature allows the user to protect

against inadvertent programming of the nonïvolatile data

registers. If the WP pin is tied to LOW, the data registers are

protected and become read only. Similarly, the WP pin going

low after start will interrupt a nonvolatile write to data

registers, while the WP pin going low after an internal write

cycle has started will have no effect on any write operation.

DP7140 will accept slave addresses but the data registers

are protected from programming, which the device indicates

by failing to send an acknowledge after data is received.

If the master sends address 07h or addresses greater than

08h the slave responds with NoACK after the Memory

Address byte.

Address 8: Volatile Access Control Register ï ACR (I/O)

The ACR bit 7 (VOL) toggles between Nonïvolatile and volatile registers accessed at address 00h. When VOL is Low (0),

the nonïvolatile IVR is accessed at address 00h. When VOL is high (1), the volatile Wiper Register is accessed at address 00h.

The initial default value for VOL = 0.

Bit

Name

0/1 VOL

00h and 80h are the only values that should be written to address 08h. For any other value written to address 08h the slave will

load only bit 7 but it will answer with a NoACK.

Address 7: RESERVED

The user should not read or write to this address. DP7140 will respond with NoACK and it will take no action.

Address 07h can be accessed only in a sequential read and its content is FFh.

Address 6ï2: NonïVolatile General Purpose Memory (I/O)

8ïbit Nonïvolatile Memory

Bit

Name

General Purpose Memories are preprogrammed at the factory to a default value of “00h”.

DP7140

Address 1: Device ID (Read Only)

Bit 7 defines the DP device manufacturer; COPAL ELECTRONICS = high (1)

Bit

Name

A writing to address 1 has no effect. Attempts to do so will return an ACK but no data will be written.

Address 0: IVR/WR Register (I/O)

Address 00h accesses one of two memory registers: the initial value register (IVR) or the wiper register (WR) depending

upon the value of bit 7 in Access Control Register (ACR) which is at address 08h, above.

WR controls the wiper·s position and is a volatile memory while IVR is nonïvolatile and retains its data after the chip has

been powered down. Writes to IVR automatically update the WR while writes to WR leave IVR unaffected.

WR: Wiper Register = Volatile.

IVR: Initial Value Register = Nonïvolatile.

Writing and Reading operations:

1. If Bit 7 from ACR is 0 (nonïvolatile):

g A write operation to address 00h will write the same value in WR and IVR.

g A read operation to address 00h will output the content of IVR.

2. If bit 7 from ACR is 1 (volatile):

g A write operation to address 00h will write in WR only.

g A read operation to address 00h will output the content of WR.

All changes to the wiper·s position are immediate. There is no delay the wiper·s movement when writing to nonïvolatile

memory.

Bit

Name

IVR is preprogrammed at the factory to a default value of “80h”.

I C SERIAL BUS INSTRUCTION FORMAT

Table 14. I C SLAVE ADDRESS BITS

Slave Address

R/W bit

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

Transfer Data

Read

Write

51h

50h

1 (R)

0 (W)

If the Slave Address Byte sent by the host is different the device will send a NoACK.

I C Protocol:

(A) Write data procedure with designated address. (See Table 15)

1. Host transfers the start condition

2. Host transfers the device slave address with the write mode R/W bit (0).

3. Device sends ACK

4. Host transfers the corresponding memory address to the device

5. Device sends ACK

6. Host transfers the write data to the designated address

7. Device sends ACK

8. Routines (6) and (7) are repeated based on the transfer data, and the designated address is automatically incremented*

9. Host transfers the stop condition.

*Automatically incremented writes are not possible after a nonïvolatile write.

DP7140

Single write to either a volatile or nonïvolatile register. Note that Bit 7 of ACR determines which memory type is being written.

Table 15. SINGLE WRITE

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(9)

Start

Slave

Address

R/W

ACK

Memory

Address

ACK

Write

Data

Stop

ACK

A single write to either a volatile or nonïvolatile register. At address 00h bit 7 of ACR determines which memory type is being written.

Table 16. MULTIPLE WRITES

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

Start

Slave

Memory

Address

Write

Data

Write

Data

Stop

Address

R/W

ACK

Multiple writes are possible only if the starting address is 08h and it should be stopped with the first nonvolatile data byte. If

a nonvolatile write does not end with a STOP procedure the register is not written.

(B) Read data procedure with designated address.

1. Host transfers the start condition

2. Host transfers the device slave address with the write mode R/W bit (0)

3. ACK signal recognition from the device

4. Host transfers the read address

5. ACK signal recognition from the device

6. Host transfers the reïstart condition

7. Host transfers the slave address with the read mode R/W bit (1).

8. ACK signal recognition from the device

9. The device transfers the read data from the designated address

10. Host transfers ACK signal

11. The (9) & (10) routines above are repeated if needed, and the read address is autoïincremented

12. Host transfers ACK ¶H· to the device

13. Host transfers the stop condition

Table 17. READ DATA

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

Start

Slave

Memory

Restart

Slave

Address

Read

Data

Read

Data

Stop

Address

R/W ACK Address

ACK

R/W

ACK

1. Host transfers the start condition

2. Host transfers the device slave address with the read mode R/W bit =1

3. ACK signal recognition from the device. (Host then changes to receiver)

4. The device transfers data from the previous access address +1

5. Host transfers ACK signal

6. The (4) & (5) routines above are repeated if needed

7. Host transfers AC.ꢄ¶+·

8. Host transfers the stop condition

Table 18. Read Data w/o Designated Address

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

Stop

Start

Slave

Address

R/W

ACK

Read

Data

ACK

Read

Data

ACK

DP7140

PACKAGE DIMENSIONS

MSOP 8, 3x3

SYMBOL

MIN

NOM

MAX

1.10

0.15

0.95

0.38

0.23

3.10

5.00

3.10

0.05

0.75

0.22

0.13

2.90

4.80

2.90

0.10

0.85

3.00

4.90

3.00

0.65 BSC

0.60

0.40

0.80

0.95 REF

0.25 BSC

0º

6º

TOP VIEW

DETAIL A

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-187.

DETAIL A

NIDEC COPAL ELECTRONICS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

NIDEC COPAL ELECTRONICS CORP. product s are not de signe d, int e nde d, or aut horize d for use as compone nt s in syst e ms int e nde d for surgical implant int o t he body, or

ot he r applicat ions int e nde d t o support or sust ain life , or for any ot he r applicat ion in which t he failure of t he NIDEC COPAL ELECTRONICS CORP. product could cre at e a

sit uat ion where personal injury or deat h may occur.

NIDEC COPAL ELECTRONICS CORP. re se rve s t he right t o make change s t o or discont inue any product or se rvice de scribe d he re in wit hout not ice . Product s wit h dat a she e t s

labeled "Advance Informat ion" or "Preliminary" and ot her product s described herein may not be in product ion or offered for sale.

NIDEC COPAL ELECTRONICS CORP. advise s cust ome rs t o obt ain t he curre nt ve rsion of t he re le vant product informat ion be fore placing orde rs. Circuit diagrams illust rat e

t ypical semiconduct or applicat ions and may not be complet e.

NIDEC COPAL ELECTRONICS CORP.

Japan Head Office

Nishi-Shinjuku, Kimuraya Bldg.,

7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023

Phone: +81-3-3364-7055

Fax: +81-3-3364-7098

www.nidec-copal-electronics.com

DP7140 [NIDEC]

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