DP7241 [NIDEC]
Quad Digital Potentiometer;
| 型号： | DP7241 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | Quad Digital Potentiometer |
| 文件： | 总16页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7241
Quad Digital Potentiometer (DP) with
64 Taps and 2-wire Interface
FEATURES
DESCRIPTION
Four linear-taper digital potentiometers
64 resistor taps per potentiometer
The DP7241 is four Digital Potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of 63 resistive elements connected between
two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
serial bus (I2C-like). On power-up, the contents of the
first data register (DR0) for each of the four
potentiometers is automatically loaded into its
respective wiper control register (WCR).
End to end resistance 2.5k, 10k, 50k or
100k
Potentiometer control and memory access via
2-wire interface (I2C like)
Low wiper resistance, typically 80W
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
20-lead SOIC and TSSOP packages
Industrial temperature range
The DP7241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
For Ordering Information details, see page 15.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC 20 Lead (W)
TSSOP 20 Lead (Y)
R
R
H1
R
H2
R
H3
H0
RW0
RL0
1
2
3
4
5
6
7
8
9
20 VCC
19 RW3
18 RL3
17 RH3
16 A1
15 A3
14 SCL
13 RW2
12 RL2
11 RH2
SCL
SDA
WIPER
CONTROL
REGISTERS
2-WIRE BUS
INTERFACE
R
W0
RH0
A0
R
W1
R
W2
R
W3
A2
CAT
5241
RW1
RL1
A0
A1
A2
NONVOLATILE
DATA
REGISTERS
CONTROL
LOGIC
RH1
SDA
A3
R
R
L1
R
L2
R
L3
L0
GND 10
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2011 Rev. P
DP7241
PIN DESCRIPTION
Pin (SOIC)
Name Function
1
2
RW0
RL0
RH0
A0
Wiper Terminal for Potentiometer 0
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Device Address, LSB
3
4
5
A2
Device Address
6
RW1
RL1
RH1
SDA
Wiper Terminal for Potentiometer 1
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Serial Data Input/Output
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND Ground
RH2
RL2
RW2
SCL
A3
High Reference Terminal for Potentiometer 2
Low Reference Terminal for Potentiometer 2
Wiper Terminal for Potentiometer 2
Bus Serial Clock
Device Address
A1
Device Address
RH3
RL3
RW3
VCC
High Reference Terminal for Potentiometer 3
Low Reference Terminal for Potentiometer 3
Wiper Terminal for Potentiometer 3
Supply Voltage
PIN DESCRIPTION
DEVICE OPERATION
SCL: Serial Clock
The DP7241 is four resistor arrays integrated with 2-
wire serial interface logic, four 6-bit wiper control
registers and sixteen 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL). RH and RL
are symmetrical and may be interchanged. The tap
positions between and at the ends of the series resis–
tors are connected to the output wiper terminals (RW) by
a CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
The DP7241 serial clock input pin is used to clock
all data transfers into or out of the device.
SDA: Serial Data
The DP7241 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin
is an open drain output and can be wire-or'd with the
other open drain or open collector outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A match
in the slave address must be made with the address
input in order to initiate communication with the
DP7241.
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
RW: Wiper
The four RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
Doc. No. MD-2011 Rev. P
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© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7241
ABSOLUTE MAXIMUM RATINGS(1)
Parameter
Ratings
-55 to +125
-65 to +150
-2.0 to +VCC +2.0
-2.0 to +7.0
1.0
Units
°C
°C
V
Temperature Under Bias
Storage Temperature
(2)(3)
Voltage on any Pin with Respect to VSS
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10s)
Wiper Current
W
300
°C
mA
12
RECOMMENDED OPERATING CONDITIONS
Vcc = +2.5V to +6V
Parameter
Ratings
Units
Operating Ambient Temperature (Industrial)
-40 to +85
°C
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter Test Conditions
Min
Typ
100
50
Max
Units
k
k
k
k
%
RPOT
RPOT
RPOT
RPOT
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-25)
Potentiometer Resistance Tolerance
RPOT Matching
10
2.5
20
1
%
Power Rating
25°C, each pot
50
mW
mA
IW
Wiper Current
6
RW
RW
Wiper Resistance
IW = 3mA @ VCC =3V
IW = 3mA @ VCC = 5V
VSS = 0V
300
150
VCC
Wiper Resistance
80
VTERM Voltage on any RH or RL Pin
GND
VN
Noise
(4)
TBD
1.6
nV/¥Hz
%
Resolution
Absolute Linearity (5)
Relative Linearity (6)
RW(n)(actual) - R(n)(expected)
1
LSB(7)
LSB(7)
ppm/°C
ppm/°C
pF
(8)
(8)
RW(n+1) - [RW(n)+LSB
]
0.2
TCRPOT Temperature Coefficient of RPOT
TCRATIO Ratiometric Temp. Coefficient
CH/CL/CW Potentiometer Capacitances
(4)
(4)
(4)
300
20
10/10/25
0.4
(4)
fc
Frequency Response
RPOT = 50k
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(7) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(8) n = 0, 1, 2, ..., 63
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
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Doc. No. MD-2011 Rev. P
DP7241
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
ICC Power Supply Current
Test Conditions
Min
Typ
Max
Units
fSCL = 400kHz
1
mA
VIN = GND or VCC;
ISB
Standby Current (VCC = 5.0V)
1
µA
SDA = GND; RWX = GND (2)
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
10
10
µA
µA
V
ILO
VIL
VIH
VOUT = GND to VCC
-1
VCC x 0.3
VCC + 1.0
0.4
Input High Voltage
VCC x 0.7
V
VOL1 Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
V
CAPACITANCE
TA = 25°C, f = 1.0MHz, VCC = 5V
Symbol Parameter
Test Conditions
Min
Typ
Max
8
Units
pF
(1)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL)
VI/O = 0V
(1)
CIN
VIN = 0V
6
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
Typ
Max Units
fSCL
TI(1)
tAA
Clock Frequency
400
50
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
0.9
(1)
tBUF
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
1.2
0.6
1.2
0.6
0.6
0
tHD:STA
tLOW
Clock Low Period
tHIGH
Clock High Period
tSU:STA
tHD:DAT
tSU:DAT
Start Condition Setup Time (For a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
100
(1)
tR
SDA and SCL Rise Time
0.3
(1)
tF
SDA and SCL Fall Time
300
tSU:STO
tDH
Stop Condition Setup Time
Data Out Hold Time
0.6
50
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
Typ
Max Units
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) All four wiper terminals RW0, RW1, RW2, and RW3 are tied to ground.
Doc. No. MD-2011 Rev. P
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© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7241
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the
device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
Volts
(1)(2)
ILTH
100
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Figure 1. Bus Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
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Doc. No. MD-2011 Rev. P
DP7241
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 0101 for the DP7241 (see Figure 5). The
next four significant bits (A3, A2, A1, A0) are the
device address bits and define which device the
Master is accessing. Up to sixteen devices may be
individually addressed by the system. Typically, +5V
and ground are hard-wired to these pins to establish
the device's address.
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
After the Master sends a START condition and the
slave address byte, the DP7241 monitors the bus
and responds with an acknowledge (on the SDA line)
when its address matches the transmitted slave
address.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
DP7241 will be considered a slave device in all
applications.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The DP7241 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The DP7241 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
When the DP7241 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the DP7241 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Doc. No. MD-2011 Rev. P
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© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7241
Acknowledge Polling
WRITE OPERATION
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the DP7241 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the DP7241 is still
busy with the write operation, no ACK will be returned.
If the DP7241 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of DP7241. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The DP7241
acknowledges once more and the Master generates
the STOP condition, at which time if a non-volatile
data register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
Figure 5. Slave Address Bits
DP7241
0
1
0
1
A3 A2 A1 A0
*
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
S
SLAVE/DP
ADDRESS
INSTRUCTION
BYTE
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
Pot/WCR Data Register
DR WCR DATA
Fixed
Variable
op code
Address
Address
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
7
Doc. No. MD-2011 Rev. P
DP7241
INSTRUCTIONS AND REGISTER
DESCRIPTION
INSTRUCTION BYTE
The next byte sent to the DP7241 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The P1 and P0 bits point to one of four
Wiper Control Registers. The least two significant bits,
R1 and R0, point to one of the four data registers of
each associated potentiometer. The format is shown
in Table 2.
SLAVE ADDRESS BYTE
The first byte sent to the DP7241 from the
master/processor is called the Slave/DP Address
Byte. The most significant four bits of the slave
address are a device type identifier. These bits for the
DP7241 are fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the DP7241 to successfully continue the com-
mand sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3 - A0 inputs
can be actively driven by CMOS input signals or tied
to VCC or VSS.
Data Register Selection
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
0
1
1
0
1
1
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
A3
A2
A1
A0
1
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
P1
P0
R1
R0
(MSB)
(LSB)
Doc. No. MD-2011 Rev. P
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© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7241
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Regis–
ters is a non-volatile operation and will take a
maximum of 5ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The DP7241 contains four 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as standard memory locations for system
parameters or user preference data.
INSTRUCTIONS
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in
the WCR
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
The Wiper Control Register is a volatile register that
loses its contents when the DP7241 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Read Data Register – read the contents of the
selected Data Register
Data Registers (DR)
— Write Data Register – write a new value to the
selected Data Register
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
Table 3. Instruction Set
Instruction Set
WCR1 WCR0
Instruction
Operations
I3 I2 I1 I0
/ P1
/ P0
R1
R0
Read Wiper Control
Register
Read the contents of the Wiper Control
Register pointed to by P1-P0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
1/0
1/0
0
0
Write Wiper Control
Register
Write new value to the Wiper Control
Register pointed to by P1-P0
1/0
1/0
1/0
1/0
0
0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Read Data Register
Write Data Register
1/0 1/0 1/0
1/0 1/0 1/0
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
Transfer the contents of the Data Register
1/0 1/0 1/0 pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
XFR Data Register to
Wiper Control Register
1
1
0
1
1
0
0
1
0
1
0
1
1/0
1/0
0
Transfer the contents of the Wiper Control
1/0 1/0 1/0 Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
XFR Wiper Control
Register to Data Register
Transfer the contents of the Data Registers
1/0 1/0 pointed to by R1-R0 of all four pots to their
respective Wiper Control Registers
Global XFR Data Registers
to Wiper Control Registers
0
Transfer the contents of both Wiper Control
1/0 1/0 Registers to their respective data Registers
pointed to by R1-R0 of all four pots
Global XFR Wiper Control
Registers to Data Register
1
0
0
0
0
1
0
0
0
0
Increment/Decrement
Wiper Control Register
Note: 1/0 = data is one or zero
Enable Increment/decrement of the
1/0
1/0
0
0
Control Latch pointed to by P1-P0
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
9
Doc. No. MD-2011 Rev. P
DP7241
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to non-
volatile memory and takes a maximum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers; or the transfer can occur between all
potentiometers and one associated register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
DP7241; either between t he host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the DP7241 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the RL terminal.
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA
0
1
0
1
ID3 ID2 ID1 ID0
S
A2 A1 A0
S
T
A
R
T
A3
A I3 I2 I1
P0
I0
P1
R1 R0
A
C
K
C
K
T
O
P
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 8. Three-Byte Instruction Sequence
SDA
0
1
0
1
S
T
A
R
T
I3
ID3 ID2
ID0
A
C
K
I2
I1
I0
R1 R0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
P1 P0
ID1
A3 A2 A1 A0
O
P
Internal
Address
Device ID
WCR[7:0]
or
Instruction
Opcode
Data
Pot/WCR
Address
Register
Address
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
SDA
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0
I3
I2
I0
R1 R0
P1 P0
S
T
A
R
T
A
C
K
A
C
K
I
I
D
E
C
1
S
I
D
E
C
n
N
C
1
N
C
2
T
O
P
N
C
n
Internal
Address
Instruction
Opcode
Data
Pot/WCR
Address
Register
Address
Doc. No. MD-2011 Rev. P
10
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7241
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRID
SCL
SDA
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0
1 0 0 1 P1 P0 0 0
7 6 5 4 3 2 1 0
Write Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0
1 0 1 0 P1 P0 0 0
7 6 5 4 3 2 1 0
Read Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0
1 0 1 1 P1 P0 R1 R0
7 6 5 4 3 2 1 0
Write Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0
1 1 0 0 P1 P0 R1 R0
7 6 5 4 3 2 1 0
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2011 Rev. P
DP7241
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
S
T
A
R
T
A
C
K
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0
0 0 0 1 0 0 R1 R0
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
S
T
A
R
T
A
C
K
A
C
K
S
T
O
P
0 1 0 1 A3 A2 A1 A0
1 0 0 0 0 0 R1 R0
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
S
T
A
R
T
A
C
K
A
C
K O
P
S
T
0 1 0 1 A3 A2 A1 A0
1 1 1 0 P1 P0 R1 R0
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
S
T
A
R
T
A
C
K
A
C
K O
P
S
T
0 1 0 1 A3 A2 A1 A0
1 1 0 1 P1 P0 R1 R0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
. . .
S
T
A
R
T
A
C
K
A
C
K
A
C
K O
P
S
T
0 1 0 1 A3 A2 A1 A0
0 0 1 0 P1 P0 0 0
I/D I/D
I/D I/D
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Doc. No. MD-2011 Rev. P
12
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7241
PACKAGE OUTLINE DRAWINGS
SOIC 20-Lead 300 mils (W) (1)(2)
SYMBOL
MIN
2.36
0.10
2.05
0.31
0.20
12.60
10.01
7.40
NOM
MAX
A
A1
A2
b
2.49
2.64
0.30
2.55
0.51
0.33
13.00
10.64
7.60
0.41
0.27
c
E1
E
D
12.80
10.30
7.50
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.75
1.27
8°
L
0.81
b
e
Q
Q1
5°
15°
PIN#1 IDENTIFICATION
TOP VIEW
D
h
h
Q1
A2
Q
A
Q1
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degree.
(2) Complies with JEDEC standard MS-013.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
13
Doc. No. MD-2011 Rev. P
DP7241
TSSOP 20-Lead 4.4mm (Y) (1)(2)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
6.60
6.50
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
6.40
6.30
4.30
c
E1
E
D
6.50
6.40
E
E1
e
4.40
0.65 BSC
0.60
L
0.45
0°
0.75
8°
L1
Q1
1.00 REF
e
TOP VIEW
D
c
A2
A
Q1
L
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degree.
(2) Complies with JEDEC standard M0-153.
Doc. No. MD-2011 Rev. P
14
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7241
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
DP
7241
W
I
-10
T1
Optional
Company ID
Temperature Range
I = Industrial (-40ºC to 85ºC)
Resistance
-25: 2.5k
-10: 10k
-50: 50k
-00: 100k
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
Product
Number
7241
Package
W: SOIC
Y: TSSOP
ORDERING PART NUMBER
Part Number
DP7241WI-25
DP7241WI-10
DP7241WI-50
DP7241WI-00
DP7241YI-25
DP7241YI-10
DP7241YI-50
DP7241YI-00
Resistance
Package
2.5k
10k
50k
100k
2.5k
10k
50k
100k
SOIC
TSSOP
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) This device used in the above example is a DP7241WI-10-T1 (SOIC, Industrial Temperature, 10k, Tape & Reel, 1,000/Reel).
(3) For additional package and temperature options, please contact your nearest COPAL ELECTRONICS Sales office.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
15
Doc. No. MD-2011 Rev. P
REVISION HISTORY
Date
Revision Description
09/30/2003
03/03/2004
G
H
Deleted WP from Functional Diagram, pg. 1
Added TSSOP package in all areas
Eliminated data sheet designation
03/29/2004
I
Eliminated Commercial temperature range in all areas
Updated Absolute Max Ratings and Potentiometer Characteristics notes
04/05/2004
04/22/2006
J
Corrected Potentiometer Resistance [Changed (-2.5) to (-25)] in table
Updated Example of Ordering Information
K
Updated 20-Lead TSSOP Package Drawing
Updated Example of Ordering Information
Update Copyrights, Trademarks and Patents
Added MD- in front of Document No.
05/24/2007
L
Update Pin Description
Update D.C Operating Characteristics: Standby Current Test Conditions
06/20/2007
02/04/2008
M
N
Update Package Outline Drawings
Change 2-wire with I²C
04/08/2008
08/25/2008
O
P
Update Example of Ordering Information
Update Ordering Part Number table
Update Figures 7, 8 and 9
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RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
NIDEC COPAL ELECTRONICS CORP. product s are not de signe d, int e nde d, or aut horize d for use as compone nt s in syst e ms int e nde d for surgical implant int o t he body, or
ot he r applicat ions int e nde d t o support or sust ain life , or for any ot he r applicat ion in which t he failure of t he NIDEC COPAL ELECTRONICS CORP. product could cre at e a
sit uat ion where personal injury or deat h may occur.
NIDEC COPAL ELECTRONICS CORP. re se rve s t he right t o make change s t o or discont inue any product or se rvice de scribe d he re in wit hout not ice . Product s wit h dat a she e t s
labeled "Advance Informat ion" or "Preliminary" and ot her product s described herein may not be in product ion or offered for sale.
NIDEC COPAL ELECTRONICS CORP. advise s cust ome rs t o obt ain t he curre nt ve rsion of t he re le vant product informat ion be fore placing orde rs. Circuit diagrams illust rat e
t ypical semiconduct or applicat ions and may not be complet e.
NIDEC COPAL ELECTRONICS CORP.
Japan Head Office
Nishi-Shinjuku, Kimuraya Bldg.,
7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023
Phone: +81-3-3364-7055
Fax: +81-3-3364-7098
Document No: MD-2011
Revision:
P
www.nidec-copal-electronics.com
Issue date:
08/25/08
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