NJU#3713AV-TE2 [NJRC]
Converter;
| 型号： | NJU#3713AV-TE2 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Converter |
| 文件： | 总8页 (文件大小：47K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU3713A
12-BIT SERIAL TO PARALLEL CONVERTER
ꢀGENERAL DESCRIPTION
ꢀPACKAGE OUTLINE
The NJU3713A is a 12-bit serial to parallel converter
especially applying to MPU outport expander. It can
operate from 2.4V to 5.5V.
The effective outport assignment of MPU is available
as the connection between NJU3713A and MPU using
only 4 lines.
The serial data synchronizing with 5MHz or more
clock can be input to the serial data input terminal and
the data are output from parallel output buffer through
serial in parallel out shift register and parallel data
latches.
NJU3713AV
The hysteresis input circuit realizes wide noise
margin and the high drive-ability output buffer (25mA)
can drive LED directly.
ꢀ
PIN CONFIGURATION
ꢀFEATURES
ꢁ12-Bit Serial In Parallel Out
VDD
P4
P3
P2
P1
NC
CLR
STB
CLK
DATA
1
2
20
19
18
17
16
15
14
13
12
11
P5
P6
P7
P8
VSS
NC
P9
P10
P11
P12
ꢁHysteresis Input
ꢁOperating Voltage
0.5V typ at 5V
2.4 to 5.5V
ꢁMaximum Operating Frequency 5MHz
3
4
5
6
ꢁOutput Current
25mA at 5V, 5mA at 3V
SSOP20
7
ꢁC-MOS Technology
ꢁPackage Outline
8
9
10
NJU3713AV
ꢀBLOCK DIAGRAM
P1
P2
P3
DATA
CLK
P11
P12
STB
CLR
Controller Circuit
Ver.2008-02-22
- 1 -
NJU3713A
ꢀTERMINAL DESCRIPTION
No.
1
2
3
4
SYMBOL
P5
I/O
O
O
O
O
-
FUNCTION
P6
P7
P8
VSS
NC
Parallel Conversion Data Output Terminals
5
6
GND
Non Connection
-
7
8
9
P9
O
O
O
O
I
I
I
I
-
O
O
O
O
-
P10
P11
P12
DATA
CLK
STB
CLR
NC
P1
P2
P3
P4
Parallel Conversion Data Output Terminals
10
11
12
13
14
15
16
17
18
19
20
Serial Data Input Terminal
Clock Signal Input Terminal
Strobe Signal Input Terminal
Clear Signal Input Terminal
Non Connection
Parallel Conversion Data Output Terminals
Power Supply Terminal (2.4 to 5.5V)
VDD
Ver.2008-02-22
- 2 -
NJU3713A
ꢀFUNCTIONAL DESCRIPTION
(1) Reset
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
output are "L" level.
Normally, the CLR terminal should be "H" level.
(2) Data Transmission
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
latches.
Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore,
the clock signal should be controlled for data order.
Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure
to protect the noise.
CLR
L
STB
X
CLK
X
OPERATION
All of latches are reset (the data in the shift register is no change).
All of parallel conversion outputs are "L".
The serial data into the DATA terminal are inputted to the shift register.
In this stage, the data in the latch is not changed.
H
H
L
H
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
L
H
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift register.
Note 1) X: Don’t care
Ver.2008-02-22
- 3 -
NJU3713A
ꢀTIMING CHART
CLK
CLR
STB
DATA
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
Ver.2008-02-22
- 4 -
NJU3713A
ꢀABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Output Current
SYMBOL
RATINGS
-0.5 ~ +7.0
UNIT
V
VDD
VI
VSS-0.5 ~ VDD+0.5
VSS-0.5 ~ VDD+0.5
±25
V
VO
IO
V
mA
Output Short Current
(P1~P12 Terminals)
VO=7V, VI=0V
VO=0V, VI=7V
20 (max)
-20 (max)
IOSD
mA
(Note 5)
Power Dissipation
PD
570 (SSOP)
mW
(Note 6)
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
-25 ~ +85
-65 ~+150
°C
°C
Note 2) All voltage are relative to VSS=0V reference.
Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also
recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause
malfunctions and impact on the reliability.
Note 4) To stabilize the IC operation, place decoupling capacitor between VDD and VSS
Note 5) VDD=7V, VSS=0V, less than 1 second per pin.
Note 6) Mounted on a PCB.
.
ꢀDC ELECTRICAL CHARACTERISTICS
(VDD=2.4~5.5V, VSS=0V, Ta=25°C, unless otherwise noted)
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Operating Voltage
VDD
2.4
-
5.5
V
Operating Current
High-level Input Voltage
Low-level Input Voltage
Input Leakage Current
IDDS
VIH
VIL
ILI
VIH=VDD, VIL=VSS
-
-
-
-
0.1
VDD
mA
V
0.7VDD
VSS
0.3VDD
V
VI=0~
VDD
-10
VDD-1.5
VDD-1.0
VDD-0.5
VDD-0.5
VSS
-
-
-
-
-
-
-
-
-
10
VDD
VDD
VDD
VDD
1.5
0.8
0.4
0.5
µA
IOH=-25mA
IOH=-15mA
IOH=-10mA
VDD=5V
P1~P12
Terminals
High-level Output Voltage
(Note 7)
VOHD
V
V
VDD=3V IOH=-5mA
IOL=+25mA
VDD=5V
IOL=+15mA
IOL=+10mA
VSS
P1~P12
Terminals
Low-level Output Voltage
(Note 7)
VOLD
VSS
VDD=3V IOL=+5mA
VSS
Note 7) Specified value represent output current per pin. When use, total current consideration and less than power dissipation in rating
operation should be required.
Ver.2008-02-22
- 5 -
NJU3713A
ꢀSWITCHING CHARACTERISTICS
(VDD=2.4~5.5V, VSS=0V, Ta=25°C, unless otherwise noted)
PARAMETER
Set-Up Time
SYMBOL
tSD
CONDITION
MIN
TYP
MAX
UNIT
DATA-CLK
20
-
-
ns
Hold Time
Set-Up Time
Hold Time
tHD
CLK-DATA
STB-CLK
20
30
30
-
-
-
-
-
-
-
-
-
-
ns
ns
tSSTB
CLK-STB
tHSTB
-
ns
tpd PCK
tpd PSTB
tpd PCLR
fMAX
CLK-P1~P12
STB-P1~P12
CLR-P1~P12
100
80
80
-
ns
Output Delay Time
-
ns
-
ns
Maximum Operating Frequency
Note 8) COUT=50pF
5
MHz
Ver.2008-02-22
- 6 -
NJU3713A
ꢀSWITCHING CHARACTERISTICS TEST WAVEFORM
fMAX
CLK
tSD
DATA
tHD
STB
tSSTB
tHSTB
CLK
STB
tpd PCK
L
P1~P12
CLK
H
STB
tpd PSTB
P1~P12
CLR
DATA
tpd PCLR
H
P1~P12
Ver.2008-02-22
- 7 -
NJU3713A
ꢀAPPLICATION CIRCUIT
P1
P3
P5
P7
P9
P11
MPU
P2
P4
P6
P8
P10
P12
DATA
CLK
STB
CLR
NJU3713A
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2008-02-22
- 8 -
相关型号：
©2020 ICPDF网 联系我们和版权申明