NJU3426 [NJRC]
16-SEGMENT X 15-Digit VFD CONTROLLER / DRIVER; 16段×15位数字VFD控制器/驱动器
| 型号： | NJU3426 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | 16-SEGMENT X 15-Digit VFD CONTROLLER / DRIVER |
| 文件： | 总12页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU3426
PRELIMINARY
16-SEGMENT X 15-Digit
VFD CONTROLLER / DRIVER
ꢀ GENERAL DESCRIPTION
ꢀ PACKAGE OUTLINE
The NJU3426 is a VFD (Vacuum Fluorescent Display)
controller/driver to dynamically drive up to 16 segments x 15
digits. It consists of display data RAM, an address counter,
command registers, a serial interface and high voltage drivers.
The direct control from the MPU and high voltage drivers of
45V make the NJU3426 well suited for various VFD displays.
NJU3426FP1
ꢀ FEATURES
ꢁ
ꢁ
ꢁ
ꢁ
Directly Drives 16-segment x 15-digit
High VFD Driving Voltage
: |VDD-VFDP|=45V
Display Shift Function
Programmable Duty Ratio for Timing Signal
:2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16 duty
Display ON/OFF Control Function
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Display Data RAM
: 30 x 8-bit
Built-in Oscillator (Formed by Connecting an External Ceramic Resonator)
8-bit Serial Interface
Power-ON Reset Function
Operating Voltage
C-MOS Technology
Package Outline
:3.0 to 5.5V
:QFP48-P1
ꢀ BLOCK DIAGRAM
S0 to S15
T0 to T13
VDD
High Voltage Driver
Segment Data Latch
High Voltage Driver
Timing Counter
VSS
VFDP
Duty
Counter
Display RAM
30 x8-bit
Timing
Counter
XT
OSC
XTb
Instruction Decoder
SI
SCK
RSTb
REST
Serial Buffer
CSb
02/08/29
- 1 -
NJU3426
ꢀ
FUNCTION DESCRIPTION
(1) ADDRESS COUNTER
The address counter indicates the “Display data RAM address”, in which the display data will be transferred and stored.
For the data transmission, once an initial RAM address is determined, the display data can be continuously transmitted
without setting the RAM address each time. When the upper 2 bits (B7 and B6) of the 1st word are “0,0”, the lower 5
bits (B4 to B0) are recognized as RAM address data. And, the 2nd word is recognized as display data, which will be
stored in the RAM address designated by the 1st word, and simultaneously the RAM address is counted up by an
auto-increment operation.
The “Display data RAM address”, which can be specified by the 1st word, ranges from “0,0,0,0,0” (00H) to “1,1,1,0,1”
(1DH). However, the auto-increment keeps counting up to “1,1,1,1,1” (1FH) every display data transmission because of
the 5-bit address counter, and finally the RAM address wraps to “0,0,0,0,0” (00H) and begins counting up. Note that the
display data, stored in the RAM address of “1,1,1,1,0” (1EH) and “1,1,1,1,1” (1FH), is ignored in this sequence.
DISPLAY DATA RAM ADDRESS
B7
0
B6
0
B5
*
B4
B3
B2
B1
B0
AD4 AD3 AD2 AD1 AD0
Recognition data
Display data RAM address
*:don’t care
RAM
Address
Character
B7 B6
address
RAM
B4 B3
B1 B0
B7 B6
B4 B3 B2 B1 B0
B5
B2
B5
Address
01H
03H
05H
07H
09H
0BH
0DH
0FH
11H
13H
15H
17H
19H
1BH
1DH
1FH
C0
C1
C2
C3
C4
C5
C6
C7
C8
00H
02H
04H
06H
08H
0AH
0CH
0EH
10H
12H
14H
16H
18H
1AH
1CH
1EH
T0
T1
T2
T3
T4
T5
T6
T7
T8
C9
T9
C10
C11
C12
C13
C14
T10
T11
T12
T13
S15 S14 S13 S12 S11 S10 S9 S8
S7 S6 S5 S4 S3 S2 S1 S0
: These display data is ignored.
DISPLAY DATA RAM MAPPING
- 2 -
NJU3426
(2) COMMAND REGISTER 1
The “Command register 1” is used for setting “Duty ratio for timing signal”, “Display control ON/OFF” and “Shifting
display digits”. When the upper 1 bit (B7) of the 1st word is “1”, the lower 7 bits (B6 to B0) are recognized as
command data, and stored in the “Command register 1”. Note that changing the “Duty ratio” or “Shifting display
digits” must be executed under the “Display control OFF”, otherwise it may cause flickering. The contents of the
“Command register 1” is initially set up at power-ON reset or reset signal, as shown below.
DEFAULT VALUES OF COMMAND REGISTER 1
• Duty ratio for timing signal
• Display control ON/OFF
• Shifting display digits
: 2/16
: OFF
: 7
B7
1
B6
B5
B4
B3
B2
B1
B0
DT2 DT1 DT0 DSP DE2 DE1 DE0
Recognition data
Duty ratio for Display control
timing signal ON / OFF
Shifting display digits
MD2
MD1
MD0 Duty ratio for timing signal
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2/16
4/16
6/16
8/16
10/16
12/16
14/16
15/16
DSP
Display control
0
1
OFF
ON
Note.)
When the “Display control is OFF” is set, all output pins become in display OFF state.
DE2
0
DE1
0
DE0
0
Shifting display digits
7
0
0
1
8
0
1
0
9
0
1
1
1
1
0
0
1
1
0
1
0
10
11
12
13
14
1
1
1
- 3 -
NJU3426
(3) COMMAND REGISTER 2
The “Command register 2” is used for setting the “Initial character address” , which corresponds to the T0 pin. When the
upper 2 bits (B7 and B6) of the 1st word is “0,1”, the lower 4 bits (B3 to B0) are recognized as command data, and stored
in the “Command register 2”. The contents of the “Command register 2” is initially set up at power-ON reset or reset
signal, as shown below.
DEFAULT VALUES OF COMMAND REGISTER 2
• Initial character address : C1 (0,0,0,1)
B7
0
B6
1
B5
*
B4
*
B3
B2
B1
B0
DS3 DS2 DS1 DS0
Recognition data
Initial character address
*:don’t care
DS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DS2
DS1
DS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Initial character address
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
Prohibited
- 4 -
NJU3426
(4) DISPLAY SHIFT OPERATION
The display shift operation can be performed by changing the “Initial character address” of the “Command register 2”.
And, the number of digits for the display shift in the loop is determined by the “Shifting display digits” of the
“Command register 1”. In other words, shifting display area ranges from the “Initial character address” specified by the
“Command register 2” to the last address designated by the “Command register 1”.
The default value of the “Initial character address” is C1 (0,0,0,1), as shown in the table of “Display data RAM”. In
addition, supposing that the value of the “Shifting display digits” is “N”, the “Initial character address” must be set in the
range between C0 and CN in order not to exceed the digit “N”. Because the display shift operation doesn’t apply to the
addresses beyond the range of the digit “N”, the display images, initially set, appear on these addresses. Just for
reference, one character of display image is composed of 16 segments.
HOW TO SET LEFT DISPLAY SHIFT
The left display shift is carried out by incrementing the “Initial character address” gradually like C2, C3, C4, ---
CN. To the contrary, decrementing the address performs right display shift. The following description
provides the example on how to set the left display shift, using alphanumeric display images such as “0”, “1”,
“2”, ---, “9”, “A”, “B”, ---, and “E”.
STEP1) Setting display images in the display data RAM
•
Display RAM data
Character address
Display image
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
SETP2) Setting the
“Initial character address
”
to C2 and the “Shifting display digits N” to 12 (T11).
Shifting display digits
C0
Character
address
C1
C2
C3
C12
C13
C14
Timing output
terminals
T0
1
T1
2
T10
11
T11
12
T12
13
T13
14
Character
Display image
is not shifted.
In this setting, the display images of "2", "3”,- - - appear on the T0, T1, T2, - - - T10 pins respectively, and the
image “0” is on the T11 pin, which is assigned to the 12th character address. The display images “D” and “E”
don’t shift but remain on the T12 and T13 pins, assigned to the 13th and 14th characters respectively, because their
character addresses are outside of the digit “N”.
STEP3) Changing the
“
Initial character address
”
to C3, and leaving the
“Shifting display digits N” as 12 (T11).
Shifting display digits
Character
address
C2
C3
C4
C0
C1
C13
C14
Timing output
terminals
T0
1
T1
2
T10
11
T11
12
T12
13
T13
14
Character
Display image
is not shifted.
- 5 -
NJU3426
ꢀ TIMING SIGNAL / DUTY-CHANGE WAVEFORM
Display timing
13 14 15 0 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 0 1
2
3
4
5 6
(Duty count)
ST2 ST1 ST0
2/16
4/16
6/16
0
0
0
0
0
1
0
1
0
8/16
0
1
1
0
1
0
Timing signal
(T0 to T14)
10/16
12/16
14/16
15/16
1
1
1
0
1
1
1
0
1
Segment signal
ꢀ DISPLAY TIMING CHART
fXT
XT
tBK
tDG
T0
T1
T2
•
•
•
•
•
•
•
•
T13
tSP
S0 to S15
Oscillation frequency
: fXT
:800kHz to 3.5MHz
Minimum blanking time : tBK=(1/fXT) x 16 x 2
(duty15/16)
:40µs to 9.2µs
1-character display time : tDG=tBK x 16
:640µs to 147.2µs
1-cycle display time
: tSP=tDG x 14
:20.608ms to 8.96ms
- 6 -
NJU3426
(5) SERIAL DATA TRANSMISSION
Communication between the NJU3426 and MPU uses the serial data transmission with synchronous clock, and 8 bits
serial data constitutes 1 word. Each bit on the SI pin is fetched at the rising edge of the serial clock (SCK), and the
entire 8 bits are loaded as 1 word at the rising edge of the chip select (CSb).
During one communication, multiple words can be transferred continuously. The 1st word must be either “Display data
RAM address”, “Command register 1” or “Command register 2”. When the 1st word is RAM address data, the 2nd and
ascending words must be display data. When it’s the “Command register 1 or 2”, the 2nd and ascending words are
ignored.
SCK
SI
D0
D1
D2
D3
D4
D5
D6
D7
SERIAL DATA TIMING
CSb
SCK
SI
WORD n
WORD
1
WORD
2
SERIAL DATA TRANSMISSION FORMAT
•
Serial input data
DATA FORMAT FOR THE 1ST WORD
DISPLAY DATA RAM ADRESS
B7
0
B6
0
B5
*
B4
AD4
B3
AD3
B2
AD2
B1
AD1
B0
AD0
*:don’t care
*:don’t care
*:don’t care
COMMAND DATA 1
B7
1
B6
DT2
B5
DT1
B4
DT0
B3
DSP
B2
DE2
B1
DE1
B0
DE0
COMMAND DATA 2
B7
0
B6
1
B5
*
B4
*
B3
DS3
B2
DS2
B1
DS1
B0
DS0
SERIAL DATA FOR THE 2ND AND ASCENDING WORDS
When the 1st word is the “Display data RAM address”, the 2nd and ascending words must be display data.
When the 1st word is the “Command register 1 or 2”, the 2nd and ascending words are ignored.
- 7 -
NJU3426
ꢀ ABSOLUTE MAXIMAM RATINGS
(VSS=0V, Ta=25°C)
CONDITIONS
PARAMETER
Operation voltage
Input voltage
SYMBOL
VDD
RATINGS
-0.3 to +7.0
-0.3 to VDD+0.3
VDD-45 to VDD+0.3
-15
UNIT
V
V
V
mA
mA
VIN
VFDP
IOH1
VFD driving voltage
Relative to VDD.
1 pin out of S0 to S15 pins
1 pin out of T0 to T13 pins
All output pins
“H” level output current
IOH2
-35
“H” level
-100
20
mA
mA
mA
ΣIOH
IOL
Total output current
“L” level output current
“L” level
All output pins
100
ΣIOL
Total output current
Operating temperature
Storage temperature
Power dissipation
Topr
Tstg
PD
-40 to 85
-55 to 125
T.B.D.
°C
°C
mW QFP
Note 1):
The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, an electrical or physical stress may
cause permanent damage to the LSI.
Note 2):
Note 3):
De-coupling capacitors for VDD and VSS and VFDP and VSS must be connected for stabble operation.
The following voltage relation must be maintained; VDD> VSS≥ VFDP, VSS=0.
- 8 -
NJU3426
ꢀ ELECTRICAL CHARACTERISTICS
•
DC characteristics 1
(VDD=5.0V, VSS=0V, Ta=-40 to 85°C)
PARAMETER
Operating voltage
SYMBOL
VDD
CONDITIONS
VDD terminal
MIN
4.5
TYP
MAX
5.5
UNIT
V
XT, RSTb, CSb, SCK, SI terminals
“H” level input voltage
“L” level input voltage
VIH
VIL
0.8VDD
V
0.2VDD
CSb, SCK, SI terminals
Input off leak current
IIZ
±1
µA
mA
mA
kΩ
kΩ
V
DD=5.5V, VI=0 or 5.5V
SO to S15
terminals
TO to T13
terminals
VDD=4.5V,
FDP=VDD-40V,
VOH=VDD-2.5V
-7
-15
140
70
V
Display output current
IOH
RSTb terminal, Ta=25°C
VDD=5.0V, VI=VSS
S0 to S15, T0 to T13 terminals, Ta=25°C
VDD=5.0V, VI=VSS, VFDP=VDD-40V
Pull-Up resistance
RUR
200
120
260
200
Pull-down resistance
RDST
V
V
FDP terminal
DD=5.0V, VFDP=VDD-40V,
Display operating
current
IDD
10
15
mA
Ceramic resonator:1MHz,
All Segment/Timing output ON
•
DC characteristics 1
PARAMETER
(VDD=5.0V, VSS=0V, Ta=-40 to 85°C)
SYMBOL
CONDITIONS
Fig. 1
MIN
TYP
MAX
UNIT
Operating oscillation frequency,
External clock Input
fXT,
fCL
0.8
3.5
MHZ
External clock Input
Rise time, Fall time
tCLH, tCLL
Fig. 1
20
ns
Serial input data setup time
Serial input data hold time
Serial clock frequency
Serial clock interval time
Reset palse width
tSIS
tSIH
fSCK
tSCI
tRSTb
tR
Fig. 2
Fig. 2
Fig. 3
Fig. 3
Fig. 4
Fig. 5
60
10
ns
ns
MHZ
1.5
10
10
10
0.05
µs
µs
ms
Power rise time
- 9 -
NJU3426
•
DC characteristics 2
(VDD=3.3V, VSS=0V, Ta=-40 to 85°C)
PARAMETER
Operating voltage
SYMBOL
VDD
CONDITIONS
VDD terminal
MIN
3.0
TYP
MAX
3.6
UNIT
V
XT, RSTb, CSb, SCK, SI terminals
“H” level input voltage
“L” level input voltage
VIH
VIL
0.8VDD
V
0.2VDD
CSb, SCK, SI terminals
Input off leak current
IIZ
±1
µA
mA
mA
kΩ
kΩ
V
DD=3.6V, VI=0 or 3.6V
S0 to S15
terminals
T0 to T13
terminals
V
V
V
DD=3.0V,
FDP=VDD-40V,
OH=VDD-1.5V
-2.2
-5.5
140
70
Display output current
IOH
RSTb terminal, Ta=25°C
VDD=3.0V, VI=VSS
S0 to S15, T0 to T13 terminals, Ta=25°C
VDD=3.0V, VI=VSS, VFDP=VDD-40V
Pull-Up resistance
RUR
200
120
260
200
Pull-down resistance
RDST
V
V
FDP terminal
DD=3.3V, VFDP=VDD-40V,
Display operating
current
IDD
10
15
mA
Ceramic resonator:1MHz,
All Segment/Timing output ON
•
AC characteristics 2
PARAMETER
(VDD=3.3V, VSS=0V, Ta=-40 to 85°C)
SYMBOL CONDITIONS
MIN
TYP
MAX
UNIT
Operating oscillation frequency,
External clock Input
fXT,
fCL
Fig. 1
0.8
2
MHZ
External clock Input
Rise time, Fall time
tCLH, tCLL
Fig. 1
20
ns
Serial input data setup time
Serial input data hold time
Serial clock frequency
Serial clock interval time
Reset palse width
tSIS
tSIH
fSCK
tSCI
tRSTb
tR
Fig. 2
Fig. 2
Fig. 3
Fig. 3
Fig. 4
Fig. 5
120
20
ns
ns
MHZ
0.8
5
10
20
0.05
µs
µs
ms
Power rise time
- 10 -
NJU3426
fXT, fCL
VIH
VIH
VIH
XT, XTb
VIL
VIL
tCLH
tCLL
Fig. 1
VIH
SCK
VIL
tSIS
tSIH
VIH
VIL
VIH
VIL
SI
Fig. 2
50%
CSb
50%
SCK
50%
50%
tSCI
50%
tSCI
tSCI
Fig. 3
fSCK
tRSTb
RSTb
VIL
VIL
Fig. 4
tR
90%
VDD
10%
Fig. 5
- 11 -
NJU3426
ꢀ APPLICATION CIRCUIT
VFDP
T3
T2
VFDP
N.C.
RSTb
T1
CSb
T0
MPU
S15
S14
S13
S12
S11
S10
SCK
SI
NJU3426FP1
VSS
XT
C1
C2
XTb
VDD
C0
VDD
VFD
CAUTION]
Thespecifications on thisdatabookareonly
ivenforinformation, withoutanyguarantee
sregardseithermistakesoromissions.The
application circuits in this databook are
escribedonlytoshowrepresentativeusages
of the product and not intended for the
uaranteeorpermissionof anyrightincluding
the industrial rights.
- 12 -
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