NJU6475B_技术文档

NJU6475B

P R E L I M I N A R Y

12-Character 4-Line Dot Matrix Low Power

LCD Controller Driver with key Scan Function

GENERAL DESCRIPTION

PACKAGE OUTLINE

The NJU6475B is a Dot Matrix LCD Controller Driver for

12-character 4-line with Icon display in single chip. It contains

voltage converter, voltage regulator, bleeder resistance, CR

oscillator, instruction decoder, character generator ROM/RAM,

high voltage operation controller/driver and key scan circuit.

The voltage converter generates (about 8V) from the

supply voltage (3V) and regulated by the regulator. The bias

level of LCD driving voltage is generated of high value bleeder

resistance and the buffer amplifier matches the

impedance. 16-step contrast control function is incorporated

for its adjustment. Therefore, simple power supply circuit and

easy contrast adjustment are available. The complete CR

oscillator is incorporated without external components for

oscillation circuit. The microprocessor interface circuit which

operates by 1MHz, can be selected serial interface.

NJU6475B

The character generator ROM consisting of 10,080bits stores

252 kinds of character Font.

Each 160bits CG RAM and Icon display RAM can story

4 kinds of special character to display on the dot matrix

display area or 128 kinds of Icon on the display area.

FEATURES

•12-Character 4-Line Dot Matrix LCD Controller Driver

•Maximum 128-Icon Display

•Serial CPU Interface

•Display Data RAM

- 48 x 8 Bits :Maximum 12-Character 4-Line Display

•Character Generator ROM

•Character Generator RAM

•Icon Display RAM

•High Voltage LCD Driver

•Duty & Bias Ratio

•Useful Instruction Set

- 10,080 Bits:252 Characters (5 x 8 Dots)

- 32 x 5 Bits :4 Patterns (5 x 8 Dots)

- 32 x 5 Bits :Maximum 128-Icon

: 37-Common/63-Segment

: 1/36 duty 1/7Bias

: Clear Display, Return Home, Display On/Off Control

Display Blink,Cursor Shift, Character Shift

•Common and Segment Driver location Order Select Function (Mode-A, Mode-B)

•Power On Reset Circuit On Chip

•Hardware Reset

•Voltage Regulator On Chip

•Electrical Variable Resistance On Chip

•32-key scan function (8 x 4 Matrix)

•Oscillation circuit On Chip

•Voltage Converter (Doubler,Tripler) On Chip

•Bleeder Resistance On Chip

•Low Oprating Current

•Operating Voltage

•Package Outline

•C-MOS Technology

- 2.4V to 3.6V (Except For LCD Driving Voltage)

- Bumped-Chip / TCP

NJU6475B

PAD LOCATION

NJU6475B

PAD COORDINATES

PAD Name

Chip Size 11.22×2.5mm (Chip Center X=0um,Y=0um)

PAD Name

Mode A Mode B

PAD No.

X=(um)

Y=(um)

PAD No.

X=(um)

Y=(um)

Mode A

ALI-A1

Mode B

ALI-A1

1

-6240

-6020

-5775

-5479

-4979

-4479

-3979

-3479

-2979

-2479

-1979

-1479

- 979

- 531

- 302

- 74

155

-1090

1090

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

NC

SEGS

NC

SEGS

5817

5617

5417

5217

5017

4817

4617

4417

4217

4017

3817

3617

3417

3160

2780

2700

2620

2540

2460

2380

2300

2220

2140

2060

1980

1900

1820

1740

1660

1580

1500

1420

1340

1260

1180

1100

1020

940

1090

1

2

OSC

2

3

OSC

5

4

V

SS

5

V

5OUT

6

7

8

9

V

C2^-

C2⁺

C1^-

C1⁺

C2^-

C2⁺

C1^-

C1⁺

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

DD

V

VR

REG

VR

REG

V

1

TEST

SEL

TEST

SEL

9

COM

RESET

10

11

12

13

14

15

16

25

26

27

28

29

30

31

32

10

11

12

13

14

15

16

25

26

27

28

29

30

31

32

COM

P/S

RS

R/W

E/SCL

P/S

RS

R/W

E/SCL

383

612

840

LCD/KEY LCD/KEY

1069

1298

1536

1773

2010

2247

2484

2721

2958

3195

3466

3632

3903

4068

4244

4352

4460

4568

4676

4784

4892

5000

5217

5417

5617

5817

6017

6217

6017

REQ

DB /CS

7

DB /CS

6

DB /SIO

5

DB

4

DB

3

DB

2

DB

1

DB

0

DB

0

1

2

K

S

K

S

SEGM

1

60

SEG

2

59

SEG

3

58

SEG

0

4

57

SEG

1

5

56

SEG

2

6

55

SEG

3

7

54

SEG

4

8

53

SEG

860

780

700

620

540

460

380

300

220

140

60

20

5

9

52

SEG

6

10

SEG

51

SEG

7

11

SEG

50

SEG

12

SEG

49

SEG

NC

13

SEG

48

SEG

14

SEG

47

SEG

15

SEG

46

SEG

16

SEG

45

SEG

NC

17

44

ALI-A2

ALI-B2

NC

ALI-A2

ALI-B2

NC

SEG

18

43

SEG

19

SEG

42

SEG

1090

-

NJU6475B

PAD Name

Mode A Mode B

PAD No.

X=(um)

Y=(um)

PAD No.

X=(um)

Y=(um)

Mode A

Mode B

20

41

54

7

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

SEG

- 100

- 180

- 260

- 340

- 420

- 500

- 580

- 660

- 740

- 820

- 900

- 980

-1060

-1140

-1220

-1300

-1380

-1460

-1540

-1620

-1700

-1780

-1860

-1940

-2020

-2100

-2180

-2260

-2340

-2420

-2500

-2580

-2660

-2740

1090

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

167

168

169

SEG

-2820

-2900

-2980

-3060

-3140

-3220

-3300

-3380

-3460

-3540

-3620

-3700

-3780

-3860

-3940

-4020

-4100

-4180

-4260

-4340

-4420

-4500

-4580

-4660

-4740

-4820

-4900

-4980

-5085

-5285

-5485

-5885

-6085

-6240

1090

21

SEG

40

SEG

55

56

57

58

59

60

6

5

4

3

2

1

22

SEG

39

SEG

23

SEG

38

SEG

24

SEG

37

SEG

25

SEG

36

SEG

26

SEG

35

SEG

27

SEG

34

SEG

2

1

SEGM

28

SEG

33

SEG

24

COM

29

SEG

32

SEG

23

COM

30

SEG

31

SEG

22

COM

31

SEG

30

SEG

21

COM

32

SEG

29

SEG

20

COM

33

SEG

28

SEG

19

COM

34

SEG

27

SEG

18

COM

35

SEG

26

SEG

17

COM

36

SEG

25

SEG

8

COM

37

SEG

24

SEG

7

COM

38

SEG

23

SEG

6

COM

39

SEG

22

SEG

5

COM

40

SEG

21

SEG

4

COM

41

SEG

20

SEG

3

COM

42

SEG

19

SEG

2

COM

43

SEG

18

SEG

1

COM

44

SEG

17

SEG

4

COMM

COMS

NC

COMM

COMS

NC

45

SEG

16

SEG

3

2

1

3

2

1

46

SEG

15

SEG

47

SEG

14

SEG

48

SEG

13

SEG

1

49

SEG

12

SEG

50

SEG

11

SEG

NC

51

SEG

10

SEG

52

SEG

9

SEG

53

SEG

8

SEG

ALI-B2

NJU6475B

BLOCK DIAGRAM

NJU6475B

TERMINAL DESCRIPTION

PAD No.

11,5

4

Symbol

I/O

-

F u n c t i o n

DD SS

V ,V

DD

SS

Power Source : V =+3V

LCD driving voltage

GND : V =0V

5

V

-

1

2,3

OSC ,

I/O

System clock terminal

2

OSC

Oscillation C and R are incorporated. (Normally Open)

1

For external clock operation, the clock should be input on OSC .

17

18

P/S

RS

I

Serial input select terminal (fixed to "L")

Register selection signal input terminal

"0" instruction register. (Writing)

"1" Data register. (Writing, Reading)

19

20

R/W

I

Read(R) / Write(W) selection signal input terminal

Serial clock input terminal

E/SCL

7

23

DB /CS

I

Chip select signal

6

24

DB /SIO

I/O

I

Data input terminal

(3-state data bus.)

0

5

25 - 30

22

DB - DB

I/O port output terminal

REQ

O

This terminal normally output "L".

When confirm a key action, REQ terminal output puls.

21

LCD/KEY

I

Fix to "H" Level

o

7

35 - 42

S -S

O

Key scan signal data output terminal

Open Drain Output

0

3

31 - 34

K - K

I

Key scan data input terminal

In case of non use, fix to "H".

1

32

158 - 151

65 - 72

COM - COM

O

Common signal output terminal

150 - 143

73 - 80

1

162 - 159

163

COMM -

O

Icon common display signal output terminal

Static driving common signal output terminal

4

COMM

1

COMS

DD

SS

When power down mode V or V levels are output.

1

60

82 - 141

81,142

SEG - SEG

O

Segment signal output terminal

1

2

SEGM ,SEGM

Icon segment driving signal output terminal

NJU6475B

PAD No.

57

Symbol

I/O

O

F u n c t i o n

1

SEGS

Static driving segment signal output terminal

DD

SS

When power down mode V or V level are output.

10,9

8,7

C1⁺C1^-

C2⁺,C2^-

I/O

Step up voltage capacitor connecting terminal

5OUT

6

V

O

Step up voltage output terminal

REG

13

V

Voltage regulator output terminal

Connect the resistor between this terminal and VR terminal.

12

16

VR

I

Reference voltage for voltage regulator input terminal

Connect the resistor between this reference voltage and

DD

V

terminal.

Reset terminal

When the "L" level input over than 1.2ms to this terminal,

RESET

osc

the system is reset (at f =180KHz).

Common and Segment driver location order select terminal.

15

14

SEL

TEST

NC

I

-

"0" Mode A location (See

"1" Mode B location (See

PAD COORDINATES)

Maker test terminal

This terminal should be connected to V (or open.)

SS

43 - 47

50 - 63

Non connection terminal

These terminals are electrically open.

164 - 168

169

49

1

ALI-A1

ALI-A2

ALI-B1

ALI-B2

Alignment mark

These terminals are electrically open.

-

48

NJU6475B

FUNCTIONAL DESCRIPTION

(1) Description for each blocks

(1-1) Register

The NJU6475B incorporates three 8-bit registers, an instruction register (IR), and a Data Register (DR), Key

Register (KR). The register (IR) stores an instruction code such as "clear display" and "cursor shift" or address

data for Display Data RAM (DD RAM), Character Generator RAM (CG RAM) and Icon Display RAM (MK RAM).

The MPU can write the instruction code and address data to the register (IR), but it cannot read out from

register (IR). The Register (DR) is a temporary register, the data stored in the Register (DR) is written into

DD RAM, MK RAM. A register from these two registers is selected by the register select signal (RS). Register

(KR) is an only temporary register for key scan data. This Register (KR) can read out the contents when

selected Key signal at "H" signal. And non relation ship with signal of register select (RS).

The Relation ship with RS, R/W register as shown below.

<Table-1> Register selection

RS R/W

O p e r a t i o n

0

IR write & internal register operation mode

(Clear Display etc...)

0

1

0

Read out (KR)

Write (DR) & internal register operation mode

(DR DD RAM/CG RAM/MK RAM)

1

Read out (KR)

(1-2) Address Counter (AC)

The address counter (AC) addresses the DD RAM, CG RAM or MK RAM. When the address setting instruc-

tion is written into register (IR), the address information is transferred from register (IR) to the address counter

(AC). The selection of DD RAM, CG RAM or MK RAM is also determined by this instruction.

After writing (or reading) the display data to (or from) the DD RAM, CG RAM or MK RAM, the address counter

(AC) increments (or decrements) automatically.

(1-3) Display Data RAM (DD RAM)

The display data RAM (DD RAM) consisting of 48 x 8 bits stores up to 48-character display data represented

in 8-bit code.

The DD RAM address data set in the address counter (AC) is represented in Hexadecimal code.

(Example) DD RAM Address "08"

upper order bit

lower order bit

6

5

4

3

2

1

0

AC AC

AC

0

1

0

hexadecimal

0

8

NJU6475B

(1-3-1) The relation between DD RAM address and display position on the LCD

-12-Characters 4-Line Display

1

2

3

4

5

6

7

8

9

10 11 12

Display Position

1st Line 00 01 02 03 04 05 06 07 08 09 0A 0B

2nd Line 10 11 12 13 14 15 16 17 18 19 1A 1B

3rd Line 20 21 22 23 24 25 26 27 28 29 2A 2B

4th Line 30 31 32 33 34 35 36 37 38 39 3A 3B

DD RAM Address

(Hexadecimal)

When the display shift is performed, the DD RAM address changes as follows:

[Left shift display]

(00)

(10)

(20)

(30)

01 02 03 04 05 06 07 08 09 0A 0B 00

11 12 13 14 15 16 17 18 19 1A 1B 10

21 22 23 24 25 26 27 28 29 2A 2B 20

31 32 33 34 35 36 37 38 39 3A 3B 30

[Right shift display]

0B 00 01 02 03 04 05 06 07 08 09 0A

1B 10 11 12 13 14 15 16 17 18 19 1A

2B 20 21 22 23 24 25 26 27 28 29 2A

3B 30 31 32 33 34 35 36 37 38 39 3A

(0B)

(1B)

(2B)

(3B)

(1-4) Character Generator ROM (CG ROM)

The Character Generator ROM (CG ROM) stores 5 x 8 dots character pattern represented in 8-bit character

code. The capacity is up to 252 kinds of 5 x 8 dots character pattern.

The correspondence between character code and standard character pattern of NJU6475B is shown in table 2.

User defined character patterns (Custom Font) are also available by mask option. (in this case, the address

H

(20) are using for "Space Pattern".)

NJU6475B

<Table-2> The Correspondence Between Character Code

and Standard Character Pattern (ROM Version -02)

NJU6475B

(1-5) Character Generator RAM (CG RAM)

The Character Generator RAM stores any kinds of character pattern in 5 x 8 dots written by the user

program to display user's original character pattern. The CG RAM can store 4 kinds of character in 5 x 8 dots

mode.

H

To display user's original character pattern stored in the CG RAM, the address data (00) -(03) should

be written to the DD RAM as shown in Table-3.

<Table-3> Correspondence of CG RAM address, DD RAM character code

and CG RAM character pattern (5 x 8 dots)

Character Code

(DD RAM Data)

7 6 5 4 3 2 1 0

Character Pattern

(CG RAM Data)

4 3 2 1 0

CG RAM Address

7 6 5 4 3 2 1 0

Upper

Bits

Lower

Bits

Upper

Lower Upper

Lower

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1 1 1 1 0

1 0 0 0 1

1 1 1 1 0

1 0 1 0 0

1 0 0 1 0

1 0 0 0 1

0 0 0 0 0

Character Pattern

Example (1)

0 0 0 0 0 0 0 0

0 1 0 0 0

Cursor Position

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1 0 0 0 1

0 1 0 1 0

1 1 1 1 1

0 0 1 0 0

1 1 1 1 1

0 0 1 0 0

0 0 0 0 0

Character Pattern

Example (2)

0 0 0 0 0 0 0 1

0 1 0 0 1

Cursor Position

0 0 0

0 0 1

0 0 0 0 0 0 1 1

0 1 0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Notes : 1. Character code bit 0,1 correspond to the CG RAM address bit 3,4 (2bits ; 4patterns).

2. CG RAM address 0 to 2 designate character pattern line position. The 8th line should be "0".

If there is "1" in the 8th line, but bit "1" is always displayed on the cursor position regardless of cursor

existence.

3. Row position character pattern correspond to CG RAM data bits 0 to 4 are shown above.

4. CG RAM character patterns are selected when character code bits 2 to 7 are all "0" and these are

addressed by character code bits "0" and "1".

5. "1" for CG RAM data corresponds to display on and "0" to display off.

NJU6475B

(1-6) Icon display RAM (MK RAM)

The NJU6475B can display maximum 128 Icons.

The Icon display can be controlled by writing the data into MK RAM corresponding to the Icons.

The relation between MK RAM address and Icon display position is shown in Table-4.

<Table-4> Correspondence among Icon Position, MK RAM Address and Data

MK RAM Address Bits for Icon Position MK RAM Address and Data

H

7

6

5

4

3

2

1

0

(60 - 7F )

D

*

D

*

D

*

D

1

5

D

2

6

D

3

7

D

4

8

D

H

0110 0000 60

0110 0001 61

97

98

1

COMM Line and

Both besides of 1st Line

H

0110 0101 65

0110 0110 66

0110 0111 67

0110 1000 68

0110 1001 69

*

21

*

25

29

22

*

26

30

23

*

27

31

24 102

1

3

5

7

*

103

104

(COM ,COM ,COM ,COM )

28 105

32 106

2

COMM Line and

Both besides of 2nd Line

H

0110 1101 6D

0110 1110 6E

0110 1111 6F

0111 0000 70

0111 0001 71

*

45

*

49

53

46

*

50

54

47

*

51

55

48 110

H

9

11

13

15

*

111

112

(COM ,COM ,COM ,COM )

H

52 113

56 114

3

COMM Line and

Both besides of 3rd Line

H

0111 0101 75

0111 0110 76

0111 0111 77

0111 1000 78

0111 1001 79

*

69

*

73

77

70

*

74

78

71

*

75

79

72 118

17

19

21

23

*

119

120

(COM ,COM ,COM ,COM )

76 121

80 122

4

COMM Line and

Both besides of 4th Line

H

0111 1101 7D

0111 1110 7E

0111 1111 7F

*

93

*

94

*

95

*

96 126

H

25

27

29

31

*

127

128

(COM ,COM ,COM ,COM )

H

Notes : 1. When the Icon display function using, the system should be initialized by the software initialization

Because the MK RAM is not initialized by the power on reset and hardware.

1

2

1

4

2. The cross-points between segments (SEGM and SEGM ) and commons (COMM to COMM and

2

32

COM to COM ) are always set "OFF" level.

3. In the table 4, * mark are invalid, therefore both of "0" or "1" can be written but these are no meaning.

NJU6475B

(1-7) Timing generator

The timing generator generates a timing signals for the DD RAM, CG RAM and MK RAM and other

internal circuits. RAM and timing for the display and internal operation timing for MPU access are separately

generated, so that may not interfere with each other.

Therefore, when the data write to the DD RAM for example, there will be undesirable influence, such as

flickering, in areas other than display area.

(1-8) LCD Driver

LCD Driver consists of 37-common driver and 63-segment driver. The character pattern data are latched

to the addressed segment-register respectively.

This latched data controls display driver to output LCD driving waveform.

(1-9) Cursor Blinking control circuit

This circuit controls cursor On / Off and cursor position character blinking. The cursor or blinking appear in

H

the digit locating at the DD RAM address set in the address counter (AC). When the address counter is (08) ,

a cursor position is shown as bellow.

6

5

4

3

2

1

0

AC

0

AC

1

AC

0

AC

0

AC

0

AC

0

4-Line Display

1

2

3

4

5

6

7

8

9

10 11 12

Display position

1st Line 00 01 02 03 04 05 06 07 08 09 0A 0B

2nd Line 10 11 12 13 14 15 16 17 18 19 1A 1B

3rd Line 20 21 22 23 24 25 26 27 28 29 2A 2B

4th Line 30 31 32 33 34 35 36 37 38 39 3A 3B

DD RAM Address

(Hexadecimal)

Cursor position

Note : The cursor or blinking also appear when the address counter (AC) selects the CG RAM or the MK RAM.

But the displayed cursor and blinking are meaningless.

If the AC stores the CG or MK RAM address data, the cursor and blinking are displayed in the meaning-

less position.

NJU6475B

(2) Power on Initialization by internal circuits

(2-1) Internal Reset circuits Initialization

The NJU6475B is automatically initialized by internal power on initialization circuits when the power is turned

on. In the internal power on initialization, following instructions are executed.

During the Internal power on initialization, the busy flag (BF) is "1" and this status is kept during 6ms

OSC

DD

(f =180KHz) after V rose to 2.4V.

Initialization sequence

Set Function

PD=1 : Power down OFF

H

Contrast Control

Set (00) to the contrast register

Display ON/OFF

Control

D=0

C=0

B=0

: Display OFF

: Cursor OFF

: Cursor Blink OFF

I/D=1 : Increment by 1

S=0 : Non shift

Set Mode Entry

Clear Display

E N D

Note : If the condition of power supply rise time described in the Electrical Characteristics is not satisfied, the

internal Power On Initialization will not performed.

In this case, the software initialization by MPU is required.

(2-2) Hardware Initialization

The NJU6475B prepares RESET terminal to initialize the all system.

When the "L" level is input over 1.2ms to the RESET terminal, reset sequence is executed. In this time, the

OSC

busy signal is output during 6ms (f =180KHz) after RESET terminal went to "H".

-Timing Chart

Over 1.2ms

External Reset

Signal

6ms

BUSY

NJU6475B

(3) Instruction

The NJU6475B incorporates two registers, an Instruction Register (IR) and a Data Register (DR). These

two registers store control information temporarily to allow interface between NJU6475B and MPU or peripheral

IC operating different cycles. The operation of NJU6475B is determined by this control signal from MPU.

The control information includes resister selection signals (RS), Read / Write signals (R/W) and data signal

(SIO).

<Table-5> shows each instruction and its operating time

Execute Time

C

o

d

e

(MAX)

CP

OSC

Instruction

Maker Test

D e s c r i p t i o n

(f or f

R/W DB⁷DB⁶DB⁵DB⁴DB³DB²DB¹DB⁰

RS

0

=180kHz)

0

All "0" code is using for

maker testing.

-

Clear Display

Return Home

0

1

Clears Display and sets RAM

5.42ms

H

address (00) in AC.

H

Sets RAM address (00) in AC

0

1

*

and returns shifted display to

original position. RAM contents

are not changed

sets cursor move direction and

display shift operation which are

performed at data read/write.

83.4us

0us

Entry Mode Set

0

I/D

S

Display ON/OFF

Set Display Control

Control

0

1

D

C

B

*

On /Off (D), cursor On /Off (C)

and character blinking (B) at

cursor position.

moves cursor and shifts dis-

play without changing RAM(DR)

contents.

0us

Cursor or

Display Shift

Cursor :

83.4us

Display : 0us

S/C R/L

0

1

*

Function Set

*

PD Sets Interface data length (DL)

and power down mode (PD).

0us

Electronic Volume

Register Set

0

1

*

Electronic

Sets Vreg data to EVR control

volume register.

0us

RAM Address Set

Address

Sets RAM Address. After this

83.4us

instruction, the data is trans-

ferred to/from RAM.

Key Data Read

0

1

0

Read Data (KEY DATA)

When LCD/Key= "1", reads key

data out.

0us

Data Write to CG

or DD or MK RAM

Write Data (DD RAM)

(CG RAM)

Writes data into DD or CG or

MK RAM.

83.4us

*

(MK RAM)

I/D=1:Increment, I/D=0:Decrement,

S=1:Include Display Shift,

S/C=1:Shift Display, S/C=0:Cursor

shift, R/L=1:Shift to Right,

DD RAM : Display data RAM

CG RAM : Character generator

RAM

When FRQ is

changed, the

execute time is

also changed.

* : Don't care

MK RAM : Icon display RAM

R/L=1:Shift left, PD=0:Power Down Mode AC : Address counter use for

PD=1:Cancel Power Down Mode DD, CG and MK RAM

Note : If the oscillation frequency is changed, the execution time is also changed.

NJU6475B

(3-1) Description of each instructions

(a) Maker Test

7

6

5

4

3

2

1

0

RS R/W DB

DB

0

DB

0

DB

0

DB

0

DB

0

DB

0

DB

0

Code

(b) Clear Display

0

7

6

5

4

3

2

1

0

RS R/W DB

DB

0

DB

0

DB

0

DB

0

DB

0

DB

0

DB

1

Code

0

Clear Display Instruction is executed when the code "1" is written into DB .

H

When this instruction is executed, the space code (20) is written into every DD RAM address, then

H

the DD RAM (00) is set into address counter and I/D of entry mode is set as increment mode. If the cursor

or blink are displayed, they are returned to the left end of the 1st line on the LCD panel.

In addition, S of entry mode is not changes and contents of MK RAM and CG RAM are also not changed.

H

Note : The character code (20) must be blank code in the user defined character pattern (Custom font).

(c) Return Home

7

6

5

4

3

2

1

0

RS R/W DB

DB

0

DB

0

DB

0

DB

0

DB

0

DB

1

DB

*

Code

0

*= Don't Care

1

Return Home instruction is executed when the code "1" is written into DB .

H

When this instruction is executed, the DD RAM address (00) is set into the address counter. Display is

returned to its original position if shifted, the cursor or blink are returned to the left end of the 1st line on

the LCD if the cursor or blink are operating. The DD RAM contents do not change.

(d) Entry Mode Set

7

6

5

4

3

2

1

0

RS R/W DB

DB

0

DB

0

DB

0

DB

0

DB

1

DB

I/D

DB

S

Code

0

Entry Mode Set instruction which sets the cursor moving direction and display shift On/Off, is executed

2

1

0

when the code "1" is written into DB and codes of (I/D) and (S) are written into DB (I/D) and DB (S).

(I/D) sets the address increment or decrement, and the (S) sets the entire display shift at the DD RAM

writing.

I/D

1

F u n c t i o n

Address increment : The address of the DD RAM or CG RAM increment (+1) when the

read/write operation, and the cursor or blink moves to the right.

0

Address decrement : The address of the DD RAM or CG RAM decrement (-1) when the

read/write operation, and the cursor or blink moves to the left.

S

F u n c t i o n

Entire display shift.

The shift direction is determined by I/D. : shift to left at I/D=1 and shift to the right at

the I/D=0. The shift is operated only for the character, so that it looks as if the cursor

stands still and display moves.

The display does not shift when reading from DD RAM and writing/reading into/from

CG RAM.

1

0

The display does not shift.

NJU6475B

(e) Display ON/OFF Control

RS R/W DB

7

6

5

4

3

2

1

0

DB

0

DB

0

DB

0

DB

1

DB

D

DB

C

DB

B

Code

0

Display ON/OFF control instruction which controls the whole display ON/OFF, the cursor ON/OFF and the

3

cursor position character blink, is executed when the code "1" is written into DB and codes of (D), (C)

2

1

0

and (B) are written into DB (D), DB (C) and DB (B), as shown below.

D

1

F u n c t i o n

Display On

0

Display Off. In this mode, the display data remains in the DD RAM so that it is

retrieved immediately on the display when the D changes to 1.

C

1

F u n c t i o n

Cursor On. The cursor is displayed by 5 dots on the 8th line.

0

Cursor Off. Even if the display data write, the I/D etc does not change.

B

1

F u n c t i o n

The cursor position character is blinking.

Blinking rate is 480ms at f =180KHz.

OSC

The cursor and the blink can be displayed simultaneously.

0

The character does not blink.

Character Font 5×7 Dots

Alternating Display

(1) Cursor Display Example

(2) Brink Display Example

(f) Cursor Display Shift

7

6

5

4

3

2

1

0

RS R/W DB

DB

0

DB

0

DB

1

DB

*

DB

*

Code

0

S/C R/L

*= Don't Care

The cursor /display shift instruction shifts the cursor display to the right or left without writing or reading

display data. This function is used to correct or search the display. The cursor moves to the 2nd line after

the 12nd digit of the 1st line. Notice that 1st to 3rd line displays shift at the same time. When the displayed

data are shifted repeatedly, each display moves in only same line. The 2nd and 3rd line display do not shift

into the 1st and 2nd line.

The contents of address counter (AC) does not change by operation of only the display shift.

4

This instruction is executed when the code "1" is written into DB and the codes of (S/C) and (R/L) are

3

2

written into DB (S/C) and DB (R/L), as shown below.

S/C

0

1

R/L

0

1

0

1

F u n c t i o n

Shift the cursor position to the left ((AC) is decremented by 1).

Shift the cursor position to the right ((AC) is incremented by 1).

Shifts the entire display to the left and the cursor follows it.

shifts the entire display to the right and the cursor follows it.

NJU6475B

(g) Function Set

7

6

5

4

3

2

1

0

RS R/W DB

DB

0

DB

1

DB

*

DB

*

DB

*

DB

*

DB

Code

0

PD

*= Don't Care

Function set instruction which sets the interface data length and power down is executed, when the code

5

0

"1" is written into DB and (PD) is written into DB , as shown below.

When the power down mode is set, the display turns off automatically. Afterward, when the power down

mode is reset, the display is off continuously.

The display appears by the display on instruction.

PD

1

F u n c t i o n

Power down mode off (Normal operation)

0

Power down mode on (the display goes to off automatically.)

(h) Set Electronic Volume Register

7

6

5

4

3

2

1

0

RS R/W DB

DB

1

DB

*

DB

*

DB

3

2

1

0

Code

0

C

*= Don't Care

Higher order bit

Lower order bit

Contrast Control instruction which adjusts the contrast of LCD, is executed when the code "1" is written

6

0

3

0

3

into DB and the codes of C to C are written into DB to DB as shown below.

The contrast of LCD can be adjusted one of 16 voltage stage by setting 4 bit register.

Set the binary code "0000" when contrast control unused.

3

2

1

0

LCD

DD

5

C

0

C

0

C

V

= V - V

0

1

0

low

:

1

high

NJU6475B

(i) Set RAM Address

Code

7

6

5

4

3

2

1

0

RS R/W DB

DB

A

DB

A

DB

A

DB

A

DB

A

DB

A

DB

A

0

1

Higher order bit

Lower order bit

7

The RAM address set instruction is executed when the code "1" is written into DB and the address is

6

0

written into DB to DB as shown above.

6

0

The address data (DB to DB ) is written into the address counter (AC) by this instruction.

After this instruction execution, the data writing/reading is performed into/from the addressed RAM.

The RAM includes DD RAM, CG RAM and MK RAM and these RAMs are shared by addressed as shown

below.

RAM Address

H

DD RAM 1st Line

DD RAM 2nd Line

DD RAM 3rd Line

:

(00) to (0B)

H

(10) to (1B)

H

(20) to (2B)

H

DD RAM

4th Line

(30) to (3B)

H

CG RAM 4 Characters :

(40) to (5F)

H

MK RAM 128 Icons

(j) Write Data to CG, DD or MK RAM

-Write Data to DD RAM

:

(60) to (7F)

7

6

5

4

3

2

1

0

RS R/W DB

DB

D

DB

D

DB

D

DB

D

DB

D

DB

D

DB

D

Code

1

0

D

Higher order bit

Lower order bit

-Write Data to CG or MK RAM

RS R/W DB

7

6

5

4

3

2

1

0

DB

*

DB

*

DB

D

DB

D

DB

D

DB

D

DB

D

Code

1

0

*

*= Don't Care

Higher order bit

Lower order bit

Write Data to RAM instruction is executed when the code "1" is written into (RS) and code "0" is written into

(R/W).

By the execution of this instruction, the data is written into RAM. The selection of RAM is determined by the

previous instruction.

After this instruction execution, the address increment (+1) or decrement (-1) is performed automatically

according to the entry mode set.

NJU6475B

(3-2) Initialization using the internal reset circuit

When internal reset operates for initialization, the function set, Display ON/OFF Control and Entry Set instruc-

tion must be executed before the data input as shown below.

Initialized

No display appears

Power On

RS R/W DB⁷DB⁶DB⁵DB⁴DB³DB²DB¹DB⁰

Function Set

0

1

*

1

Power down mode OFF

Turn on display and cursor.

Entire display is in space

mode. In case of mark dis-

play function, the contens

of MK RAM should be ini-

tialized by instruction be-

fore the display on.

Display ON/OFF

Control

0

1

0

Example for address incre-

ent and cursor right shift

when the data is written to

the DD, CG or MK RAM.

Entry Mode Set

0

1

0

Write data to the DD, CG or MK RAM

and set the instruction

NJU6475B

(3-3) Initialization by instruction

If the power supply conditions for the correct operation of the internal reset circuits are not met,

the NJU6475B must be initialized by instruction.

Initialized

No display appears

Power On

Wait more than 6ms

DD

after V rises to 2.4 V

RS R/W DB⁷DB⁶DB⁵DB⁴DB³DB²DB¹DB⁰

Function Set

0

1

*

Wait more than 3.0ms

Function Set

Wait more than 200us

Function Set

Set operation and power

down mode OFF.

Function Set

Display Off

0

1

*

Display Clear

Entry Mode Set

Example for address incre-

ment and cursor right shift

when the data is written to

The DD, CG or MK RAM.

Write data to the DD, CG or MK RAM

and set the Instructions

Note : When the Icon display function using, the contents

of MK RAM should be initialized by instruc-

tion before the display on.

NJU6475B

(4) Power down Function

NJU6475B incorporates the power down mode to reduce the operating current.

The power down mode is set/reset by the function set instruction.

In the power down mode, all the character display and Icon display turn off and only static display operation

is available.

The status of internal circuits at the power down mode is shown below.

-Main oscillator stops and sub oscillator for the static display starts the operation.

-Voltage converter, Key Scan, Voltage Regulator, Voltage follower (OP-AMP) are stopped.

-The contents of DD, CG, MK RAM are kept.

(5) LCD Display

(5-1) Power Supply for LCD Driving

NJU6475B incorporates voltage converter to generate the LCD driving voltage which is adjusted by the

voltage regulater and the EVR.

(a) Voltage Converter

-Voltage Tripler

+

-

+

-

SS

5OUT

By connecting capacitor between C1 and C1 , C2 and C2 , V and V

respectively, two times

DD

SS

5OUT

negative voltage of V --V output from V

.

-Voltage Doubler

+

-

respectively, and connecting the C1⁺

SS

5OUT

By connecting capacitor between C2 and C2 , V and V

+

-

DD

SS

5OUT

terminal to C2 terminal, and C1 terminal being open, negative voltage of V --V output from V

.

DD

V

=+3V

=±0V

= -3V

V

=+3V

=±0V

SS

5OUT

V

Voltage Doubler

= -6V

Voltage Tripler

(b) Voltage Regulator

DD

5OUT

Voltage Regulator incorporates a OP-AMP which is supplied V and V , and a reference voltage

REF

source (V ).

REF

By setting the VR level by connecting Ra and Rb, the regulator which amplifies V , outputs the LCD

REG

driving voltage to the V terminal.

DD

REG

Therefore the LCD driving voltage can be output between V and V by setting.

REG

REF

DD

REG

5OUT

< V

V

= ( 1+ Rb / Ra) V in condition, V = 0V, V

REF

The EVR functions V value adjustment from 1st step to 16th by a step when the 4 bit data write into the

EVR register by the instruction.

H

Set the EVR register to (00) when the EVR function is unused. Use variable resistances to external to the

REF

external resistances Ra, Rb and thermistor if need due to the voltage reference V is changed by the lot

and operating temperature.

Take care the noise input on the VR terminal because of it is designed with high impedance. Short wiring

should be required to avoid the noise input, if necessary.

NJU6475B

REF

[ The Voltage Reference V Characteristics ]

DD

V

SS

Supply Voltage

:

= 0V, V = -3V

Temperature : 25 °C

-5

-6

-7

-8

00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH0DH 0EH 0FH

Electric Volume value

REG

[ The LCD Operating Voltage V

Characteristics ]

DD

SS

5OUT

Supply Voltage

: V = 0V, V

= -3V,

Voltage Tripler Output : V

= -9V

External Resistances : Ra = 180KΩ, Rb = 820KΩ

Temperature : 25 °C

REG

H

REF

H

Used Formulation

: V (XX) = (1 + 820kΩ/180kΩ) V (XX)

-1.05

-1.1

-1.15

-1.2

-1.25

-1.3

00H

02H

04H

06H

08H

0AH

0CH

0EH

01H

03H

05H

07H

09H

0BH

0DH

0FH

Electric Volume value

NJU6475B

(c) Bleeder Resistance

1

2

3

4

5

Each LCD driving voltage (V , V , V , V , V ) is generated by the high impedance bleeder resistance

buffered by voltage follower OP-AMP to get a enough display characteristics with low operating current. The

bleeder resistance is set 1/7 bias suitable for 1/36 duty by 5MΩ resistance in total.

5

DD

5

The capacitor connected between V and V is needed for stabilizing V . The determination of the each

1

2

3

capacitance of C , C and C generating for LCD operating voltage is required to operate with the LCD

panel actually.

The capacitance for the typical application is shown below:

LCD Driving Voltage vs Duty

Power

Supply

Duty Ratio

Bias

1/36

1/7

LCD

DD

V

5

V

- V

LCD

V

is the maximum amplitude for LCD driving voltage.

Typical application for LCD operating voltage generation

Note : Take care the noise into the VR terminal as designed with high impedance.

Short wiring or sealed wiring are required to avoid the noise, if necessary.

NJU6475B

(5-2) Relation between oscillation frequency and LCD frame frequency

As the NJU6475B incorporates oscillation capacitor and resistor for CR oscillation, 180KHz oscillation is

available without any external components. (1 Clock = 5.56us)

1/36 Duty

1 frame = 5.56 (us) x 62 x 36 = 12.4 (ms)

Frame frequency = 1 / 12.4 (ms) = 80.6 (Hz)

NJU6475B

(6) Key Scan Circuit

(6-1) Key scan timing chart

CHATTERING

0

3

K to K

Continuously 3 times "L" detection

Continuously 3 times "H" detection

KEYCHECK

(Inner Side

of NJU6475B) Fig. 1

REQ

H H H L L L KEYCHECK

0.71mS KEYCHECK L H H L H H H KEYCHECK

Fig. 2

LCD/KEY

R/W

DB7/CS

E/SCL

LCD DATA(Write)

Set Key Register

(Inner Side

Set "00010000 00000000" into Register

"Hi-Z"

of NJU6475B)

0

7

S to S

Fig. 4

Fig. 3

(6-2) Key Scan

1. KEYCHECK signal always operates to check the status of keys excepting for power down mode.

0

3

2. When Key signal (K to K ) 3 times detected continuously at rise up edge of KEYCHECK (inner side

NJU6475), key Scan circuit performs output request signal (REQ terminal) rise to "H" and simultaneously

key input information transmit to CPU. Its useful for anti-chattering. At the same time of REQ signal output,

0

the key register status is "00010000 00000000" (Non Key Input) automatically. Key input terminal (K to

3

K ) are "H" in normal, then turn to "L" when Key input.

CHATTERING

0

3

K to K

Continuously 3 times "L" detection

H H H L L L 0.71mS

KEYCHECK

(Inner Side

of NJU6475B)

REQ

Fig. 1

In case of request signal "H", When detects 3 times continuously key released status, request signal will be "L".

CHATTERING

0

3

K to K

Continuously 3 times "H" detection

L H H L H H H

KEYCHECK

(Inner Side

of NJU6475B)

REQ

Fig. 2

NJU6475B

3. When the request signal is detected, CPU should be LCD / KEY to "H" and read out key data by instruc-

tion. 16-bit key data synchronizing to "SCL" (SCL terminal) is read out to CPU.

(1st time output key data was fixed as "00010000 00000000")

keyscan operation start from the next rising edge of SCL after the end of key data read out opration.

Fig. 3

0

3

0

7

4. The key data are gotten from 4 terminals (K to K ) at each timing of key scan signals (S to S ).

The detected data are up dating anytime and stores to key register.

0

S

"L"

1

S

·

7

S

0.45mS

Fig. 4

End of Key Scan

- Key scan timing : 0.45ms (fosc = 180KHz,MAX =0.64ms)

- Pulth width

: 45us (fosc = 180KHz, MAX =64us)

NJU6475B

(6-3) Key scanning timing

kp

0

7

Key status is gotten at 3/4 port timing of t during "L" period of S to S .

0

S

kp

t

1

S

·

kp

1/4 t

kp

3/4 t

Detecting timing

(6-4) The format of detection

1st Byte

MSB

L3

2nd Byte

MSB

LSB

L0

LSB

L2

L1

H7

K

H6

H0

H5

K

H4

K

H3

K

H2

H1

H0

0

1

K

Fix

L3

L0

3

0

H7

7

0

K to K : Corresponds to K to K

K to K : Corresponds to S to S

( For Example )

1st Byte

MSB

2nd Byte

MSB

0

LSB

0

LSB

0

1

0

1

0

NJU6475B

(6-5) Key roll over input

NJU6475B can be accepted the key roll over input.

In case of key roll over input, the output results are shown below;

X

-Connecting same S signal line at multiple key push.

When key-in shown above case, the data contents are "00011100" "00000100".

X

-The case of connecting different S signal line at multiple key push (1)

When key-in shown above case, the data contents are "00010100" "00010100".

NJU6475B

X

-The case of connecting different S signal line at multiple key push (2)

When key-in like as shown above, the data contents are "00010101" "00010100".

In this case, the result will be same, at each key-in shown below.

[Case 1]

[Case 2]

[Case 3]

[Case 4]

[Case 5]

[Case 6]

NJU6475B

(6-6) The inner composition of Key Scan circuit

The inner composition of key scan circuit shown below :

N J U 6 4 7 5 B Inner Circuit

Output Nch

Open drain

O

Input Pull up

schmitt

· · ·

0

1

7

0

1

2

3

S

K

·

-In case of non input the key each terminal status shown below:

0

7

S to S : The status of Nch FET output side is ON, output result is "L".

0

3

K to K : The status is "H" by pull-up resistance.

X

-When any key key-in, K of key-in side turn to "L" and it can confirms.

0

3

-Input terminal (K to K ) are composed by schmitt inverter input method.

NJU6475B

(7) Interface with MPU

Interface circuit of NJU6475B can be connected to serial by turn to "L" P/S terminal on shown below serial

0

5

data timing. And DB to DB can be use to output port.

Notes : RS, R/W, LCD/KEY requires setting before CS fall down.

RS is unrelated to read out of key data and writing of port data.

Serial interface circuit is in operation at CS is "L".

When SCL rises, input data was lead, and rises CS case loading input data.

When the input data was less than 16 bits, input data will be invalid at rises CS. And so on equal or over than

16 bits case, rear side total 16 bits are effectiveness. The input data should be total 16 bits.

The data of read/write are composed MSB first.

NJU6475B

-Data format

The data formatted by 2 byte form at read/write.

When writing data consists LCD data and port data.

The using data in write mode means one of key data.

In write mode of data format, 1st byte means recognition data of LCD data and Port data.

In "0110 0000" (fixed) selects LCD data, in "0110 0001" (fixed) selects Port data.

The data of 2nd byte consists each data contents.

When the 1st byte of MSB 4 bit data are not "0110", in this case the input data will be invalid.

D⁷

D⁶

D⁵

D⁴

D³

D²

D¹

D⁰

DB⁷DB⁶DB⁵DB⁴DB³DB²DB¹DB⁰

*

LCD/ RS R/W

KEY

1st Byte

Higher

Selected Bit

(0110)

2nd Byte

Lower

Selected Bit LCD Data (Instruction)

(0000)

LCD

Data

0

1

0

Instruction

Execution

Time

Higher

Selected Bit

(0110)

Lower

Selected Bit LCD Data (RAM Data)

(0000)

LCD

Data

Instruction

Execution

Time

Higher

Lower

Output Port (Set "L"=0,"H"=1)

PORT

Data

Selected Bit

(0110)

Selected Bit

(0001)

Instruction

Execution

0

1

*

0

1

*

Time

Key Data 1

Key Data 2

Selected Bit

(0001)

KEY

Data

*

* : Invalid Data

Notes : The instruction requires execution time after transmit 16 bit data. After transmit data can not transmit

continuously

NJU6475B

MAXIMUM ABSOLUTE RATINGS

P A R A M E T E R

Supply Voltage (1)

Input Voltage

SYMBOL

R A T I N G S

- 0.3 ~ + 7.0

UNIT

V

N O T E

DD

V

t

DD

- 0.3 ~ V + 0.3

V

Operating Temperature

Storage Temperature

Topr

Tstg

- 30 ~ + 80

°C

- 55 ~ + 125

Note-1 : If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed. Using

the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the

electric characteristics conditions will cause malfunction and poor reliability.

DD

SS

Note-2 : Decoupling capacitor should be connected between V and V due to the stabilized operation for

the voltage converter.

SS

Note-3 : All voltage value are specified as V = 0V.

DD

SS

DD

SS

5out

SS

The relation : V > V , V > V ≥ V , V = 0V must be maintained.

NJU6475B

DD

ELECTRICAL CHARACTERISTICS (V = 2.4 ~ 3.6V, Ta = -20 ~ +75 °C)

SYMBOL

UNIT NOTE

P A R A M E T E R

C O N D I T I O N S

(OSC1, Except terminals K⁰~ K³)

MIN.

TYP.

MAX.

IH1

DD

V

0.8V

-

V

4

5

Input Voltage 1

IL1

SS

V

DD

0.2V

IH2

K⁰~ K³

DD

(Application to terminals

)

0.8V

V

Input Voltage 2

Input Voltage 3

IL2

SS

V

DD

0.2V

)

V

IH3

DD

(Applicate to terminal OSC1)

V -0.5

V

IL3

SS

V

0.5

-

V

OH1

OL1

OL2

COM1

OH

DD

-I = 0.205mA, V = 3.0V

2.0

V

Output Voltage 1

OL

DD

I = 1.6mA, V = 3.0V

-

0.5

0.6

V

0

7

OL

Output Voltage (S ~ S )

I = 300uA

V

d

Driver ON-resist (COM)

R

±I = 1uA (All COM Terminal)

20

30

40

50

kΩ

8

O

DD

5

V = V , V

SEG1

COM2

SEG2

1

d

Driver ON-resist (SEG)

±I = 1uA (All SEG Terminal)

-

kΩ

O

DD

5

V = V , V

d

Driver Output-resist

(COM)

±I = 1uA (All COM Terminal)

O

1

4

V = V , V

d

Driver Output-resist

(SEG)

±I = 1uA (All SEG Terminal)

O

2

3

V = V , V

1

IV

V Sink Current

-

-12.3

-

uA

Driver current

4

V Source Current

16.8

-1

in

DD

Input Leak Current

ILI

-Ip

V = 0 ~ V

-

1

6

DD

K⁰~ K³

terminal)

Pull-up MOS Current

V

= 3V (ALL DB,

10

25

320

50

380

DD1

I

f

^OSC= Internal OSC on Display

^DD= 3V, On display, V = -5V

^OSC= Internal OSC on Display

^DD= 3V,On access, t^CYCE= 5uS

7

V

5

Operating Current

DD2

I

f

-

640

uA

V

5OUT

ef

DD

OUT

voltage

Output

Voltage

Efficiency

V

V = 3V

I

3 Times

= 100uA

-4.6

-4.8

95.0

Ta = 25°C

converter

Part

L

R = ∞

3 Times

90.0

%

1

2

3

4

V

Ta = 25°C

2.44

2.01

0.73

0.30

2.57

2.14

0.86

0.43

2.70

2.27

0.99

0.56

DD

V = 3V

LCD Drive Voltage

V

5

V = 0V

Measured at COM/SEG

terminal

Bleeder Resistance

B

DD

5

B

DD

5

R (V - V )/IB

R

V

- V = 3V

5.0

MΩ

B

I :Bleeder Resistance Cur.

B

R : 5 Bleeder Resist

REG

R^L= , R^RV=1M , V^5OUT= -10.8V

DD

Output Voltage

reg. Operating voltage

Reference Voltage

V

∞

Ω

V -10.8

-

V -1.8

5OUT

REF

DD

V -11

DD

V

Reference

V -3.6

V

DD

Reference, Ta=25°C

V -0.75 V -1.05 V -1.35

OSC

Clock Oscillation Freq.

LCD Driving Voltage

f

V = 3V, Ta=25°C

125

180

-

235

kHz

V

LCD

5OUT

DD

V -3

DD

V

Terminal, V = 3V

V -13.5

9

NJU6475B

Note-4 : Input/Output structure except LCD display are as shown below.

-Input terminal structure

(without pull-up MOS)

Applicated terminals : E/SCL, RS,

R/W, P/S, SEL, RESET, LCD/KEY

(Pull-up with MOS, schmitt)

(Pull down MOS)

TEST

0

3

K ~ K

-Input terminals structure

Applicated terminal : OSC1

-Common terminals

Input/Output structure.

Applicated terminal

7

0

: DB to DB

NJU6475B

Note-5 : Apply to the output and Input/Output Terminals.

Note-6 : Except current of pull-up MOS and output drive MOS.

Note-7 : Except Input/Output part current but including the current on bleeder resistance.

If the input level is medium, current consumption will increase due to penetration current.

therefore, the input level must be fixed to "H" or "L".

-Operating Current Measurement Circuit

DD

5OUT

Note-8 : Rcom and Rseg are the resistance values between power supply terminals (V , V ) and

1

32

1

4

DD

each common terminal (Com to Com / COMM to COMM ) and Supply voltage (V ,

5OUT

1

60

1

2

V

) and each segment terminal (SEG to SEG / SEGM to SEGM ) respectively, and

measured when the current Id is flown on every common and segment terminals at same time.

Note-9 : Apply to the voltage from each COM and SEG are less than ±0.15V against the LCD driving

DD

5OUT

contrast voltage (V , V ) at no load condition.

NJU6475B

BUS TIMING CHARACTERISTICS

-Serial Interface sequence

DD

SS

(V = 2.4 ~ 3.6V, V = 0V, Ta = -20 ~ +75°C)

P A R A M E T E R

Serial clock cycle time

SYMBOL

MIN.

1

300

700

-

500

200

300

-

200

-

MAX.

-

20

-

20

-

CONDITION

Fig. 1

UNIT

uS

nS

CYCE

t

SCH

Serial clock

"High" level

"Low" level

t

SCL

width

t

SCr

t , t

SCf

Serial clock rise and fall down time

Chip select pulse width

Chip select set up time

Chip select hold time

Chip select rise and fall time

CS

PW

CSU

t

CH

CSr

t , t

CSf

AS

t

Set up time

RS, R/W, LCD/KEY-CS

AH

Address hold time

t

SISU

Serial input data set up time

Serial input data hold time

Serial output data delay time

Serial output data hold time

t

SIH

t

-

SOD

t

700

-

SOH

t

200

Serial Interface

Fig. 3 Serial Interface Sequence Characteristics

NJU6475B

-I/O Part sequence

P A R A M E T E R

Port set time

S Y M B O L MIN.

MAX.

500

CONDITON

Fig. 2

UNIT

uS

PS

t

-

0

7

-The load of DB to DB is CL = 100 pF

CS

IH1

V

IH1

V

0

5

DB ~ DB

PS

t

IL1

V

Fig. 2 I/O Port Sequence (Serial Interface)

-The input conditions of using hardware reset circuit.

Input Timing

RSL

t

RESET

VIL

P A R A M E T E R

Reset Input RAW level width

SYMBOL

CONDITION

-

MIN.

1.2

TYP.

-

MAX.

-

UNIT

ms

RSL

t

-The power supply conditions of using power on reset circuit.

(Ta = -20 ~ +75°C)

P A R A M E T E R

The power supply rise time

The power OFF time

SYMBOL

CONDITION

MIN.

0.1

1

TYP.

-

MAX.

5

-

UNIT

ms

rDD

t

-

OFF

t

Since the internal initialization circuits will not operate normally unless the above conditions are met, in

such a case of initialized by instruction. (Refer to initialization by the instruction)

OFF

t

specifies the power off time in a short period off or cyclical on/off.

OFF

* t specifies the power off time in a short period off or cyclical ON/OFF.

NJU6475B

-Key Scan Sequence

P A R A M E T E R

SYMBOL MIN.

TYP.

66.7

44.4

0.36

-

MAX.

300

48

0.38

1.0

CONDITION UNIT

0

7

KDS

E/SCL-S to S Delay time

Key scan pulse width "H","L" level

Key scan time

t

-

Fig. 3

uS

mS

uS

KHz

KP

-

KS

-

KDR

KF

REQ output delay time

Key in check signal frequency

-

0.98

1.41

1.84

0

3

-The load of K to K is CL = 20 pF

DD

0.7V

DD

0.5V

DD

KEYCHECK

REQ

0.5V

KF

1 / t

DD

0.7V

DD

0.3V

KDR

t

KDR

t

IH1

SCL/E

V

KDS

t

0

S

1

S

2

S

3

S

4

S

5

S

KP

t

6

S

7

S

KS

t

Fig. 3 Key scan sequence

NJU6475B

-External clock input

P A R A M E T E R

SYMBOL

MIN.

125

45

-

MAX.

235

55

0.2

CONDITION UNIT

CP

External clock operating frequency

External clock duty

External clock rise time

External clock fall time

f

Fig. 4

KHz

%

uS

Duty

CPr

t

CPf

t

-

CP

Tf

K

I

K

T

Duty =

K

I

T + T

OSC1

DD

V -0.5

DD

0.5V

CP

Tf = 1/f

DD

V +0.5

CPf

t

CPr

t

Fig.4 External clock input

-The key scan circuit timing characteristics measurement cricurit

N J U 6 4 7 5 B

0

1~7

0

1~3

S (S )

K (K )

NOTE : SW Resistance is 0Ω

(measurement : only pattern wires)

CL=20pF

NJU6475B

LCD DRIVING WAVE FORM

NJU6475B

APPLICATION CIRCUIT (1)

12-Character 4-Line

(Terminal description, Mode A)

NJU6475B

APPLICATION CIRCUIT (2)

12-Character 4-Line

(Terminal description, Mode B)


型号：	NJU6475B
厂家：	NEW JAPAN RADIO
描述：	12-Character 4-Line Dot Matrix Low Power LCD Controller Driver with key Scan Function 12个字符4行点阵低功耗LCD控制器驱动程序与键扫描功能显示控制器微控制器和处理器外围集成电路驱动 CD
文件：	总45页 (文件大小：2369K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6475B [NJRC]

相关型号：

NJU6520

NJU6520CH

NJU6520CH-01

NJU6520H

NJU6533

NJU6533C

NJU6533FA2

NJU6533FG1

NJU6533KQ1

NJU6535

NJU6535FG1

NJU6535FH1