NJU6679_技术文档

NJU6679

PRELIMINARY

128-common x 132-segment

BIT MAP LCD DRIVER

GENERAL DESCRIPTION

PACKAGE OUTLINE

The NJU6679 is a bit map LCD driver to display graphics or charac-

ters. It contains 25,344 bits display data RAM, microprocessor inter-

face circuits, instruction decoder, 132-segment and 128-common driv-

ers.

The bit image display data is transferred to the display data RAM by

serial or 8-bit parallel interface.

The NJU6679 displays 128 x 132 dots graphics or 8-character 8-line

by 16 x 16 dots character.

NJU6679CL

It oscillates by built-in OSC circuit without any external components.

Furthermore, the NJU6679 features Partial Display Function which

creates up to 2 blocks of active display area and optimizes duty cycle

ratio. This function sets optimum boosted voltage by the combination

with both of programmable 6-time voltage booster circuit and 201-

step electrical variable resistor. As result, it reduces the operating cur-

rent.

The operating voltage from 2.4V to 3.6V and low operating current are

useful for small size battery operating items.

FEATURES

Direct Correspondence between Display Data RAM and LCD Pixel

Display Data RAM - 25,344 bits (1.5 times over than display size)

236 LCD Drivers - 128-common and 132-segment

Direct Microprocessor Interface for both of 68 and 80 type MPU

Serial Interface

Partial Display Function

(2 blocks of active display area and automatic duty cycle ratio selection)

Easy Vertical Scroll by the variable start line address and over size display data RAM

Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12 bias

Common Driver Order Assignment by mask option

Version

C0 to C127(Pin name)

NJU6679A Com0 to Com127

NJU6679B Com127 to Com0

Useful Instruction Set

Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set,

Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read,

All On/Off, Voltage Booster Circuits Multiple Select(Maximum 6-time), n-Line Inverse,

Read Modify Write, Power Saving, ADC Select, etc.

Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(6-time Maximum),

Regulator, Voltage Follower x 4

Precision Electrical Variable Resistance

Low Power Consumption

Operating Voltage

--- 2.4V to 3.6V

LCD Driving Voltage --- 6.0V to 18V

JUL.10.2000

Ver. 2.1

Package Outline

--- COF / TCP / Bumped Chip

C-MOS Technology

NJU6679

PAD LOCATION

C

46

C

47

DUMMY19

DUMMY18

DUMMY17

DUMMY16

DUMMY15

DUMMY14

DUMMY13

DUMMY12

V_DD

C

63

S₀

V₁

V₂

V₃

V₄

V₅

VR

V_DD

-

C1

C1 ⁺

-

C2

C2⁺

-

C3

C3⁺

-

C4

C4⁺

X

-

C5

C5⁺

V_OUT

V_SS

D₇

D₆

D₅

Y

D₄

D₃

D₂

D₁

D₀

RD

WR

A0

CS

OSC₂

OSC₁

T₁

T₂

V_SS

RES

SEL68

P/S

V_DD

DUMMY11

DUMMY10

DUMMY9

DUMMY8

DUMMY7

DUMMY6

DUMMY5

DUMMY4

DUMMY3

DUMMY2

DUMMY1

S₁₃₁

C₁₂₇

1

DUMMY0

C₁₁₁

C₁₁₀

Chip Center

Chip Size

Chip Thickness

Bump Size

Pad pitch

Bump Height

Bump Material

: X=0um,Y=0um

: X=10.31mm,Y=3.13mm

: 675um + 30um

: 45um x 83um

: 60um(Min)

: 15um TYP.

: Au

NJU6679

PAD No.

301

302

303

304

305

306

307

308

309

310

311

Terminal

C84

C83

C82

C81

C80

C⁷⁹

C78

C77

C76

C⁷⁵

C74

C73

C72

C⁷¹

C70

C69

C68

C67

C66

C65

C64

X= um

-4995

Y= um

-216

-276

-336

-396

-456

-516

-576

-636

-696

-756

-816

312

313

314

315

316

317

318

319

320

321

-876

-936

-996

-1056

-1116

-1176

-1236

-1296

-1356

-1416

NJU6679

BLOCK DIAGRAM

C

0

C

63

S

0

S

131

C

127

C₆₄

V_SS

V_DD

to V

5

C O M

S E G

D r i v e r

C O M

V

1

5

D r i v e r

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

S h i f t

Voltage

R e g i s t e r

COM SEG

Timing

Generator

D i s p l a y D a t a L a t c h

VR

T₁,T₂

Display Data RAM

192 x 132

Culumn Address Decoder

Culumn Address Counter

Display

Timing

Generator

Culumn Address Register

M u l t i p l e x e r

OSC1

OSC2

OSC.

Instruction Decoder

B F

B u s H o l d e r

S t a t u s

I n t e r n a l B u s

R e s e t

RES

M P U I n t e r f a c e

SEL68

RD

D₀to D₇(SI,SCL)

CS

WR

A0

P/S

NJU6679

TERMINAL DESCRIPTION

No.

Symbol I/O

F u n c t i o n

Power

VDD

1,40

5,22

VDD=+3V

VSS

GND VSS=0V

Power

39

38

37

36

35

V1

V2

V3

V4

V5

LCD Driving Voltage Supplying Terminal. When the internal voltage booster is

not used, supply each level of LCD driving voltage from outside with following

relation.

VDD>V1>V2>V3>V4>V5

When the internal power supply is on, the internal circuits generate and supply

following LCD bias voltage from V1 to V4 terminals.

Bias

V1

V2

V3

V4

1/4Bias

1/5Bias

1/6Bias

1/7Bias

1/8Bias

1/9Bias

1/10Bias

1/11Bias

1/12Bias

V5+3/4VLCD

V5+4/5VLCD

V5+5/6VLCD

V5+6/7VLCD

V5+7/8VLCD

V5+8/9VLCD

V5+2/4VLCD

V5+3/5VLCD

V5+4/6VLCD

V5+5/7VLCD

V5+6/8VLCD

V5+7/9VLCD

V5+2/4VLCD

V5+2/5VLCD

V5+2/6VLCD

V5+2/7VLCD

V5+2/8VLCD

V5+2/9VLCD

V5+1/4VLCD

V5+1/5VLCD

V5+1/6VLCD

V5+1/7VLCD

V5+1/8VLCD

V5+1/9VLCD

V5+9/10VLCD V5+8/10VLCD V5+2/10VLCD V5+1/10VLCD

V5+10/11VLCD V5+9/11VLCD V5+2/11VLCD V5+1/11VLCD

V5+11/12VLCD V5+10/12VLCD V5+2/12VLCD V5+1/12VLCD

(VLCD=VDD-V5)

33,32,

31,30,

29,28,

27,26,

25,24

C1⁺,C1^-

C2⁺,C2^-

C3⁺,C3^-

C4⁺,C4^-

C5⁺,C5^-

O

Step up capacitor connecting terminals.

Voltage booster circuit (Maximum 6-time)

23

VOUT

O

I

Step up voltage output terminal. Connect the step up capacitor between this

terminal and VSS.

34

VR

Voltage adjust terminal. V5 level is adjusted by external bleeder resistance

connecting between VDD and V5 terminal.

7

6

T1

T2

I

LCD bias voltage control terminals. ( *:Don't Care)

V o lta g e

T 1

T 2

V o lta g e A d j.

V /F C ir.

b o o s te r C ir.

L

H

*

L

A v a ila b le

N o t A v a il.

A v a ila b le

N o t A v a il.

H

14 to 21

11

D0 to

D7

I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.

P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input

terminal. Data from SI is loaded at the rising edge of SCL and

latched as the parallel data at 8th rising edge of SCL.

(SI)

(SCL)

A0

I

Connect to the Address bus of MPU. The data on the D 0 to D7 is

distinguished between Display data and Instruction by status of A0.

A0

H

L

Distin. Display Data Instruction

4

RES

CS

I

Reset terminal. When the RES terminal goes to "L", the initialization is

performed. Reset operation is executing during "L" state of RES.

10

Chip select terminal. Data Input/Output are available during CS ="L".

NJU6679

No

Symbol I/O

F u n c t i o n

13

12

RD(E)

I

RD signal of 80 type MPU input terminal. Active "L"

During this signal is "L" , D0 to D7 terminals are output.

Enable signal of 68 type MPU input terminal. Active "H"

WR(R-

W)

I

Connect to the 80 type MPU WR signal. Actie "L".

The data on the data bus input syncronizing the rise edge of this signal.

The read/write control signal of 68 type MPU input terminal.

R/W

H

L

State

Read

Write

3

2

SEL68

P/S

I

MPU interface type selection terminal.

SEL68

State

H

L

68 Type

80 Type

serial or parallel interface selection terminal.

Chip Select Data/Command

Read/Write

serial Clock

P/S

"H"

"L"

Data

D0 to D7

SI(D7)

CS

A

RD,WR

-

A0

Write Only SCL(D6)

RAM data and status read operation do not work in mode of

the serial interface.

In case of the serial interface (P/S="L"),RD and WR must be fixed

"H" or "L", and D0 to D5 are high impedance.

8

9

OSC1

OSC2

I

System clock input terminal for Maker testing.(This terminal should be Open)

For external clock operation, the clock shoud be input to OSC1 terminal.

41 to 104 C0 to

C63

O

LCD driving signal output terminals.

Segmet output terminals:S 0 to S131

Common output terminals:C 0 to C127

Segment output terminal

The following output voltages are selected by the combination of FR and data

in the RAM.(non of the n-line inverse functions)

Output Voltage

RAM

Data

FR

Normal

Reverse

V2

105 to 236

S0

O

H

L

VDD

V5

toS131

H

L

V3

H

L

V2

VDD

V5

V3

Common output terminal

The following output voltages are selected by the combination of FR and status

of common.

237 to 300

C64 to

C127

Scan data

H

FR

H

L

Output Voltage

V5

VDD

V1

H

L

V4

NJU6679

Functional Description

(1) Description for each blocks

(1-1) Busy Flag (BF)

While the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the status

read are inhibited .

The busy flag goes to “1” from D7 terminal when status read instruction is executed.

When enough cycle time over than tCYC indicated in “ BUS TIMING CHARACTERISTICS” is ensured, no

need to check the busy flag for reduction of the MPU loads.

(1-2)Display Start Line Register

The Display start Line Register is a pointer register which indicates the address in the Display Data RAM

corresponding with COM0(normally it display the top line in the LCD Panel). This register also operates for

vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the

display start address of the Display Data RAM represented in 8-bit to this register.

(1-3) Line Counter

The Line Counter generates the line address of display data RAM by the count up operation synchronizing the

common cycle after the reset operation at the status change of internal FR signal.

(1-4) Column Address Counter

The column address counter is 8-bit pre-settable counter addressing the column address of display data RAM

as shown in Fig. 1. It is incremented (+1) up to (84)H by the Display Data Read/Write instruction execution.

It stops the count up operation at (84)H, and it does not count up non existing address area over than (84)H by

the count lock function. This count lock is released by new column address set.

The column address counter is independent of the Page Register.

By the Address Inverse Instruction, the column address decoder inverse the column address of Display Data

RAM corresponding to the Segment Driver.

(1-5) Page Register

The page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accesses

the data with the page change, the page address set instruction is required.

(1-6) Display Data RAM

Display Data RAM is the bit map RAM consisting of 25,344 bits to memorize the display data corresponding to

each pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCD

panel and controls the display by following bit data.

When Normal Display : On="1" , Off="0"

When Inverse Display : On="0" , Off="1"

The Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these data

are set into the Display Data Latch.

The access operation from MPU to the display data RAM and the data output from the display data RAM are

so controlled to operate independently that the data rewriting does not influence with any malfunctions to the

display.The relation between column address and segment output can inverse by the Address Inverse Instruc-

tion ADC as shown in Fig.1.

(1-7) Common Driver Assignment

The scanning order can be assigned by mask option as shown on Table 1.

Table 1

C O M O utputs Terminals

62

C 0

125

258

321

P A D N o .

P in na m e

Ver.A

C 63

C O M 63

C O M 64

C 127

C 64

C O M 64

C O M 63

C O M 0

C O M 127

C O M 0

Ver.B

C O M 127

NJU6679

F o r exam p le the

Line

P a g e A d d ress D A TA

D ispla y P a tte rn

D ispla y sta rt line

Address

is 10H

D 0

D 1

D 2

0 0

0 1

0 2

0 3

0 4

0 5

0 6

0 7

0 8

0 9

0 A

0 B

0C

0D

0 E

D 4 ,D 3 ,D 2 ,D 1 ,D 0

D 3

P e g e 0

D 4

D 5

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

(0,0,0,0,0)

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(0,0,0,0,1)

P e g e 1

0 F

1 0

11

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

C n Out

C 0

C 1

C 2

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(0,0,0,1,0)

C 3

P e g e 2

C 4

C 5

C 6

C 7

C 8

C 9

:

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

D 0

D 1

8 6

8 7

8 8

8 9

8 A

8 B

8C

8D

8 E

8 F

9 0

9 1

9 2

9 3

9 4

9 5

9 6

9 7

9 8

9 9

C 118

C 119

C 1 2 0

C 1 2 1

C 1 2 2

C 1 2 3

C 1 2 4

C 1 2 5

C 1 2 6

C 1 2 7

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(1,0,0,0,1)

P e g e 1 7

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(1,0,0,1,0)

P e g e 1 8

:

D 6

D 7

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

B 6

B 7

B 8

B 9

B A

B B

B C

B D

B E

B F

D 4 ,D 3 ,D 2 ,D 1 ,D 0

(1,0,1,1,1)

P e g e 2 3

|

C o lum n

A d d re-

ss

7 A 7 B 7 C 7 D 7 E 7 F 8 0 8 1 8 2 8 3

0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0

0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9

D 0 ="0"

D 0 ="1"

A

D

C

7 F 7 E 7 D 7 C 7 B 7 A

8 3 8 2 8 1 8 0

1 2 2

1 2 3

1 2 4

1 2 5

1 2 6

1 2 7

1 2 8

1 2 9

1 3 0

1 3 1

S e g m e n t O utput

0

1

2

3

4

5

6

7

8

9

Fig.1 Correspondence with Display Data RAM Address

NJU6679

(1-8) Reset Circuit

Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.

Initialization

1

2

3

Display Off

Normal Display (Non-inverse display)

ADC Select : Normal (ADC Instruction D0 =”0”)

Read Modify Write Mode Off

4

5

6

Internal Power supply (Voltage Booster) circuits Off

Static Drive Off

7

Driver Output Off

8

Clear the serial interface register

9

Set the address(00)H to the Column Address Counter

Set the 1st Line in the Display Start Line Register.page (00)H to the Page Address Register

Set the page “0” to the Page Address Register

Set the EVR register to (FF)H

Set the All display(1/128 duty)

Set the Bias select(1/12 Bias)

10

11

12

13

14

15

16

Set the 6-Time Voltage Booster

Set the n line turn over register (0)H

The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time

with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L"

level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation

goes to normal.

When the internal LCD power supply is not used, the external LCD power supply into the NJU6679 must be

turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the

oscillation circuit and the output terminal conditions (D0 to D7) are not influenced. The initialization must be

performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset

Instruction performs the initialization procedures from No.9 to No.16 as shown in above.

Note) The noise into the RES terminal should be eliminated to avoid the error on the application with the

careful design.

(1-9) LCD Driving

(a) LCD Driving Circuits

LCD driving circuits are consisted of 260 multiplexers which operate as 132 Segment drivers and 128 Com-

mon drivers. 128 Common drivers with the shift register scan the common display signal. The combination of

the Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave

form is shown in the Fig. 7.

(b) Display Data Latch Circuits

Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common

cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse

ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display

Data RAM is not changed.

(c) Line Counter and Latch signal of Latch Circuits

The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock

(CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display

data are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving

circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by

the MPU.

(d) Display Timing Generator

Display Timing Generator generates the timing signal for the display system by combination of the master

clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate

LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.

NJU6679

(e)Common Timing Generation

The common timing is generated by display clock.

-Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0)

127 128 1

2

3

4

5

6

7

8

125 126 127 128 1

2

3

4

5

CL

FR

V

DD

V

1

C0

C1

V

4

V

5

V

DD

V1

V

4

V

5

RAM DATA

Sn

V

2

DD

V

3

V

5

Fig.2

-Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6)

127 128 1

2

3

4

5

6

7

8

125 126 127 128 1

2

3

4

5

CL

FR

V

DD

V

1

C0

C1

V

4

V

5

V

DD

V

1

V

4

V

5

RAM DATA

Sn

V

2

DD

V

3

V

5

Fig.3

NJU6679

(f) Oscillation Circuit

The Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generates

clocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency is

divided as shown in below for display clock CL.

-The relation between duty and divide

1/104 1/112 1/120 1/128

1/8 1/16 1/24 1/32 1/40 1/48 1/56 1/64 1/72 1/80 1/88 1/96

Duty

Divide 1/64 1/32 1/21 1/16 1/12 1/10 1/9 1/8 1/7 1/6 1/5

1/4

(g) Power Supply Circuit

Internal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power Supply

Circuit consists of Voltage Booster (6-Time maximum) Circuits, Regulator Circuits, and Voltage Followers.

The internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large size

LCD panel application. If the contrast is not good in the large size LCD panel application, please supply the

external.

The suitable values of the capacitors connecting to the V1 to V5 terminals and the voltage booster circuit, and

the feedback resistors for V5 operational amplifier depend on the LCD panel. And the power consumption with

the LCD panel is depending on the display pattern. Please evaluate with actual LCD module.

The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction.

When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator

circuits, voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4, and V5 for the

LCD should be supplied from outside, terminals C1⁺, C1^-, C2⁺, C2^-,C3⁺, C3^-, C4⁺, C4^-, C5⁺, C5^-and VR should

be open. The status of internal power supply is selected by T1 and T2 terminal. Furthermore the external

power supply operates with some of internal power supply function.

Voltage

Booster

C1+,C1- to

C5+,C5-

T1

T2

Voltage Adj.

Buffer(V/F) Ext.Pow Supply

VR Term.

L

L/H

L

ON

OFF

ON

-

H

VOUT

Open

H

OFF

V5,VOUT

Open

When (T1, T2)=(H, L), C1⁺, C1^-, C2⁺, C2^-,C3⁺, C3^-, C4⁺, C4^-, C5⁺, C5^-terminals for voltage booster circuits are

open because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal

should be supplied from outside.

When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster

circuits and Voltage adjust circuits do not operate.

NJU6679

(2) Instruction

The NJU6679 distinguishes the signal on the data bus by combination of A0, RD and WR. The decode of the

instruction and execution performs depending on the internal timing only neither the external clock. In case of

serial interface, the data input as MSB first serially.

The Table. 4 shows the instruction codes of the NJU6679.

(*:Don't Care)

Table 4. Instruction Code

C o d e

In s truc tio n

D e s c rip tio n

A 0 R D W R D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

(1 )

(2 )

D i s p la y O N /O F F

0

1

0

1

0

1

0

1

0

1

L C D D i s p la y O N /O F F

0 :O F F 1 :O N

D i s p la y S ta rt L ine S e t

H ig h O r d e r 4 b i ts

0

1

0

1

0

1

H ig h O r d e r

A d d re s s

D e te rm ine the D i s p la y L ine o f

R A M to the C O M 0 .

(S e t the H ig h e r o rd e r 4 b its )

D i s p la y S ta rt L ine S e t

L o w e r O rd e r 4 b its

0

1

0

1

0

L o w e r O rd e r

A d d re s s

D e te rm ine the D i s p la y L ine o f

R A M to the C O M 0 .

(S e t the L o w e r o r d e r 4 b i ts )

H i.

(3 )

(4 )

P a g e A d d re s s S e t

H ig h O r d e r 1 b i ts

*

S e t th e H i g h e r o r d e r 1 b i t p a g e

o f D D R A M to the P a g e

A d d re s s R e g is te r

P a g e A d d re s s S e t

L o w e r O rd e r 4 b its

L o w e r O rd e r

P a g e A d d re s s o f D D R A M to the P a g e

A d d re s s R e g is te r

S e t th e L o w e r o rd e r 4 b it p a g e

C o lum n A d d re s s S e t

H ig h O r d e r 4 b i ts

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

H ig h O r d e r

C o lum n A d d .

S e t th e H i g h e r o r d e r 4 b i t s

C o lum n A d d re s s to the R e g .

C o lum n A d d re s s S e t

L o w e r O rd e r 4 b its

L o w e r O rd e r

C o lum n A d d .

S e t th e L o w e r o rd e r 4 b its

C o lum n A d d re s s to the R e g .

(5 )

(6 )

(7 )

(8 )

S ta tus R e a d

S ta tus

0

R e a d o ut the inte rna l S ta tus

W rite D i s p la y D a ta

R e a d D i s p la y D a ta

W rite D a ta

R e a d D a ta

W rite the d a ta into the D i s p la y

D a ta R A M

R e a d the d a ta fro m the D i s p la y

D a ta R A M

N o rm a l o r Inve rse o f

O N /O F F S e t

1

0

1

0

1

0

1

Inve rse the O N a n d O F F

D i s p la y

0 :N o rm a l 1 :Inve rs e

(9 )

W h o le D i s p la y O N

/N o rm a l D i s p la y

0

1

0

1

0

1

0

1

0

1

0

1

W h o le D i s p la y Turns O N

0 :N o rm a l 1 :W h o le D i s p . O N

(1 0 ) S u b i n s truc tio n ta b le

m o d e

0

S e t th e S u b i n s truc tio n ta b le .

(11 ) P a rtia l D i s p la y

1 s t B lo c k , S e t

0

1

0

1

0

S ta rt d i s p la y

unit

S e t th e S ta rt d i s p la y unit o f 1 s t

B lo c k .

S ta rt d i s p la y unit

1 s t B lo c k ,

S e t The n u m b e r o f

d i s p la y units

num b e r o f d is p la y

units

S e t th e n u m b e r o f d i s p la y units

o f 1 s t B lo c k .

2 n d B lo c k , S e t

0

1

0

1

0

1

0

S ta rt d i s p la y

unit

S e t th e S ta rt d i s p la y unit o f 2 n d

B lo c k .

S ta rt d i s p la y unit

2 n d B lo c k ,

S e t The n u m b e r o f

d i s p la y units

num b e r o f d is p la y

units

S e t th e n u m b e r o f d i s p la y units

o f 2 n d B lo c k .

P a rtia l d i s p la y o n

0

1

0

1

0

*

0

It c o m e s o ff th e m o d e to s e t

a n d a d is p la y is e xe c u te d .

(1 2 ) n-line Inve rse D rive

S e t

R e g i s te r S e t

H ig h e r o rd e r 2 b its

0

1

0

1

0

1

0

1

*

hig h e r S e t th e n u m b e r o f inve rse d rive

o rd e r

lin e .

R e g i s te r S e t

L o w e r o rd e r 4 b its

L o w e r o rd e r

S e t th e n u m b e r o f inve rse d rive

lin e .

n-line Inve rse D rive

S e t is e xe c u te d .

0

T h e e xe c utio n o f th e line inve r s e

d rive .

(1 3 ) E V R R e g i s te r S e t

E V R R e g i s te r S e t

H ig h e r o rd e r 4 b its

0

1

0

1

0

1

E V R D a ta

H ig h e r o rd e r

S e t th e V 5 o u tp u t le v e l to the

E V R re g i s te r. (H i g h e r o r d e r 4

b its )

E V R R e g i s te r S e t

L o w e r o rd e r 4 b its

E V R D a ta

L o w e r o rd e r

S e t th e V 5 o u tp u t le v e l to the

E V R re g i s te r. (L o w e r o rd e r 4

b its )

E V R R e g i s te r S e t

i s e xe c ute d .

0

1

0

1

0

1

0

1

0

1

T h e e xe c utio n o f th e E V R .

(1 4 ) E n d o f s u b instruc tio n

ta b le m o d e

It e n d s the s e ttin g o f s u b

ins truc tio n ta b le .

NJU6679

(*:Don't Care)

Code

Instruction

Description

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

A0 RD W R

(15) Bias Select

0

1

0

1

0

1

Bias

Select the bias

(9 Patterns)

Boost

Multiple

(16) Voltage Booster

C ircuits Multiple

Select

0

1

0

1

0

Set the Booster circuits

(2 to 6 times)

(17) Read Modify W rite

/End

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Read Modify W rite mode

D 0=0:On D0=1:E nd

(18) Reset

0

Initialize the internal C ircuits

(19) Internal Power Supply

ON/OFF

0

1

0:Int. Power Supply OFF

1:Int. Power Supply ON

(20) LCD Driving Voltage

Set

0

1

Set LC D D riving Voltage after

the internal (external) power

supply is turned on

(21) Power Save

(Dual Command)

Set the Power Save Mode

(LC D D isplay OFF

+Whole Display Turns ON)

(22) ADC Select

0

1

0

1

0

1

0

1

Set the DD RAM vs Segment

D 0=0:Normal D 0=1:Inverse

NJU6679

(3) Explanation of Instruction Code

(3-1) Display On/Off

This instruction executes whole display On/Off without relationship of the data in the Display Data RAM and

internal conditions.

R/W

A0

0

RD

1

W R

D7

1

D6

0

D5

1

D4

0

D3

1

D2

1

D1

1

D0

D

0

D 0:Display Off

1:Display On

(3-2) Display Start Line

This instruction sets the line address of Display Data RAM corresponding the COM0 terminal (the highest

position line of display in normal application). The display area is fixed automatically by number of display line

which corresponds the display duty ratio from the pointed line address as the start line. This instruction realizes

the vertical smooth scroll with extredisplay RAM or the page address change by dynamic line addressing. In

this time, the contents of RAM are not changed.

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

0

D4

1

D3

A7

D2

A6

D1

A5

D0

A4

0

1

0

1

0

A3

A2

A1

A0

A7

0

A6

A5

A4

0

A3

0

A2

0

A1

0

A0

Line Address(HEX)

0

1

0

1

0

:

1

0

1

BF

(3-3) Page Address Set

When MPU accesses the Display Data RAM, the page address must be selected before the data writing. The

access to the Display Data RAM is available by the page and column address set (Refer the Fig. 1). The page

address change does not influence with the display.

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

0

D4

0

D3

*

D2

*

D1

*

D0

A4

0

1

0

1

0

A3

A2

A1

A0

(*:Don't Care)

A4

A3

A2

A1

0

A0

0

Page

0

1

0

1

:

1

0

1

23

NJU6679

(3-4) Column Address

When MPU accesses the Display Data RAM, the page address (refer(3-3) ) and column address set are

required before the data writing. The column address set requires twice address set which are higher order 4

bits address set and lower order 4 bits. When the MPU accesses the Display Data RAM sequentially, the

column address is increase one by one automatically, therefore, the MPU can access only the data sequen-

tially without address set.

After writing 1page data, page address setting is required due to page address doesn't increase automatically.

The increment of the column address is stopped at the address of (83)H automatically, and the page address is

not changed even if the column address increase to (83)H and stop. In this time the page address is not

changed.

R/W

A0

0

RD

1

W R

D7

0

D6

0

D5

0

D4

1

D3

A7

D2

A6

D1

A5

D0

A4

0

Higher Order

Lower Order

0

1

0

A3

A2

A1

A0

A7

A6

A5

0

A4

0

A3

A2

0

A1

A0

Column Address(HEX)

0

:

0

1

0

1

:

0

:

1

0

1

83

(3-5) Status Read

This instruction reads out the internal status of "BUSY", “ADC", "ON/OFF" and "RESET".

R/W

A0

0

RD

0

WR

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

ON/OFF

RESET

1

BUSY ADC

BUSY : BUSY=1 indicate the operating or the Reset cycle.

The instruction can be input after the BUSY status change to "0".

ADC

: Indicate the output correspondence of column (segment) address and segment driver.

0 :Counterclockwise Output (Inverse) Column Address 131-n <---> Segment Driver n

1 :Clockwise Output

(Normal) Column Address n

<---> Segment Driver n

(Note) The data "0=Inverse" and "1=Normal" of ADC is inverted with the ADC select

Instruction of "1=Inverse" and "0=Normal".

ON/OFF : Indicate the whole display On/Off status.

0 : Whole Display "On

1 : Whole Display "Off"

(Note) The data "0=On" and "1=Off" of Display On/Off status read out is inverted with the

Display On/Off instruction data of "1=On" and "0=Off".

RESET : Indicate the initializing by RES signal or reset instruction.

0 :

-

1 : Initialization Period

NJU6679

(3-6) Write Display Data

This instruction writes the 8-bit data on the data bus into the Display Data RAM. The column address in-

creases "1" automatically after data writing, therefore, the MPU can write the 8-bit data into the Display Data

RAM continuously without any address setting after the start address setting.

R/W

A0

1

RD

1

W R

D7

D6

D5

D4

D3

D2

D1

D0

0

WRITE DATA

(3-7) Read Display Data

This instruction reads out the 8-bit data from Display Data RAM addressed by the column and page address.

The column address increase "1" automatically after data reading out, therefore, the MPU can read out the 8-

bit data from the Display Data RAM without any address setting after the start address setting. One time of

dummy read must operate after column address set as the explanation in "(5-4) Access to the Display Data

RAM and Internal Register". In the serial interface mode, the display data is not read out.

R/W

A0

1

RD

0

W R

D7

D6

D5

D4

D3

D2

D1

D0

1

READ DATA

(3-8) Normal or Inverse On/Off Set

This instruction changes the condition of display turn on and off as normal or inverse. The contents of Display

Data RAM is not changed by this instruction execution.

R/W

A0

0

RD

1

W R

D7

1

D6

0

D5

1

D4

0

D3

0

D2

1

D1

1

D0

D

0

D 0 : Normal

1 : Inverse

RAM data "1" correspond to "On"

RAM data "0" correspond to "On"

(3-9) Whole Display On

This instruction turns on the all pixels independent of the contents of Display Data RAM. In this time, the

contents of Display Data RAM is not changed and kept. This instruction takes precedence over the "Normal or

Inverse On/Off Set Instruction".

R/W

A0

0

RD

1

W R

D7

1

D6

0

D5

1

D4

0

D3

0

D2

1

D1

0

D0

D

0

D 0 : Normal Display

1 : Whole Display turn on

When Whole Display On Instruction is executed in the Display Off status, the internal circuits go

to the power save mode (refer to the (s) Power Save).

NJU6679

(3-10) Sub Instruction table mode

This instruction switches the instruction table from the main to the sub. The sub instruction table contains

instructions of partial display, n-line inverse drive set and EVR register set as mentioned in (11), (12) and (13).

The instruction of sub instruction table mode must be executed before above 3 sub instructions execution. The

instruction of end of sub instruction table mode (14) switches the instruction table from the sub to the main. If

any main instructions are written in the sub instruction mode, the NJU6679 will malfunction.

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

0

D0

0

-Set sub Instruction table flow is shown below:

Sub Instruction table

mode

Switches to Sub instruction table mode.

Switches to Main instruction mode.

Set sub instructions.

End of Sub Instruction

table mode.

NJU6679

(3-11) Partial Display

This instruction divides the active display area in a LCD panel to 16 units consisting of 8 commons per unit

and displays one or two blocks of active display area consisting of a unit or more. In the partial display mode,

the display duty ratio is set automatically according to the number of unit in a block or two.

Therefore, the partial display function realizes to go down the LCD driving voltage according to the display

duty ratio. As a result, the operation current of display system is much saved against the full display mode.

The display units

UNIT

0

1

2

3

4

5

6

7

(8 commons)

128-common

8

9

10

11

12

13

14

15

(8 commons)

132-segment

Partial display instruction

The partial display operates by the combination of instructions which area unit number of start position start

unit block in the display area and a number of display unit from start position to end as a block. The number of

block is set up to two.

R/W

A0

0

RD

1

W R

D7

0

D6

0

D5

0

D4

0

D3

D

D2

D

D1

D

D0

D

Start display

unit

0

1^stBlock

2^ndBlock

The number of

display units

0

1

0

1

0

1

0

1

D

0

D

Start display

unit

The number of

display units

D

After execution of the next instruction, the display mode is changed to the

partial display and the duty is changed automatically.

Partial display

on

0

1

0

1

0

D :unit number (Hex.)

Incase of full display (1/128 duty), all of units on the display are selected when the first

start unit is set to “0” (0,0,0,0) and the second number of display unit is set to “16”

(1,0,0,0,0). In this time, the second block settings are ignored.

Note)

In case of only one block display, the second block settings are ignored when the

second start unit is set to “0” (0,0,0,0) and the second display unit number is set to “0”

(0,0,0,0,0).

Keep the order of partial display instruction sequence.

Do not set over “UNIT 15” the display data in DD RAM are assigned continuously from

page 0 for all of display block, even if non-display area is existed between the first

block and the second.

NJU6679

The example of partial display setting

UNIT 0

1^stBlock

UNIT 1

UNIT 2

UNIT 3

UNIT 4

UNIT 5

UNIT 6

UNIT 7

2^ndBlock

UNIT 8

UNIT 9

UNIT 10

UNIT 11

UNIT 12

UNIT 13

active display-block

UNIT 14

UNIT 15

The above partial display condition is set as follows:

1)Set sub instruction mode

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

D0

0

Set sub instruction

mode.

0

2)Set partial display conditions

R/W

A0

0

RD

1

W R

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

1^stBlock, Set start

display unit to ”0”

0

1^stBlock, Set the number

of display units to ”2”

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2^ndBlock, Set start

display unit to ”4”

2^ndBlock, Set the number

of display units to ”5”

Partial display on.

In this case, 1/56 duty. (Duty=1/(number of display units x 8))

3)End sub instruction mode

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

0

D0

1

End sub instruction

mode. Back to main

instruction mode.

0

Although the partial display instruction changes duty cycle ratio automatically and display area, LCD driving

voltage, Bias and others are not changed. Therefore, the instruction of LCD driving voltage “OFF” (D=0) must

be set before partial display operation, and the other instructions such as the n-line inverse drive set, EVR

register set, bias select and voltage booster select should be set for optimum display-contrast. The “End of sub

instruction mode” is required before these instructions in order to prevent momentary flickering.

NJU6679

-Set Partial Display flow is shown below:

Internal Power Supply OFF

Sub Instruction Table Mode

Partial Display

n-line Inverse Drive Set

EVR Register Set

End Sub Instruction Table

Mode

Bias Select

Voltage Booster Times Select

Wait Time

Internal Power Supply ON

(3-12) n-line Inverse Drive Mode

This instruction sets a line number for inversion of LCD driving signal levels between “1” and “0”. It reduces

the stripe shadow(crosstalk) and stabilizes display quality. The n-line inverse number is set according to the

result of actual LCD panel display.

The instructions must be input in order of followings. These instructions are sub instruction sets and must be

set after (3-10)Sub instruction table mode.

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

0

D4

1

D3

*

D2

*

D1

A5

D0

A4

Higher order

0

1

0

1

0

A3

A2

A1

A0

Low order

(*:Don't Care)

A5

A4

A3

A2

0

A1

0

A0

0

Inverse line

0

-

0

1

2

:

1

64

The actual operation starts after following instruction.

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

0

D0

0

NJU6679

(3-13) EVR Register Set

This instruction controls voltage adjustment circuits of internal LCD power supply and changes LCD driving

voltage “V5”. Finally, it adjusts the contrast of LCD display. By setting a data into EVR register, V5 output

voltage selects one condition out of 201-voltage conditions. The range of V5 voltage is adjusted by setting

external resistors as mentioned in "(4)(b) Voltage Adjust Circuits".

This instruction is sub instruction and it must be set after (3-10) Sub instruction table mode.

R/W

A0

0

RD

1

W R

D7

1

D6

0

D5

0

D4

0

D3

A7

D2

A6

D1

A5

D0

A4

0

1

0

1

0

1

A3

A2

A1

A0

A7

0

A6

0

A5

1

A4

1

A3

0

A2

1

A1

A0

VLCD

1

Low

:

1

High

VLCD=VDD-V5

When EVR doesn't use, set the EVR register to (1,1,1,1,1,1,1,1).

The actual operation starts after following instruction.

R/W

A0

0

RD

1

W R

D7

1

D6

0

D5

1

D4

0

D3

0

D2

0

D1

0

D0

0

(3-14) End of Sub instruction table mode

"End of sub instruction table mode" instruction switches instruction table from sub to main.

(11)Partial display, (12)n-line inverse drive mode, and (13)EVR are sub instruction sets on the sub instruction

table. The instruction of “END of sub instruction mode” must be set after these sub instruction sets. The

NJU6678 may occur incorrect operation if any main instructions on the main instruction table are input in mode

of sub instruction table.

R/W

A0

0

RD

1

W R

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

0

D0

1

0

NJU6679

(3-15) Bias Select

This instruction decides the value of LCD driving voltage bias ratio.

Especially, the bias shuld be selected for display quality in partial mode.

R/W

A0

RD

W R

D 7

D 6

D 5

D 4

D 3

D 2

A 2

D 1

A 1

D 0

A 0

(*:Don't Care)

0

1

0

1

0

1

A 3

A3

A2

0

1

*

A1

A0

0

1

0

1

0

1

0

1

*

Bias

1/4

0

1

0

1

0

1

*

1/5

1/6

1/7

1/8

1/9

1/10

1/11

1/12

(3-16) Voltage Booster Circuit Multiple Select

This instruction Selects a voltage boost time.

The multiple must be selected the voltage boost times according to the maximum boost times by the external

capacitors connections or less. Especially, the multiple should be selected for display quality and saving

operation current in partial display mode.

R/W

A0

0

RD

1

W R

D 7

0

D 6

0

D 5

1

D 4

1

D 3

0

D 2

A 2

D 1

A 1

D 0

A 0

0

Commands

Booster Multiple

6-Time External 5-Time External 4-Time External 3-Time External 2-Time External

A2

A1

A0

capacitors

connections

0

1

0

1

*

0

1

0

1

*

2-Time

3-Time

4-Time

5-Time

6-Time

2-Time

3-Time

4-Time

5-Time

2-Time

3-Time

4-Time

2-Time

3-Time

2-Time

NJU6679

(3-17) Read Modify Write/End

This instruction sets the Read Modify Write Mode for the column address increment control. In mode of the

Read Modify Write, the column address increases "1" automatically when the Display Data Write Instruction is

executed, but the address does not change when the Display Data Read Instruction is executed. This status is

continued until End instruction execution. When the End instruction (D=1) is input, the column address goes

back to the start address before the Read Modify Write instruction input. This function reduces the load of

MPU for repeating the display data change in the fixed area (ex. cursor blink).

D=”1” to release the Read Modify Write mode and the column address back to the address where the read

modify write mode setting.

R/W

A0

0

RD

1

W R

D7

1

D6

1

D5

1

D4

0

D3

0

D2

0

D1

0

D0

D

0

D 0 : Read Modify Write On

1 : End

Note) In mode of the Read Modify Write, any instructions except for Column Address Set can

execute.

- Sequence of cursor blink display

Page Address Set

Set to the Start

Address of Cursor

Display

Column Address Set

Start the

Read Modify Write

Dummy Read

Data Read

Read the Data as dummy

Data inverse by MPU

Data Write

Dummy Read

Data Read

Data Write

End the

Read Modify Write

End

NO

Finish?

YES

NJU6679

(3-18) Reset

This instruction executes the following initialization.

Initialization

(1) Set the Address (00)H into the Column Address Counter.

(2) Set the Address (00)H into the Display Start Line Register.

(3) Set the page "0" into the Page Address Register.

(4) Set 0 to the EVR Register to (FF)H.

(5) Set the All display(1/128 duty)

(6) Set the Bias select(1/12 Bias)

(7) Set the 6-Time Voltage Booster.

(8) Set the n-line inverse register (0)H

In this time, the Display Data RAM is not influenced.

R/W

A0

0

RD

1

W R

D7

1

D6

1

D5

1

D4

0

D3

0

D2

0

D1

1

D0

0

The reset signal input to the RES terminal (hardware reset) must be input for the power on initialization. Reset

instruction does not perform completely in stead of hardware reset using the RES terminal.

(3-19) Internal Power Supply ON/OFF

This instruction set the condition of internal Power Supply On/Off. Voltage Booster circuits, Voltage Regulator

and Voltage Follower operate at On. To operate the voltage booster circuits, the oscillation circuits must be

operating.

R/W

A0

0

RD

1

W R

D7

0

D6

0

D5

1

D4

0

D3

0

D2

0

D1

0

D0

D

0

D 0 : Internal Power Supply Off

1 : Internal Power Supply On

The internal Power Supply must be Off when external power supply using.

*1 The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer

capacitors, VDD and VLCD.

Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the

(4)(d) Fig.4)

NJU6679

(3-20) LCD Driving Voltage Set

This instruction controls LCD driving waveform output through the COM/SEG terminals.

R/W

A0

0

RD

1

W R

D7

0

D6

0

D5

1

D4

0

D3

0

D2

0

D1

1

D0

0

D

D 0 : LCD driving waveform output Off

1 : LCD driving waveform output On

The NJU6679 contains low power LCD driving voltage generator circuit reducing own operation current.

Therefore, it requires the following sequence procedures at power on for the power source stabilized operation.

- LCD driving power supply ON/OFF sequences

The following sequences are required when the power supply is turned On/Off.

When the power supply is turned on again after the turn off (by the power save instruction), the power save

release sequence ((3-21) Power Save) is required.

Turn ON sequence

Turn OFF sequence

Display OFF

Output Assign. Register Set

EVR Register Set

Whole Display ON

Internal Power Supply OFF

or

Internal Power Supply ON

or

External Power Supply OFF

External Power supply ON

LCD Driving Voltage

Set to OFF

(Wait Time) *1

LCD Driving Voltage

Set to ON

*1 The wait time depends on the C1 to C9, COUT capacitors (refer (4) (d)Fig.4), VDD and VLCD voltage.

Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the

following graph.)

The wait time [Typical performance]

100

80

60

40

T.B.D.

20

Cout=1 to 4.7[uF]

0

0.2

0.4

0.6

0.8

1

1.2

C3 to C7[uF]

VDD=2.7V,VLCD=7V,Ta=25C

NJU6679

(3-21) Power Save(Dual Command)

When both of Display Off and Whole Display On are executed, the internal circuits go to the power save mode

and the operating current is reduced as some as the stand by current.

The internal status in the Power Save Mode is shown in follows;

(1) Stop the Oscillation Circuits and Internal Power Supply Circuits operation.

(2) Stop the LCD driving. Segment and Common drivers output VDD level.

(3) Keep the display data and operating mode just before the power save mode.

(4) All of LCD driving bias voltage fix to the VDD level.

The power save and its release perform according to the following sequences.

Power Save Sequence

Power Save Release Sequence

Display OFF

Normal Display

Display ON

(Whole Display OFF)

Whole Display ON

LCD Driving Voltage

Set to OFF

(Wait Time)

LCD Driving Voltage

Set to ON

*1 In the power save sequence, the power save mode is started after the second instruction "whole Display

ON".

*2 In the power save release sequence, the power save mode is released after the Normal Display instruction

(Whole display OFF).

The instruction of display ON is input at any timing after the instruction of normal display in power save

release sequence.

*3 Until "LCD driving voltage set to ON" execution, NJU6679 operating current is higher than usual state and

all COM/SEG terminals output VDD level continuously.

*4 In case of the external power supply for LCD driving, it should be turned off and made condition like as

unconnection or connected to VDD before the power save mode or at the same time. In this time, VOUT

terminal should be made condition like as disconnection or connected to the lowest voltage of the system

(V5 level from the external power supply).

(3-22) ADC Select

This instruction set the correspondence of column address in the Display Data RAM and segment driver

output. (See Fig. 1.) By this instruction, the order of segment output can be changed by the software, and no

restriction of the LSI placement against the LCD panel.

R/W

A0

0

RD

1

W R

D7

1

D6

0

D5

1

D4

0

D3

0

D2

0

D1

0

D0

D

0

D 0 : Clockwise Output (Normal)

1 : Counterclockwise Output (Inverse)

NJU6679

(4) Internal Power Supply

(a) 6-time voltage booster circuits

6-time voltage booster circuits connecting five capacitors between C1⁺and C1^-, C2⁺and C2^-, C3⁺and C3^-, C4⁺

and C4^-, C5⁺and C5^-, VSS and VOUT boost the voltage of VDD - VSS to negative voltage (VDD Common) and

output the boosted voltage from the VOUT terminal. It selects one of boost time from 2 to 6 times by external

capacitors connection. Furthermore, it also selects one of boost time by ”Voltage Booster circuits multiple

select” instruction. The boost voltage and the voltage booster circuits are shown in below. Voltage Booster

circuits requires the clock signals from internal oscillation circuit, therefore, the oscillation circuits must be

operating when voltage boost operation. The boost voltage times are shown in below. When 6-time voltage

boost operation, the operation voltage of VDD-VOUT should be less than 18V.

VDD=+3V

VSS=+0V

VOUT=-VDD=-3V

VOUT=-2VDD=-6V

VOUT=-3VDD=-9V

VOUT=-4VDD=-12V

VOUT=-5VDD=-15V

2-time voltage

3-time voltage

4-time voltage

5-time voltage

6-time voltage

Examples for connecting the capacitors

SS

V

VSS

+

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

+

V

OUT

V

OUT

V

OUT

6-time voltage

5-time voltage

4-time voltage

VSS

+

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

C5+

C5-

+

V

OUT

V

OUT

3-time voltage

2-time voltage

NJU6679

(b)Voltage Adjust Circuits

The boosted voltage of VOUT output from V5 through the voltage adjust circuits for LCD driving. The output

voltage of V5 is adjusted by changing the Ra and Rb within the range of | V5 | < | VOUT |. The output voltage

is calculated by the following formula.

VLCD = VDD-V5 = (1+Rb/Ra)VREG

(1)

V

DD

V

REG

Ra

R1

R2

VR

V

5

R3

Rb

Fig. 3

The voltage of VREG is a standard voltage produced from built-in bleeder resistance. VREG is possible to be

fine-adjusted by EVR functions mentioned in (c).

For fine-adjustment of V5, R2 as variable resistor, R1 and R3 as fixed constant should be connected to VDD

terminal, VR and V5, as shown in Fig.3.

[ Design example for R1, R2 and R3 / Reference ]

- R1+R2+R3=5MW (Determined by the current flown between VDD-V5)

- Variable voltage range by the R2. -6V to -7.5V (VLCD=VDD-V5 --> 9.0V to 10.5V)

(Determined by the LCD electrical characteristics)

- VREG=3V(In case of EVR=(FF)H)

- R1, R2 and R3 are calculated by above conditions and the formula of (1) to below;

R1=2.0MW, R2=0.5MW, R3=2.5MW

* If the power supply voltage between VDD and VSS changes, V5 changes too. Therefore the power supply

voltage should be stabilized for V5 stable operation.

NJU6679

(c) Contrast Adjustment by the EVR function

The EVR controls voltage of VREG by instruction and changes voltage of V5.

As result, LCD display contrast is adjusted by V5. The EVR selects a voltage of VREG in the following 201

conditions by setting 6bits data into the EVR register.

In case of EVR operation, T1 terminal and T2 require to set couples of value as (L,L),(L,H) and (H,L) excepting

for (H,H) and the internal power supply must turn on by instruction.

(37)H to (4F)H available for use. If keeping 3% precision set EVR over (4F)H.

EVR register

(0,1,0,0,1,1,1,1)

VREG[V]

VLCD

Low

:

(4F)H

:

(124/300) x (VDD-VSS)

:

(FD)H

(FE)H

(FF)H

(1,1,1,1,1,1,0,1)

(1,1,1,1,1,1,1,0)

(1,1,1,1,1,1,1,1)

(298/300) x (VDD-VSS)

(299/300) x (VDD-VSS)

(300/300) x (VDD-VSS)

High

Adjustable range of the LCD driving voltage by EVR function

The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors

Ra and Rb.

[ Design example for the adjustable range / Reference ]

- Condition VDD=3.0V, VSS=0V

Ra=1MW, Rb=4MW ( Ra:Rb=1:4 )

The adjustable range and the step voltage are calculated as follows in the above condition.

In case of setting (4F)H in the EVR register,

VLCD = ((Ra+Rb)/Ra)VREG

= (5/1) x [(100/300) x 3.0]

= 6.2V

In case of setting (FF)H in the EVR register,

VLCD = ((Ra+Rb)/Ra)VREG

= (5/1) x [(300/300) x 3.0]

= 15.0V

Min.(4F)H

6.2

Max.(FF)H

15.0 [V]

Adjustable Range

Step Voltagre

- - - - - - - - - - - - - - - - - - -

50

[mV]

* In case of VDD=3V

NJU6679

*) The VLCD operating temperature. Please refer to the following graphs.

(conditions) VDD = 3V

Ra=1MW, Rb=4MW ( Ra:Rb = 1:4 )

Five times voltage

VLCD vs. Temperature (Typical Performance)

16

14

12

10

8

6

4

2

0

VLCD

EVR=(FF)H

T.B.D

VLCD

EVR=(4F)H

T.B.D.

-30 -20 -10

0

10 20 30 40 50 60 70 80

Ta [^oC]

NJU6679

(d) LCD Driving Voltage Generation Circuits

The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the V5 voltage with the

internal bleeder resistance. And it is supplied to the LCD driving circuits after the impedance conversion with

voltage follower circuit.

As shown in Fig. 4, Five capacitors are required to connect to each LCD driving voltage terminal for voltage

stabilizing. And the value of capacitors C6, C7, C8, C9 and C10 are determined depending on the actual LCD

panel display evaluation.

Using the internal Power Supply

Using the external Power Supply

VSS

C1+

VSS

C1+

+

C1

C1-

C2+

C2-

C3+

C3-

C4+

C1-

C2+

C2-

C3+

C3-

C4+

+

C2

C3

C4

C5

+

C_OUT

+

C4-

C5+

C5-

VOUT

NJU6679

R3

V5

R2

VR

R1

VDD

V1

C6

C7

C8

C9

C10

+

V1

V2

V3

V4

V5

External

V2

V3

V4

V5

Voltage

Generator

Reference set up value

VLCD=VDD-V5 = 9.0 to 10.5V

COUT

C1 to C5

C6 to C10

R1

to 1.0uF

T.B.D.

2.0MW

0.5MW

2.5MW

R2

R3

Fig.4

*1 Short wiring or sealed wiring to the VR terminal is required due to the high impedance of VR terminal.

*2 Following connection of VOUT is required when external power supply using.

When VSS > V5 --- VOUT=V5

When VSS < V5 --- VOUT=VSS

NJU6679

(5) MPU Interface

(5-1) Interface type selection

NJU6679 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or

serial interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in

Table 5. In case of the serial interface, status and RAM data read out operation is impossible.

Table 5

D0 to D5

Hi-Z

P/S

H

Type

CS

A0

RD

-

WR

-

SEL68

-

D7

SI

D6

Parallel

Serial

L

SCL

(5-2) Parallel Interface

The NJU6679 interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is selected.

68 type MPU or 80 is determined by the condition of SEL68 terminal connecting to "H" or "L" as shown in

table 6.

Table 6

SEL68

D0 to D7

Type

CS

A0

RD

E

WR

R/W

WR

H

L

68 type MPU

80 type MPU

RD

(5-3) Discrimination of Data Bus Signal

The NJU6679 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and

(RD,WR) signals as shown in Table 7.

Table 7

Common

68 type

80 type

Function

Read Display Data

A0

1

R/W

RD

0

WR

1

0

1

0

1

0

Write Display Data

0

1

Status Read

0

1

0

Write into the Register(Instruction)

(5-4) Serial Interface.(P/S="L")

Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are activated when

the chip select terminal CS set to "L"and P/S terminal set to "L". The 8 bits shift register and 3 bits counter are

reset to the initial condition when the chip is not selected. The data input from SI terminal is MSB first like as

the order of D7,D6,- - - - D0, and the data are entered into the shift register synchronizing with the rise edge of

the serial clock SCL. The data in the shift register are converted to parallel data at the 8th serial clock rise

edge input. Discrimination of the display data or instruction of the serial input data is executed by the condi-

tion of A0 at the 8th serial clock rise edge. A0="H" is display data and A0="L" is instruction. When RES

terminal becomes "L" or CS terminal becomes "H" before 8th serial clock rise edge, NJU6679 recognizes

them as a instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time

chart for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for the

SCL input.

Note) The read out function, such as the status or RAM data read out, is not supported in this serial interface

.

CS

SI

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

D₇

D₆

10

1

2

3

4

5

6

7

8

9

SCL

A0

Fig. 5

NJU6679

(5-5) Access to the Display Data RAM and Internal Register.

The NJU6679 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus

to adjust the operation frequency between MPU and the Display Data RAM or Internal Register.

For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read

cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the

next data read cycle. When the MPU writes the data into the Display Data RAM, the data is held in the bus-

holder, then it is written into the Display Data RAM by the next data write cycle.

Therefore high speed data transmission between MPU and NJU6679 is available because of it is not limited by

the tACC and tDS as display data RAM access time and is limited by the system cycle time (R) or (W).

If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the

waiting operation.

The read out operation does not read out the data in the pointed address just after the address set operation.

And second read out operation can read out the data correctly from the pointed address.

Therefore, one dummy read operation is required after address setting or write cycle as shown in FIG. 6.

Write Operation

MPU

WR

DATA

N

N+1

N+2

N+3

Internal

Timing

I/O Buffer

WR

N+1

N+2

N+3

N

Read Operation

MPU

WR

RD

N

n

n+1

DATA

N

Address Set N

Data Read n

Data Read n+1

Dummy Read

Internal

Timing

WR

RD

Column Address

I/O Buffer

N+1

N+2

n+1

N

n

n+2

N

Fig.6

(5-6) Chip Select

CS is Chip Select terminal. In case of CS="L", the interface with MPU is available. In case of CS=”H”, the D0

to D7 are high impedance and A0, RD, WR, D7(SI) and D6(SCL) inputs are ignored. If the serial interface is

selected when CS=”H”,the shift register and the counter are reset. However, the reset is always operated in

any conditions of CS.

NJU6679

ABSOLUTE MAXIMUM RATINGS

P A R A M E T E R

(Ta=25°C)

SYMBOL

VDD

R A T I N G S

-0.3 to +5.0

UNIT

Supply Voltage (1)

V

Supply Voltage (2)

Supply Voltage (3)

Input Voltage

V5

V1 to V4

VIN

VDD-18.0 to VDD+0.3

V5 to VDD+0.3

V

-0.3 to VDD+0.3

-30 to +80

V

Operating Temperature

Topr

°C

-55 to +125 (Chip)

-55 to +100 (TCP)

Storage Temperature

Tstg

°C

Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed.

Using the LSI within electrical characteristics is strongly recommended for normal operation. Use

beyond the electric characteristics conditions will cause malfunction and poor reliability.

Note 2) All voltage values are specified as VSS=0 V.

Note 3) The relation : VDD > V1 > V2 > V3 > V4 > V5 ; VDD > VSS > VOUT must be maintained.

Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for

the voltage converter.

ELECTRICAL CHARACTERISTICS (1)

(VDD=2.7V to 3.3V, VSS=0V, Ta=-30 to +80°C)

SYMBOL

VDD

Note

5

P A R A M E T E

C O N D I T I O N S

MIN.

2.4

TYP.

MAX.

3.6

UNIT

V

Operating Voltage(1)

V5

VDD-18.0

VDD-6.0

VDD-0.5VLCD

OperatingVoltage(2)

V

V1,V2 VLCD= VDD-V5

V3,V4

VDD

VDD-0.5VLCD

V5

High Level VIHC1 D0...D7,A0, CS,RES,RD,WR,SEL68,

P/S Terminals

0.8VDD

VSS

VDD

0.2VDD

VDD

V

Input

Voltage

Low Level

VILC1

High Level VOHC11 D0...D7

Terminals

IOH=-0.5mA

IOL= 0.5mA

0.8VDD

VSS

Output

Voltage

Low Level VOLC11

0.2VDD

All Input terminals

Input Leakage

ILIO

- 1.0

1.0

uA

6

7

Current

RON1

RON2

IDDQ

VLCD=15.0V

VLCD=8.0V

2.0

3.0

Ta=25°C

Driver On-resistance

Stand-by Current

Operating Current

kW

uA

3.0

4.5

during Power save Mode

T.B.D.

8

9

IDD12 Display VLCD=15.0V

IDD21 Accessing f CYC=200kHz

NJU6679

SYMBOL

CIN

Note

P A R A M E T E R

C O N D I T I O N S

MIN

TYP

10

MAX

UNIT

A0,CS,RES,RD,WR,SEL68,

P/S,T1,T2,D0...D7

Input Terminal

Capacitance

pF

Ta=25°C

Oscillation Frequency

Output Volt.

fOSC

T.B.D.

kHz

V

VSS-Vout, 6-time voltage booster,

VDD=3V

VOUT1

VDD-15.0

VDD-15.5

4000

VDD=3V;COUT=4.7uF

6-time voltage booster

On-resistance

DC/DC

VOUT2

V5

2000

W

V

Adjustment

Voltage Booster Circuit "OFF"

range of LCD

VDD-18.0V

VDD-6.0V

Driving Volt.

Voltage

Booster Voltage

Follower

10

Voltage Adjustment Circuit "OFF"

V

VDD=3V, VLCD=12V

COM/SEG Terminals Open

No Access

IOUT1

IOUT2

T.B.D.

Operating

Current

uA

%

11

12

IOUT3

Display Checkered pattern

Voltage Reg.

VREG%

VDD=3V,Ta=25°C, VREG=4F to FFH

Note 5) NJU6679 can operate wide operating range, but it is not guarantee immediate voltage changing during

the accessing of the MPU.

Note 6) Apply to the High-impedance state of the D0 to D7 terminals.

Note 7) RON is the resistance values between power supply terminals(V1, V2, V3, V4) and each output

terminals of common and segment supplied by 0.1V. This is specified within the range of supply

voltage (2).

Note 8,9,11) Apply to current after "LCD Driving Voltage Set".

Note 8) Apply to the external display clock operation in no access from the MPU and no use internal power

supply circuits.

Note 9) Apply to the condition of cyclic (tcyc) inverted data input continuously in no use internal power supply

circuits. The operating current during the accessing is proportionate to the access frequency. In the no

accessing period, it is as same as IDD1X.

Note 10) LCD driving voltage V5 can be adjusted within the voltage follower operating range.

Note 11) Each operating current of voltage supply circuits block is specified under below table conditions.

Status

Operating Condition

External

Voltage Supply

(Input Terminal)

Unuse

SYMBOL

Internal

Oscillator

Validity

Voltage

Booster

Validity

Voltage

Adjustment

Validity

Voltage

Follower

Validity

T1

T2

IOUT1

IOUT2

IOUT3

L

H

*

L

Validity

Invalidity

Validity

Use(VOUT)

H

Validity

Invalidity

Use(VOUT,V5)

(* = Don’t Care)

Note 12) Apply to the precision of the voltage between VDD and V5 with EVR function.

NJU6679

MEASUREMENT BLOCK DIAGRAM

:IOUT1

VR

V5

VDD

T1

A

NJU6679

T2

C1-C2+ C2-

+

C3+ C3-C4+

C4-

C5+

C5- VOUT

VSS C1+

+

:IOUT2

VR

V5

VDD

T1

A

NJU6679

T2

C1-C2+ C2- C3+ C3-C4+ C4-

C5+

C5- VOUT

VSS C1+

+

:IOUT3

VR

V5

VDD

T1

T2

A

NJU6679

C1-C2+ C2- C3+ C3-C4+

C5-

VOUT

VSS C1+

C4-C5+

+

ELECTRICAL CHARACTERISTICS (2)

P A R A M E T E R SYMBOL

(VDD=2.7V to 3.3V, VSS=0V, Ta=-30 to +80°C)

C O N D I T I O N S

MIN

1.0

TYP

MAX

UNIT Note

Reset time

tR

RES Terminal

us

13

Reset "L" Level Pulse

tRW

RES Terminal

10

us

14

Width

Note 13) Specified from the rising edge of RES to finish the internal circuit reset.

Note 14) Specified minimum pulse width of RES signal. Over than tRW "L" input should be required for correct

reset operation.

NJU6679

BUS TIMING CHARACTERISTICS

- Read/Write operation sequence (80 Type MPU)

t

CYC8

A0,CS

t

AW8

t

AH8

tCCL

WR,RD

t

CCH

tDH8

t

DS8

D

(Write)

0

to D

7

t

f

tr

tACC

t

CH8

D

0

to D

7

(Read)

(VDD=2.7V to 3.3V,Ta=-30 to +80°C)

S YMBO-

L

C O N D ITIO-

P A R A M E T E R

M IN.

TYP.

M A X .

UNIT

N

Address Hold Time

tAH8

10

0

ns

A0,C S

Terminals

Address Set Up Time

tAW 8

S ystem C ycle W R

Time

tC YC 8

(W)

220

350

50

ns

RD

tC YC 8 (R)

W R ,"-

L"

W R ,RD

Terminals

tC C L(W)

C o ntrol

RD,"-

P ulse W idth

L"

tC C L(R)

200

ns

"H"

D a ta Set Up Time

D a ta Hold Time

tC C H

tD S 8

160

35

ns

tDH8

15

D 0 to D 7

Terminals

RD Access Time

Output D isable Time

tA C C 8

tCH8

120

15

CL=100pF

C S , WR,

RD,A0, D0

to D 7

Rise Time, Fall Time

tr,tf

15

ns

Terminals

Note 15) Rise time (tr) and fall time (tf) of input signal should be less than 15ns.

Note 16) Each timing is specified based on 0.2xVDD and 0.8xVDD.

NJU6679

- Read/Write operation sequence (68 Type MPU)

t

CYC6

t

EWL

E

t

AW6

t

EWH

t

f

R/W

t

r

t

AH6

A0,CS

tDH6

t

DS6

D

0

to D

7

(Write)

t

OH6

t

ACC6

D

0

to D

7

(Read)

(VDD=2.7V to 3.3V,Ta=-30 to +80°C)

P A R A M E T E R

SYMBOL

tAH6

MIN.

TYP.

10

MAX.

CONDITION UNIT

Address Hold Time

ns

Address Set Up Time

System Cycle Time(W)

System Cycle Time(R)

tAW6

0

A0,CS,R/W

Terminals

tCYC6(W)

tCYC6(R)

220

350

200

50

Read"H"

Enable

Pulse Width

"L"

tEWH

E Terminal

Write"H"

tEWL

tDS6

160

35

Data Set Up Time

Data Hold Time

Access Time

ns

tDH6

tACC6

tOH6

15

D0 to D7

Terminals

150

20

ns

CL=100pF

ns

Output Disable Time

A0, CS, R/W,

E, D0 to D7

Terminals

Rise Time, Fall Time

tr,tf

15

ns

Note 17) tCYC6 indicates the E signal cycle during the CS activation period. The System Cycle Time must be

required after CS becomes active.

Note 18) Rise time (tr) and fall time (tf) of input signal should be less than 15ns.

Note 19) Each timing is specified based on 0.2xVDD and 0.8xVDD.

NJU6679

- Write operation sequence (Serial Interface)

t

CSS

t

CSH

CS

A0

t

SAS

t

SAH

t

SCYC

t

SLW

SCL

SI

t

SHW

tSDS

t

SDH

t

f

t

r

(VDD=2.7V to 3.3V,Ta=-30 to +80°C)

P A R A M E T E R

SYMBOL

tSCYC

tSHW

tSLW

MIN.

TYP.

60

MAX.

CONDITION UNIT

Serial Clock cycle

SCL "H" pulse width

SCL "L" pulse width

Address Set Up Time

Address Hold Time

Data Set Up Time

Data Hold Time

ns

SCL

30

Terminal

30

tSAS

0

A0 Terminal

SI Terminal

CS Terminal

tSAH

150

25

tSDS

tSDH

10

tCSS

10

CS-SCL Time

tCSH

300

SCL, A0,

CS, SI

Rise Time, Fall Time

tr,tf

15

ns

Terminals

Note 20) Rise time (tr) and fall time (tf) of input signal should be less than 15ns.

Note 21) Each timing is specified based on 0.2xVDD and 0.8xVDD.

Note 22) In case of instruction set continuously, it is required to wait more than 450ns between the instruction

and next as follows.

SCL 8th clock

SCL 1st clock

SCL

450 ns

SCL"L"pulse width

(Between the

Instruction N+1

Instruction N

instruction and next)

NJU6679

LCD DRIVING WAVEFORM

127

0 1 2 3 4 5

127

126

0

1

2

3

4

V_DD

FR

V

SS

V_DD

COM₀

V

1

COM

1

V

2

COM₀

V

3

COM

3

V

4

COM

V

5

6

V_DD

COM

7

V

1

V

2

COM₁

V

3

COM

8

V

4

COM

9

V

5

COM

10

COM

11

COM

12

COM

13

V_DD

COM

14

COM

15

V

1

V

2

COM₂

V

3

V

4

V

5

V_DD

V

1

V

2

SEG₀

V

3

V

4

V

5

V_DD

V

1

V

2

SEG₁

V

3

V

4

V

5

V₅

V₄

V

3

V₂

V₁

V

DD

COM₀-SEG₀

-

V₁

V₂

V₃

V₄

V₅

-

V

5

V

4

V

3

V₂

V₁

V

DD

COM₀-SEG₁

-

V₁

V₂

V₃

V₄

V₅

-

Fig.7

NJU6679

APPLICATION CIRCUIT

- Microprocessor Interface Example

The NJU6679 interfaces to 80 type or 68 type MPU directly.

And the serial interface also communicate with MPU.

- 80 Type MPU

VDD

VCC

A0

CEL86

A0 to A7

IORQ

CS

Decoder

MPU

NJU6679

D0 to D7

RD

D0 to D7

RD

WR

P/S

RES

GND

VSS

RESET

- 68 Type MPU

VCC

VDD

A0

CEL86

A0 to A15

VMA

CS

Decoder

NJU6679

MPU

D0 to D7

E

R/W

RES

P/S

RES

GND

VSS

RESET

- Serial Interface

VCC

VDD

A0

CEL86

A1 to A7

CS

Decoder

VDD

OR GND

MPU

NJU6679

SI

Port1

Port2

SCL

P/S

RES

GND

VSS

RESET


型号：	NJU6679
厂家：	NEW JAPAN RADIO
描述：	128-common x 132-segment BIT MAP LCD DRIVER 128普通X 132段位图LCD驱动器驱动器 CD
文件：	总46页 (文件大小：536K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6679 [NJRC]

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