NJU6818CJ_技术文档

NJU6818

Preliminary

80-Common X 104RGB-Segment in 4096-Color

STN LCD DRIVER

ꢀ GENERAL DESCRIPTION

ꢀ PACKAGE OUTLINE

The NJU6818 is a STN LCD driver with 80-common x

104RGB-segment in 4096-color. It consists of 312-

segment drivers (104xRGB), 80-common drivers, serial

and parallel MPU interface circuits, internal power supply

circuits, gradation palettes and 99,840-bit for graphic

display data RAM.

Each segment driver outputs 16-gradation level out of 32-

gradation level of the gradation palette.

NJU6818CJ

Since the NJU6818 provides low operating voltage of 1.7V

and low operating current, it is ideally suited for battery-

powered handheld applications.

ꢀ FEATURES

ꢁ 4096-color STN LCD driver

ꢁ LCD drivers

80-commons, 104RGB-segments

ꢁ Display data RAM (DDRAM)

ꢁ Color display mode

99,840-bit for graphic display

16-gradation level out of 32-gradation level of the gradation palette

80x312 pixels in 16-gradation level or 80x312 pixels in B&W

ꢁ Black & white display mode

ꢁ 256-color driving mode

ꢁ 8/16bit parallel interface directly-connective to 68/80 series MPU

ꢁ Programmable 8- or 16-bit data bus length for display data

ꢁ 3-/4-line serial interface

ꢁ Programmable duty and bias ratios

ꢁ Programmable internal voltage booster (Maximum 6-times)

ꢁ Programmable contrast control using 128-step EVR

ꢁ Chip Identification (ID)

ꢁ Various instructions

Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF,

Column address, Row address, N-line inversion, Initial display line, Initial COM line, Read-modify-write,

Gradation mode control, Increment control, Data bus length, Discharge ON/OFF,

Duty cycle ratio, LCD bias ratio, Boost level, EVR control, Power save ON/OFF, etc

ꢁ Low operating current

ꢁ Low logic supply voltage

ꢁ LCD driving supply voltage

ꢁ C-MOS technology

ꢁ Rectangle out look for COG

ꢁ Package

1.7V to 3.3V

5.0V to 18.0V

Bumped chip / TCP

2002/08/26

- 1 -

NJU6818

ꢀ PAD LOCATION

744: DMY₁₁₂

745: DMY₁₁₃

746: DMY₁₁₃

747: DMY₁₁₃

748: DMY₁₁₄

1

Note 1) The same name PADs are shorted mutually in the LSI.

Note 2) The DMY PADs are electrically open.

Chip Center

Chip Size

: X= 0µm, Y= 0µm

: 19.25mm x 2.50mm

Chip Thickness : 625µm ± 25µm

Bump Size

Bump Pitch

Bump high

: 26µm x 120µm

: 45µm(Min)

: 17.5µm(Typ.)

: Au

Bump Material

- 2 -

NJU6818

Y

X

ꢀ

Alignment mark 1

Alignment mark

a

a : 25µm

b : 50µm

coordinates

b

a

Alignment mark coordinates

( -9445, 1070 )

( 9445, -1070 )

b

ꢀ

Alignment mark 2

Alignment mark

coordinates

a : 50µm

c

Alignment mark coordinates

( 9257, -1068 )

- 3 -

NJU6818

ꢀ

Alignment mark 3

Alignment mark

coordinates

d : 50µm

e : 20µm

e

d

Alignment mark coordinates

( -9257, -1068 )

- 4 -

NJU6818

339: DMY₉₉

338: DMY₉₈

337: DMY₉₈

336: DMY₉₈

335: DMY₉₇

- 5 -

NJU6818

ꢀ PAD COORDINATES 1

Chip Size 19250µm x 2500µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

No.

1

No.

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

DMY₀

DMY₁

DMY₂

V_DDA

-9067.5 -1055

-9022.5 -1055

-8977.5 -1055

-8932.5 -1055

-8887.5 -1055

-8842.5 -1055

-8797.5 -1055

-8752.5 -1055

-8707.5 -1055

-8662.5 -1055

-8617.5 -1055

-8572.5 -1055

-8527.5 -1055

-8482.5 -1055

-8437.5 -1055

-8392.5 -1055

-8347.5 -1055

-8302.5 -1055

-8257.5 -1055

-8212.5 -1055

-8167.5 -1055

-8122.5 -1055

-8077.5 -1055

-8032.5 -1055

-7987.5 -1055

-7942.5 -1055

-7897.5 -1055

-7852.5 -1055

-7807.5 -1055

-7762.5 -1055

-7717.5 -1055

-7672.5 -1055

-7627.5 -1055

-7582.5 -1055

-7537.5 -1055

-7492.5 -1055

-7447.5 -1055

-7402.5 -1055

-7357.5 -1055

-7312.5 -1055

-7267.5 -1055

-7222.5 -1055

-7177.5 -1055

-7132.5 -1055

-7087.5 -1055

-7042.5 -1055

-6997.5 -1055

-6952.5 -1055

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

DMY₂₇

RS

-6772.5

-6727.5

-6682.5

-6637.5

-6592.5

-6547.5

-6502.5

-6457.5

-6412.5

-6367.5

-6322.5

-6277.5

-6232.5

-6187.5

-6142.5

-6097.5

-6052.5

-6007.5

-5962.5

-5917.5

-5872.5

-5737.5

-5692.5

-5647.5

-5512.5

-5467.5

-5422.5

-5287.5

-5242.5

-5197.5

-5062.5

-5017.5

-4972.5

-4837.5

-4792.5

-4747.5

-4612.5

-4567.5

-4522.5

-4387.5

-4342.5

-4297.5

-4162.5

-4117.5

-4072.5

-3937.5

-3892.5

-3757.5

-3712.5

-3667.5

-3532.5

-1055

D₉

-3487.5

-3442.5

-3307.5

-3262.5

-3217.5

-3082.5

-3037.5

-2992.5

-2857.5

-2812.5

-2767.5

-2632.5

-2587.5

-2542.5

-2407.5

-2362.5

-2317.5

-2182.5

-2137.5

-2092.5

-1957.5

-1912.5

-1867.5

-1822.5

-1777.5

-1732.5

-1687.5

-1642.5

-1597.5

-1372.5

-1327.5

-1282.5

-1147.5

-1102.5

-1057.5

-922.5

-1055

2

DMY₄₉

DMY₅₀

D₁₀

3

RS

4

DMY₂₈

DMY₂₉

DMY₃₀

DMY₃₁

WRb

DMY₃₂

DMY₃₃

RDb

5

V_DDA

D₁₀

6

DMY₃

ID₀

D₁₁

7

D₁₁

8

ID₀

DMY₅₁

DMY₅₂

D₁₂

9

DMY₄

DMY₅

DMY₆

DMY₇

ID₁

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

D₁₂

D₁₃

RDb

D₁₃

ID₁

DMY₃₄

DMY₃₅

V_DDA

DMY₅₃

DMY₅₄

D₁₄

DMY₈

DMY₉

ID₂

V_DDA

D₁₄

ID₂

DMY₃₆

DMY₃₇

DMY₃₈

DMY₃₉

DMY₄₀

D₀/SCL

D₁/SDA

DMY₄₁

DMY₄₂

D₂

D₁₅

DMY₁₀

DMY₁₁

DMY₁₂

DMY₁₃

ID₃

D₁₅

DMY₅₅

V_DD

ID₃

V_DD

DMY₁₄

V_SSA

V_DD

V_SSA

V_DD

DMY₁₅

SEL₆₈

DMY₁₆

DMY₁₇

V_DDA

V_DD

D₂

DMY₅₆

CL

D₃/SMODE

DMY₄₃

DMY₄₄

D₄/SPOL

D₅

CL

FLM

DMY₅₇

DMY₅₈

FR

V_DDA

DMY₁₈

DMY₁₉

P/S

-877.5

P/S

D₅

FR

-832.5

DMY₂₀

V_SSA

DMY₄₅

DMY₄₆

D₆

CLK

DMY₅₉

DMY₆₀

OSC₁

DMY₆₁

DMY₆₂

OSC₂

V_SS

-697.5

-652.5

V_SSA

-607.5

DMY₂₁

RESb

DMY₂₂

DMY₂₃

DMY₂₄

DMY₂₅

CSb

D₆

-472.5

D₇

-427.5

D₇

-382.5

DMY₄₇

V_SSA

-337.5

-292.5

V_SSA

-157.5

DMY₄₈

D₈

-112.5

-6907.5 -1055 100

-6862.5 -1055 101

-6817.5 -1055 102

22.5

CSb

DMY₂₆

D₈

D₉

V_SS

67.5

112.5

- 6 -

NJU6818

ꢀ PAD COORDINATES 2

Chip Size 19250µm x 2500µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

No.

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

154 V_SS

155 V_SS

156 V_SS

157 V_SS

158 V_SS

159 V_SS

160 DMY₆₃

161 V_LCD

162 V_LCD

163 V_LCD

164 V_LCD

165 V_LCD

166 V_LCD

167 V_LCD

168 V_LCD

169 DMY₆₄

170 V₁

171 V₁

172 V₁

173 V₁

174 V₁

175 V₁

176 V₁

177 V₁

178 V₂

179 V₂

180 V₂

181 V₂

182 V₂

183 V₂

184 V₂

185 V₂

186 DMY₆₅

187 V₃

188 V₃

189 V₃

190 V₃

191 V₃

192 V₃

193 V₃

194 V₃

195 V₄

196 V₄

197 V₄

198 V₄

199 V₄

200 V₄

201 V₄

202 V₄

203 DMY₆₆

204 V_REG

157.5 -1055 205 V_REG

202.5 -1055 206 V_REG

247.5 -1055 207 V_REG

292.5 -1055 208 V_REG

337.5 -1055 209 V_REG

382.5 -1055 210 V_REG

2812.5

2857.5

2902.5

2947.5

2992.5

3037.5

3082.5

3127.5

3172.5

3217.5

3262.5

3307.5

3352.5

3397.5

3442.5

3487.5

3532.5

3577.5

3622.5

3667.5

3712.5

3757.5

3802.5

3847.5

3892.5

3937.5

3982.5

4027.5

4072.5

4117.5

4162.5

4207.5

4252.5

4297.5

4342.5

4567.5

4612.5

4657.5

4702.5

4747.5

4792.5

4837.5

4882.5

4927.5

5152.5

5197.5

5242.5

5287.5

5332.5

5377.5

5422.5

-1055

V_EE

5467.5

5512.5

5647.5

5692.5

5737.5

5782.5

5827.5

5872.5

5917.5

5962.5

6007.5

6052.5

6097.5

6142.5

6187.5

6232.5

6277.5

6322.5

6367.5

6412.5

6457.5

6502.5

6547.5

6592.5

6637.5

6682.5

6727.5

6772.5

6817.5

6862.5

6907.5

6952.5

6997.5

7042.5

7087.5

7132.5

7177.5

7222.5

7267.5

7312.5

7357.5

7402.5

7447.5

7492.5

7537.5

7582.5

7627.5

7672.5

7717.5

7762.5

7807.5

-1055

V_EE

DMY₇₀

DMY₇₁

DMY₇₂

DMY₇₃

DMY₇₄

C1+

517.5 -1055 211

V_REG

652.5 -1055 212 DMY₆₇

697.5 -1055 213 V_REF

742.5 -1055 214 V_REF

787.5 -1055 215 V_REF

832.5 -1055 216 V_REF

877.5 -1055 217 V_REF

922.5 -1055 218 V_REF

967.5 -1055 219 V_REF

1012.5 -1055 220 V_REF

1057.5 -1055 221 DMY₆₈

1102.5 -1055 222 V_BA

1147.5 -1055 223 V_BA

1192.5 -1055 224 V_BA

1237.5 -1055 225 V_BA

1282.5 -1055 226 V_BA

1327.5 -1055 227 V_BA

1372.5 -1055 228 V_BA

1507.5 -1055 229 V_BA

1552.5 -1055 230 DMY₆₉

1597.5 -1055 231 V_SSH

1642.5 -1055 232 V_SSH

1687.5 -1055 233 V_SSH

1732.5 -1055 234 V_SSH

1777.5 -1055 235 V_SSH

1822.5 -1055 236 V_SSH

1867.5 -1055 237 V_SSH

1912.5 -1055 238 V_SSH

1957.5 -1055 239 V_SSH

2002.5 -1055 240 V_OUT

2047.5 -1055 241 V_OUT

2092.5 -1055 242 V_OUT

2137.5 -1055 243 V_OUT

2182.5 -1055 244 V_OUT

2227.5 -1055 245 V_OUT

2362.5 -1055 246 V_OUT

2407.5 -1055 247 V_OUT

2452.5 -1055 248 V_OUT

2497.5 -1055 249 V_EE

2542.5 -1055 250 V_EE

2587.5 -1055 251 V_EE

2632.5 -1055 252 V_EE

2677.5 -1055 253 V_EE

2722.5 -1055 254 V_EE

2767.5 -1055 255 V_EE

C1+

DMY₇₅

DMY₇₆

C1-

DMY₇₇

DMY₇₈

C2+

DMY₇₉

DMY₈₀

C2-

DMY₈₁

DMY₈₂

C3+

DMY₈₃

DMY₈₄

C3-

DMY₈₅

DMY₈₆

C4+

- 7 -

NJU6818

ꢀ PAD COORDINATES 3

Chip Size 19250µm x 2500µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

No.

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

307 C₄+

7852.5

7897.5

7942.5

7987.5

8032.5

8077.5

8122.5

8167.5

8212.5

8257.5

8302.5

8347.5

8392.5

8437.5

8482.5

8527.5

8572.5

8617.5

8662.5

8707.5

8752.5

8797.5

8842.5

8887.5

8932.5

8977.5

9022.5

9067.5

9430

-1055 358 COM₂₄

-1055 359 COM₂₃

-1055 360 COM₂₂

-1055 361 COM₂₁

-1055 362 COM₂₀

-1055 363 COM₁₉

-1055 364 COM₁₈

-1055 365 COM₁₇

-1055 366 COM₁₆

-1055 367 COM₁₅

-1055 368 COM₁₄

-1055 369 COM₁₃

-1055 370 COM₁₂

-1055 371 COM₁₁

-1055 372 COM₁₀

-1055 373 COM₉

-1055 374 COM₈

-1055 375 COM₇

-1055 376 COM₆

-1055 377 COM₅

-1055 378 COM₄

-1055 379 COM₃

-1055 380 COM₂

-1055 381 COM₁

-1055 382 COM₀

-1055 383 DMY₁₀₃

-1055 384 DMY₁₀₄

-1055 385 DMY₁₀₅

-964 386 SEGA₀

-919 387 SEGB₀

-874 388 SEGC₀

-829 389 SEGA₁

-784 390 SEGB₁

1055 391 SEGC₁

1055 392 SEGA₂

1055 393 SEGB₂

1055 394 SEGC₂

1055 395 SEGA₃

1055 396 SEGB₃

1055 397 SEGC₃

1055 398 SEGA₄

1055 399 SEGB₄

1055 400 SEGC₄

1055 401 SEGA₅

1055 402 SEGB₅

1055 403 SEGC₅

1055 404 SEGA₆

1055 405 SEGB₆

1055 406 SEGC₆

1055 407 SEGA₇

1055 408 SEGB₇

8257.5

8212.5

8167.5

8122.5

8077.5

8032.5

7987.5

7942.5

7897.5

7852.5

7807.5

7762.5

7717.5

7672.5

7627.5

7582.5

7537.5

7492.5

7447.5

7402.5

7357.5

7312.5

7267.5

7222.5

7177.5

7132.5

7087.5

7042.5

6997.5

6952.5

6907.5

6862.5

6817.5

6772.5

6727.5

6682.5

6637.5

6592.5

6547.5

6502.5

6457.5

6412.5

6367.5

6322.5

6277.5

6232.5

6187.5

6142.5

6097.5

6052.5

6007.5

1055

SEGC₇

SEGA₈

5962.5

5917.5

5872.5

5827.5

5782.5

5737.5

5692.5

5647.5

5602.5

5557.5

5512.5

5467.5

5422.5

5377.5

5332.5

5287.5

5242.5

5197.5

5152.5

5107.5

5062.5

5017.5

4972.5

4927.5

4882.5

4837.5

4792.5

4747.5

4702.5

4657.5

4612.5

4567.5

4522.5

4477.5

4432.5

4387.5

4342.5

4297.5

4252.5

4207.5

4162.5

4117.5

4072.5

4027.5

3982.5

3937.5

3892.5

3847.5

3802.5

3757.5

3712.5

1055

308 C₄+

309 C₄+

SEGB₈

310 DMY₈₇

311 DMY₈₈

312 C₄-

SEGC₈

SEGA₉

SEGB₉

313 C₄-

SEGC₉

SEGA₁₀

SEGB₁₀

SEGC₁₀

SEGA₁₁

SEGB₁₁

SEGC₁₁

SEGA₁₂

SEGB₁₂

SEGC₁₂

SEGA₁₃

SEGB₁₃

SEGC₁₃

SEGA₁₄

SEGB₁₄

SEGC₁₄

SEGA₁₅

SEGB₁₅

SEGC₁₅

SEGA₁₆

SEGB₁₆

SEGC₁₆

SEGA₁₇

SEGB₁₇

SEGC₁₇

SEGA₁₈

SEGB₁₈

SEGC₁₈

SEGA₁₉

SEGB₁₉

SEGC₁₉

SEGA₂₀

SEGB₂₀

SEGC₂₀

SEGA₂₁

SEGB₂₁

SEGC₂₁

SEGA₂₂

SEGB₂₂

SEGC₂₂

SEGA₂₃

SEGB₂₃

SEGC₂₃

SEGA₂₄

SEGB₂₄

314 C₄-

315 C₄-

316 C₄-

317 DMY₈₉

318 DMY₉₀

319 C₅+

320 C₅+

321 C₅+

322 C₅+

323 C₅+

324 DMY₉₁

325 DMY₉₂

326 C₅-

327 C₅-

328 C₅-

329 C₅-

330 C₅-

331 DMY₉₃

332 DMY₉₄

333 DMY₉₅

334 DMY₉₆

335 DMY₉₇

336 DMY₉₈

337 DMY₉₈

338 DMY₉₈

339 DMY₉₉

340 DMY₁₀₀

341 DMY₁₀₁

342 DMY₁₀₂

343 COM₃₉

344 COM₃₈

345 COM₃₇

346 COM₃₆

347 COM₃₅

348 COM₃₄

349 COM₃₃

350 COM₃₂

351 COM₃₁

352 COM₃₀

353 COM₂₉

354 COM₂₈

355 COM₂₇

356 COM₂₆

357 COM₂₅

9430

9067.5

9022.5

8977.5

8932.5

8887.5

8842.5

8797.5

8752.5

8707.5

8662.5

8617.5

8572.5

8527.5

8482.5

8437.5

8392.5

8347.5

8302.5

- 8 -

NJU6818

■ PAD COORDINATES 4

Chip Size 19250µm x 2500µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

No.

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

460 SEGC₂₄

461 SEGA₂₅

462 SEGB₂₅

463 SEGC₂₅

464 SEGA₂₆

465 SEGB₂₆

466 SEGC₂₆

467 SEGA₂₇

468 SEGB₂₇

469 SEGC₂₇

470 SEGA₂₈

471 SEGB₂₈

472 SEGC₂₈

473 SEGA₂₉

474 SEGB₂₉

475 SEGC₂₉

476 SEGA₃₀

477 SEGB₃₀

478 SEGC₃₀

479 SEGA₃₁

480 SEGB₃₁

481 SEGC₃₁

482 SEGA₃₂

483 SEGB₃₂

484 SEGC₃₂

485 SEGA₃₃

486 SEGB₃₃

487 SEGC₃₃

488 SEGA₃₄

489 SEGB₃₄

490 SEGC₃₄

491 SEGA₃₅

492 SEGB₃₅

493 SEGC₃₅

494 SEGA₃₆

495 SEGB₃₆

496 SEGC₃₆

497 SEGA₃₇

498 SEGB₃₇

499 SEGC₃₇

500 SEGA₃₈

501 SEGB₃₈

502 SEGC₃₈

503 SEGA₃₉

504 SEGB₃₉

505 SEGC₃₉

506 SEGA₄₀

507 SEGB₄₀

508 SEGC₄₀

509 SEGA₄₁

510 SEGB₄₁

3667.5

3622.5

3577.5

3532.5

3487.5

3442.5

3397.5

3352.5

3307.5

3262.5

3217.5

3172.5

3127.5

3082.5

3037.5

2992.5

2947.5

2902.5

2857.5

2812.5

2767.5

2722.5

2677.5

2632.5

2587.5

2542.5

2497.5

2452.5

2407.5

2362.5

2317.5

2272.5

2227.5

2182.5

2137.5

2092.5

2047.5

2002.5

1957.5

1912.5

1867.5

1822.5

1777.5

1732.5

1687.5

1642.5

1597.5

1552.5

1507.5

1462.5

1417.5

1055 511 SEGC₄₁

1055 512 SEGA₄₂

1055 513 SEGB₄₂

1055 514 SEGC₄₂

1055 515 SEGA₄₃

1055 516 SEGB₄₃

1055 517 SEGC₄₃

1055 518 SEGA₄₄

1055 519 SEGB₄₄

1055 520 SEGC₄₄

1055 521 SEGA₄₅

1055 522 SEGB₄₅

1055 523 SEGC₄₅

1055 524 SEGA₄₆

1055 525 SEGB₄₆

1055 526 SEGC₄₆

1055 527 SEGA₄₇

1055 528 SEGB₄₇

1055 529 SEGC₄₇

1055 530 SEGA₄₈

1055 531 SEGB₄₈

1055 532 SEGC₄₈

1055 533 SEGA₄₉

1055 534 SEGB₄₉

1055 535 SEGC₄₉

1055 536 SEGA₅₀

1055 537 SEGB₅₀

1055 538 SEGC₅₀

1055 539 SEGA₅₁

1055 540 SEGB₅₁

1055 541 SEGC₅₁

1055 542 SEGA₅₂

1055 543 SEGB₅₂

1055 544 SEGC₅₂

1055 545 SEGA₅₃

1055 546 SEGB₅₃

1055 547 SEGC₅₃

1055 548 SEGA₅₄

1055 549 SEGB₅₄

1055 550 SEGC₅₄

1055 551 SEGA₅₅

1055 552 SEGB₅₅

1055 553 SEGC₅₅

1055 554 SEGA₅₆

1055 555 SEGB₅₆

1055 556 SEGC₅₆

1055 557 SEGA₅₇

1055 558 SEGB₅₇

1055 559 SEGC₅₇

1055 560 SEGA₅₈

1055 561 SEGB₅₈

1372.5

1327.5

1282.5

1237.5

1192.5

1147.5

1102.5

1057.5

1012.5

967.5

922.5

877.5

832.5

787.5

742.5

697.5

652.5

607.5

562.5

517.5

472.5

427.5

382.5

337.5

292.5

247.5

202.5

157.5

112.5

1055

SEGC₅₈

SEGA₅₉

SEGB₅₉

SEGC₅₉

SEGA₆₀

SEGB₆₀

SEGC₆₀

SEGA₆₁

SEGB₆₁

SEGC₆₁

SEGA₆₂

SEGB₆₂

SEGC₆₂

SEGA₆₃

SEGB₆₃

SEGC₆₃

SEGA₆₄

SEGB₆₄

SEGC₆₄

SEGA₆₅

SEGB₆₅

SEGC₆₅

SEGA₆₆

SEGB₆₆

SEGC₆₆

SEGA₆₇

SEGB₆₇

SEGC₆₇

SEGA₆₈

SEGB₆₈

SEGC₆₈

SEGA₆₉

SEGB₆₉

SEGC₆₉

SEGA₇₀

SEGB₇₀

SEGC₇₀

SEGA₇₁

SEGB₇₁

SEGC₇₁

SEGA₇₂

SEGB₇₂

SEGC₇₂

SEGA₇₃

SEGB₇₃

SEGC₇₃

SEGA₇₄

SEGB₇₄

SEGC₇₄

SEGA₇₅

SEGB₇₅

-922.5

-967.5

1055

-1012.5

-1057.5

-1102.5

-1147.5

-1192.5

-1237.5

-1282.5

-1327.5

-1372.5

-1417.5

-1462.5

-1507.5

-1552.5

-1597.5

-1642.5

-1687.5

-1732.5

-1777.5

-1822.5

-1867.5

-1912.5

-1957.5

-2002.5

-2047.5

-2092.5

-2137.5

-2182.5

-2227.5

-2272.5

-2317.5

-2362.5

-2407.5

-2452.5

-2497.5

-2542.5

-2587.5

-2632.5

-2677.5

-2722.5

-2767.5

-2812.5

-2857.5

-2902.5

-2947.5

-2992.5

-3037.5

-3082.5

-3127.5

-3172.5

67.5

22.5

-22.5

-67.5

-112.5

-157.5

-202.5

-247.5

-292.5

-337.5

-382.5

-427.5

-472.5

-517.5

-562.5

-607.5

-652.5

-697.5

-742.5

-787.5

-832.5

-877.5

- 9 -

NJU6818

■ PAD COORDINATES 5

Chip Size 19250µm x 2500µm (Chip Center 0µm x 0µm )

PAD

No.

PAD

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

Terminal

X(µm)

Y(µm)

No.

715

716

717

718

719

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

743

744

745

746

747

748

749

750

751

752

753

754

755

756

757

758

759

760

761

762

763

764

765

613 SEGC₇₅

614 SEGA₇₆

615 SEGB₇₆

616 SEGC₇₆

617 SEGA₇₇

618 SEGB₇₇

619 SEGC₇₇

620 SEGA₇₈

621 SEGB₇₈

622 SEGC₇₈

623 SEGA₇₉

624 SEGB₇₉

625 SEGC₇₉

626 SEGA₈₀

627 SEGB₈₀

628 SEGC₈₀

629 SEGA₈₁

630 SEGB₈₁

631 SEGC₈₁

632 SEGA₈₂

633 SEGB₈₂

634 SEGC₈₂

635 SEGA₈₃

636 SEGB₈₃

637 SEGC₈₃

638 SEGA₈₄

639 SEGB₈₄

640 SEGC₈₄

641 SEGA₈₅

642 SEGB₈₅

643 SEGC₈₅

644 SEGA₈₆

645 SEGB₈₆

646 SEGC₈₆

647 SEGA₈₇

648 SEGB₈₇

649 SEGC₈₇

650 SEGA₈₈

651 SEGB₈₈

652 SEGC₈₈

653 SEGA₈₉

654 SEGB₈₉

655 SEGC₈₉

656 SEGA₉₀

657 SEGB₉₀

658 SEGC₉₀

659 SEGA₉₁

660 SEGB₉₁

661 SEGC₉₁

662 SEGA₉₂

663 SEGB₉₂

-3217.5

-3262.5

-3307.5

-3352.5

-3397.5

-3442.5

-3487.5

-3532.5

-3577.5

-3622.5

-3667.5

-3712.5

-3757.5

-3802.5

-3847.5

-3892.5

-3937.5

-3982.5

-4027.5

-4072.5

-4117.5

-4162.5

-4207.5

-4252.5

-4297.5

-4342.5

-4387.5

-4432.5

-4477.5

-4522.5

-4567.5

-4612.5

-4657.5

-4702.5

-4747.5

-4792.5

-4837.5

-4882.5

-4927.5

-4972.5

-5017.5

-5062.5

-5107.5

-5152.5

-5197.5

-5242.5

-5287.5

-5332.5

-5377.5

-5422.5

-5467.5

1055 664 SEGC₉₂

1055 665 SEGA₉₃

1055 666 SEGB₉₃

1055 667 SEGC₉₃

1055 668 SEGA₉₄

1055 669 SEGB₉₄

1055 670 SEGC₉₄

1055 671 SEGA₉₅

1055 672 SEGB₉₅

1055 673 SEGC₉₅

1055 674 SEGA₉₆

1055 675 SEGB₉₆

1055 676 SEGC₉₆

1055 677 SEGA₉₇

1055 678 SEGB₉₇

1055 679 SEGC₉₇

1055 680 SEGA₉₈

1055 681 SEGB₉₈

1055 682 SEGC₉₈

1055 683 SEGA₉₉

1055 684 SEGB₉₉

1055 685 SEGC₉₉

1055 686 SEGA₁₀₀

1055 687 SEGB₁₀₀

1055 688 SEGC₁₀₀

1055 689 SEGA₁₀₁

1055 690 SEGB₁₀₁

1055 691 SEGC₁₀₁

1055 692 SEGA₁₀₂

1055 693 SEGB₁₀₂

1055 694 SEGC₁₀₂

1055 695 SEGA₁₀₃

1055 696 SEGB₁₀₃

1055 697 SEGC₁₀₃

1055 698 DMY₁₀₆

1055 699 DMY₁₀₇

1055 700 DMY₁₀₈

1055 701 COM₄₀

1055 702 COM₄₁

1055 703 COM₄₂

1055 704 COM₄₃

1055 705 COM₄₄

1055 706 COM₄₅

1055 707 COM₄₆

1055 708 COM₄₇

1055 709 COM₄₈

1055 710 COM₄₉

1055 711 COM₅₀

1055 712 COM₅₁

1055 713 COM₅₂

1055 714 COM₅₃

-5512.5

-5557.5

-5602.5

-5647.5

-5692.5

-5737.5

-5782.5

-5827.5

-5872.5

-5917.5

-5962.5

-6007.5

-6052.5

-6097.5

-6142.5

-6187.5

-6232.5

-6277.5

-6322.5

-6367.5

-6412.5

-6457.5

-6502.5

-6547.5

-6592.5

-6637.5

-6682.5

-6727.5

-6772.5

-6817.5

-6862.5

-6907.5

-6952.5

-6997.5

-7042.5

-7087.5

-7132.5

-7177.5

-7222.5

-7267.5

-7312.5

-7357.5

-7402.5

-7447.5

-7492.5

-7537.5

-7582.5

-7627.5

-7672.5

-7717.5

-7762.5

1055

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

DMY₁₀₉

DMY₁₁₀

DMY₁₁₁

DMY₁₁₂

DMY₁₁₃

DMY₁₁₄

-7807.5

-7852.5

-7897.5

-7942.5

-7987.5

-8032.5

-8077.5

-8122.5

-8167.5

-8212.5

-8257.5

-8302.5

-8347.5

-8392.5

-8437.5

-8482.5

-8527.5

-8572.5

-8617.5

-8662.5

-8707.5

-8752.5

-8797.5

-8842.5

-8887.5

-8932.5

-8977.5

-9022.5

-9067.5

-9430

1055

-784

-829

-874

-919

-964

-9430

- 10 -

NJU6818

ꢀ BLOCK DIAGRAM

V_SSH

V_SS

V_SSA

V_DDA

V_DD

Segment Driver

Common Driver

5

V_LCD, V₁-V₄

Gradation Circuit

Data Latch Circuit

Shift Register

C₁+

C₁-

C₂+

Voltage

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

booster

V_OUT

Voltage

regulator

V_EE

Display Data RAM

(DD RAM)

V_REF

V_BA

80x104x(4+4+4)bit

V_REG

D₁₅

D₁₄

D₁₃

D₁₂

D₁₁

D₁₀

D₉

X Address Decoder

X Address Counter

X Address Register

FR

RAM

Display

Timing

Interface

FLM

CL

Generator

CLK

OSC₂

OSC₁

D₈

Oscillator

D₇

D₆

D₅

D₄/SPOL

D₃/SMODE

D₂

Instruction

Decoder

Register Read

Control

Bus Holder

Internal Bus

Pole Control

D₁/SDA

D₀/SCL

MPU Interface

Chip

Identification

CSb RS

RDb WRb P/S

SEL68 RESb

- 11 -

NJU6818

ꢁPOWER SUPPLY CIRCUITS BLOCK DIAGRAM

Reference Voltage

+

-

Generator

V_BA

+

-

V_LCD

+

-

Voltage regulator

V₁

V_REG

V_REF

+

-

+

-

V₂

Gain

+

-

V₃

Control

(1x-6x)

E.V.R

1/2V_REG

+

-

V₄

EVR register

Boost level register

C₁+

C₁-

C₂+

C₂-

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

Voltage

Booster

V_OUT

V_EE

- 12 -

NJU6818

ꢀ TERMINAL DESCRIPTION 1

No.

Symbol

V_DD

I/O

Function

123~131

151~159

231~239

4,5

Power

Power supply for logic circuits

V_SS

GND for logic circuits

V_SSH

V_DDA

GND for high voltage circuits

This terminal is internally connected to the V_DDlevel.

• This terminal is used to fix the selection terminals to the V_DD

level.

33,34

67,68

Note) Do not use this terminal for a main power supply.

This terminal is internally connected to the V_SSlevel.

• This terminal is used to fix the selection terminals to the V_SS

level.

26,27

40,41

97,98

V_SSA

Power

Note) Do not use this terminal for a main GND.

161~168

V_LCD

Power/O LCD driving voltages

• When the internal voltage booster is not used, the external

170~177

178~185

187~194

195~202

V₁

V₂

V₃

V₄

LCD driving voltages (V₁to V₄and V_LCD) must be supplied on

these terminals. And the external voltages must be maintained

with the following relation.

V_SS<V₄<V₃<V₂<_V1<V_LCD

• When the internal voltage booster is used, the LCD driving

voltages (V₁to V₄and V_LCD) are enabled by the “Power control”

instruction. The capacitors between the Vss and these terminals

are necessary.

263~267

270~274

277~281

284~288

291~295

298~302

305~309

312~216

319~323

326~330

222~229

213~220

249~257

C₁+

C₁-

O

Capacitor connection terminals for the voltage booster

C₂+

C₂-

Capacitor connection terminals for the voltage booster

C₃+

C₃-

C₄+

C₄-

C₅+

C₅-

V_BA

V_REF

V_EE

O

I

Power

Output of the reference-voltage generator

Input of the voltage regulator

Input of the voltage booster

• This terminal is normally connected to the V_DDlevel.

240~248

V_OUT

Power/O Output of the voltage booster

Input for high voltage circuits in using external power supply

Output of the voltage regulator

204~211

43,44

V_REG

RESb

O

I

Reset

Active “0”

29,30

SEL68

I

MPU interface type select

SEL86

Status

H

L

68 series

80 series

ID₀

ID₁

ID₂

ID₃

I

Chip Identification

7,8

This terminal must be fixed to “1” or “0”

13,14

17,18

23,24

The NJU6818 can read ID data, which is determined by fixing

ID₃, ID₂, ID₁and ID₀pins to “1” or “0”.

- 13 -

NJU6818

ꢀ TERMINAL DESCRIPTION 2

No.

Symbol

D₀/SCL

I/O

Function

74,75

Parallel interface:

D₇to D₀: 8-bit bi-directional bus

• In the parallel interface mode (P/S=“1”), these terminals connect

to 8-bit bi-directional MPU bus.

76,77

82,83

D₁/SDA

I/O

Serial interface:

SDA : Serial data

D₃/SMODE

SCL : Serial clock

SMODE : 3-/4-line serial interface mode selection

SPOL : RS polarity selection (in the 3-line serial interface mode)

86,87

D₄/SPOL

I/O

• In the 3-/4-line serial interface mode (P/S=“0”), the D0 terminal

is assigned to the SCL, and the D₁terminal to the SDA.

• In the 3-line serial interface mode, the D₄terminal is assigned to

the SPOL.

80.81

88,89

92,93

94,95

D₂

D₅

D₆

D₇

• Serial data on the SDA is fetched at the rising edge of the SCL

signal in the order of the D₇, D₆…D₀, and the fetched data is

converted into 8-bit parallel data at the falling edge of the 8th SCL

signal.

• The SCL signal must be set to “0” after data transmissions or

during non-access.

100,101

102,103

106,107

108,109

112,113

114,115

118,119

120,121

49,50

D₈

D₉

I/O

8-bit bi-directional bus

• In the 16-bit data bus mode, these terminals are assigned to the

upper 8-bit data bus.

D₁₀

D₁₁

D₁₂

D₁₃

D₁₄

D₁₅

CSb

• In the serial interface mode or the 8-bit data bus mode of the

parallel interface, these terminals must be fixed to “1” or “0”.

I

Chip select

Active “0”

53,54

RS

Resister select

•This signal distinguishes transferred data as an instruction or

display data as follows.

RS

Distinct.

H

L

Instruction

Display data

63,64

59,60

RDb (E)

I

80 series MPU interface (P/S=“1”, SEL68=“0”)

RDb signal. Active “0”.

68 series MPU interface (P/S=“1”, SEL68=“1”)

Enable signal. Active “1”.

80 series MPU interface (P/S=“1”, SEL68=“0”)

WRb signal. Active “0”.

WRb (R/W)

68 series MPU interface (P/S=“1”, SEL68=“1”)

R/W signal.

R/W

Status

H

Read

L

Write

- 14 -

NJU6818

ꢀ TERMINAL DESCRIPTION 3

No.

37,38

Symbol

P/S

I/O

I

Function

Parallel / serial interface mode selection

Chip

Data/

Read/

Write

RDb,

WRb

Write

only

P/S

H

Data

Serial clock

-

Select

Instruction

CSb

RS

D₀~ D₇

SDA (D1)

L

SCL (D0)

• Since the D₁₅to D₅and D₂terminals are in high impedance in the

serial interface mode (P/S=“0”), they must be fixed to “1” or “0”. The

RDb and WRb terminals also must be “1” or “0”.

133,134

135,136

139,140

141,142

CL

FLM

FR

O

This terminal must be opened.

CLK

145,146

OSC₁

I

OSC

149,150

OSC₂

O

• When the internal oscillator clock is used, the OSC₁terminal must be

fixed to “1” or “0”, and the OSC₂terminal must be opened. When the

oscillation frequency from the internal oscillator is adjusted by an

external resistor between OSC₁terminal and OSC₂.

• When an external oscillator is used, external clock is input to the

OSC₁terminal, or an external resistor is connected between the OSC₁

and OSC₂terminals.

386~697 SEGA₀

~SEGA₁₀₃

SEGB₀~

SEGB₁₀₃

SEGC₀~

O

Segment output

,

REV Mode

Normal

Reverse

Turn-off

Turn-on

0

1

0

SEGC₁₀₃

• These terminals output LCD driving waveforms in accordance with the

combination of the FR signal and display data.

In the B/W mode

FR signal

Display data

Normal display mode

V₂

V_LCD

V₂

V ₃

V_SS

V₃

Reverse display mode

V_LCD

V_SS

343~382 COM₀~

701~740

O

Common output

COM₇₉

• These terminals output LCD driving waveforms in accordance with the

combination of the FR signal and scanning data.

Data

H

L

H

L

FR

H

L

Output level

V_SS

V₁

V_LCD

V₄

L

(Terminal No. 1~3,6, 9~12, 15, 16, 19~22, 25, 28, 31, 32, 35, 36, 39, 42, 45~48, 51, 52, 55~58, 61, 62, 65, 66, 69~73, 78, 79, 84, 85, 90,

91, 96, 99, 104, 105, 110, 111, 116, 117, 122, 132, 137, 138, 143, 144, 147, 148, 160, 169, 186, 203, 212, 221, 230, 258~262, 268, 269,

275, 276, 282, 283, 289, 290, 296, 297, 303, 304, 310, 311, 317, 318, 324, 325, 331~342, 383~385, 698~700, 741~748 are dummy.)

- 15 -

NJU6818

ꢀ Functional Description

(1) MPU Interface

(1-1) Selection of parallel / serial interface mode

The P/S terminal is used to select the parallel or serial interface mode, as shown in the following table. In the serial

interface mode, it is not possible to read out display data from the DDRAM or status data from the internal

registers.

Table 1

P/S

H

L

P/S mode

Parallel I/F

Serial I/F

CSb

RS

RDb

-

WRb

-

SEL68

-

SDA

SCL

Data

D7-D0 (D15-D0)

-

Note 1) “ -” : Fix to “1” or “0”.

(1-2) Selection of MPU interface type

In the parallel interface mode, the SEL68 terminal is used to select 68- or 80-series MPU interface type, as shown

in the following table.

Table 2

SEL68

MPU type

68 series MPU

80 series MPU

CSb

RS

RDb

E

RDb

WRb

R/W

WRb

Data

D7-D0 (D15-D0)

H

L

(1-3) Data distinction

In the parallel interface mode, the combination of the RS, RDb and WRb (R/W) signals distinguishes transferred

data between the LSI and MPU as instruction or display data, as shown in the following table.

Table 3

68 series

80 series

RS

Function

R/W

H

RDb

WRb

H

L

H

L

H

L

Read out instruction data

Write instruction data

Read out display data

Write display data

L

H

L

H

(1-4) Selection of serial interface mode

In the serial interface mode, the SMODE terminal is used to select the 3- or 4-line serial interface mode, as shown

in the following table.

Table 4

SMODE

Serial interface mode

H

L

3-line

4-line

- 16 -

NJU6818

(1-5) 4-line serial interface mode

In the 4-line serial interface mode, when the chip select is active (CSb=“0”), the SDA and the SCL are enabled.

When the chip select is not active (CSb=“1”), the SDA and the SCL are disabled, and the internal shift register and

the counter are being initialized. 8-bit serial data on the SDA is fetched at the rising edge of the SCL signal (serial

clock) in order of the D₇, D₆…D₀, and the fetched data is converted into 8-bit parallel data at the rising edge of the

8th SCL signal.

In the 4-line serial interface mode, transferred data on the SDA is distinguished as display data or instruction data

in accordance with the condition of the RS signal.

Table 5

RS

H

L

Data distinction

Instruction data

Display data

Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after data

transmissions or during non-access. To release a mal-function caused by the external noises, the chip-selected

status should be released (CSb=“1”) after each of 8-bit data transmissions. The following figure illustrates the

interface timing of the 4-line serial interface operation.

CSb

RS

VALID

D₀

SDA

D₇

1

D₆

2

D₅

3

D₄

4

D₃

5

D₂

D₁

SCL

6

7

8

Fig 1

4-line serial interface timing

(1-6) 3-line serial interface mode

In the 3-line serial interface mode, when the chip select is active (CSb=“0”), the SDA and the SCL are enabled.

When the chip select is not active (CSb=“1”), the SDA and the SCL are disabled, and the internal shift register and

counter are being initialized. 9-bit serial data on the SDA is fetched at the rising edge of the SCL signal in order of

the RS, D₇, D₆…D₀, and the fetched data is converted into 9-bit parallel data at the rising edge of the 9th SCL

signal.

In the 3-line serial interface mode, data on the SDA is distinguished as display data or instruction data in

accordance with the condition of the RS bit of the SDA data and the status of the SPOL, as follows.

Table 6

SPOL=L

SPOL=H

RS

L

H

Data distinction

RS

L

H

Data distinction

Display data

Instruction data

Display data

- 17 -

NJU6818

Since the serial interface operation is sensitive to external noises, the SCL must be set to “0” after data

transmissions or during non-access. To release a mal-function caused by the external noises, the chip-selected

status should be released (CSb=“1”) after each of 9-bit data transmissions. The following figure illustrates the

interface timing of the 3-line serial interface operation.

CSb

SDA

SCL

RS

1

D₇

2

D₆

D₅

4

D₄

5

D₃

D₂

D₁

D₀

3

6

7

8

9

Fig 2 3-line serial interface timing

- 18 -

NJU6818

(2) Access to the DDRAM

When the CSb signal is ”0”, transferred data from MPU is written into the DDRAM or the instruction register in

accordance with the condition of the RS signal.

When the RS signal is “1”, the transferred data is distinguished as display data. After the “column address” and

“row address” instructions are executed, display data can be written into the DDRAM by the “Display data write”

instruction. The display data is written at the rising edge of the WRb signal in the 80 series MPU mode, or at the

falling edge of the E signal in the 68 series MPU mode.

Table 6

RS

L

H

Data distinction

Display RAM Data

Internal Command Register

In the sequence of the “Display data read” operation, transferred data from MPU is temporarily held in the internal

bus-holder, then transferred to the internal data-bus. When the “Display data read” operation is executed just after

the “column address” and “row address” instructions or “Display data write” instruction, unexpected data on the

bus-holder is read out at the 1st execution, then the data of designated DDRAM address is read out from the 2nd

execution. For this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read.

Display data write operation

n

n+1

n+2

n+3

n+4

D₀to D₁₅

WRb

n

n+1

n+2

n+3

n+4

Bus Holder

WRb

Display data read operation

WRb

D₀to D₇(D₀to D₁₅)

n

n+1

Data Read

n+1 Address n+2 Address

n+2

Data Read

Address Set

n

Dummy

Read

Data Read

n Address

RDb

Fig 3

Note) In the 16-bit data bus mode, instruction data must be 16-bit as well as the display data.

- 19 -

NJU6818

(3) Access to the instruction register

Each instruction resisters is assigned to each address between 0_Hand F_H, and the content of the instruction

register can be read out by the combination of the “Instruction resister address” and ”Instruction resister read”.

WRb

M

m

N

n

D₀to D₇

Instruction resister

Instruction resister Instruction resister Instruction resister

address set

contents read

address set

contents read

RDb

Fig 4

(4) 8-/16-bit data bus length for display data (In the parallel interface mode)

The 8- or 16-bit data bus length for display data is determined by the “WLS” of the “Data bus length” instruction.

In the 16-bit data bus mode, instruction data must be 16-bit (D₁₅to D₀) as well as display data. However, for the

access to the instruction register, the only lower 8-bit data (D₇to D₀) of 16-bit data is valid. For the access to the

DDRAM, all of the 16-bit data (D₁₅to D₀) is valid.

Table 8

WLS

L

H

Data bus length mode

8-bit

16-bit

(5) Initial display line register

The initial display line resister specifies the line address, corresponding to the initial COM line, by the “Initial display

line” instruction. The initial COM line signifies the common driver, starting scanning the display data in the DDRAM,

and specified by the “Initial COM line” instruction.

The line address, established in the initial display line resister, is preset into the line counter whenever the FLM

signal becomes “1”. At the rising edge of the CL signal, the line counter is counted-up and addressed 312-bit

display data, corresponding to the counted-up line address, is latched into the data latch circuit. At the falling edge

of the CL signal, the latched data outputs to the segment drivers.

- 20 -

NJU6818

(6) DDRAM Mapping

The DDRAM is capable of 1,248-bit (12-bit x 104-segment) for the column address and 80-bit for the row address.

In the gradation mode, each pixel for RGB corresponds to successive 3-segment drivers, and each segment driver

has 16-gradation. Therefore, the LSI can drive up to 104x80 pixels in 4096-color display (16-gradation x 16-

gradation x 16-gradation).

In the B&W mode, only MSB data from each 4-bit display data group in the DDRAM is used. Therefore, 312x80

pixels in the B&W and 104x80 pixels in the 8-gradiation are available.

The range of the column address varies depending on data bus length. The range between 00_Hand CF_His used in

the 8-bit data bus length, and the range between 00_Hand 67_His in the 16-bit data bus length.

ꢀ

In the 8-bit data bus length mode

column-address

0_H

7bit

1_H

CE_H

7bit

CF_H

5bit

0 _H

5bit

row-address

4F_H

0 _H

7bit

5bit

7bit

5bit

0_H

4bit

1_H

8bit

CE_H

4bit

CF_H

8bit

ABS=’1’

row-address

4F_H

0 _H

4bit

8bit

4bit

8bit

0_H

8bit

1_H

8bit

9A_H

8bit

9B_H

8bit

HSW=’1’

row-address

4F_H

0 _H

8bit

0_H

8bit

1_H

8bit

66_H

8bit

67_H

8bit

C256=’1’

row-address

4F_H

8bit

Fig 5

- 21 -

NJU6818

ꢀ

In the 16-bit data bus length mode

column-address

0_H

67_H

12bit

0 _H

12bit

row-address

4F_H

12bit

Fig 6

The increments for the column address and row address are set to the auto-increment mode by programming the

“AXI” and “AYI” registers of the “Increment control” instruction. In this mode, the contents of the column address

and row address counters automatically increment whenever the DDRAM is accessed.

The column address and row address counters, independent of the line counter. They are used to designate the

column and row addresses for the display data transferred from MPU. On the other hand, the line counter is used

to generate the line address, and output display data to the segment drivers, being synchronized with the display

control timing of the FLM and CL signals.

- 22 -

NJU6818

(7) Window addressing mode

In addition to the above usual DDRAM addressing, it is possible to access some part of DDRAM in using the

window addressing mode, in which the start and end points are designated. The start point is determined by the

“column address” and “row address” instructions, and the end point is determined by the “Window end column

address “and ”Window end row address” instructions. The setting example of the window addressing is listed, as

follows.

1. Set WIN=1, AXI=1, and AYI=1 by the “Increment control” instruction

2. Set the start point by the “column address” and “row address” instructions

3. Set the end point by the “Window end column address” and “Window end row address” instructions

4. Enable to access to the DDRAM in the window addressing mode

In the window addressing mode (WIN=1, AXI=1, AYI=1), the read-modify-write operation is available by setting “0”

to the “AIM” register of the “Increment control” instruction.

And in the window addressing mode, the following relation for the start and end points must be maintained to avoid

a malfunction.

AX (column address of start point) < EX (column address of the end point) < Maximum of column

address

AY (row address of start point) < EY (row address of the end point) < Maximum of row address

column address

(X, Y)

Start point

End point

Window display area

(X, Y)

Whole DDRAM area

Fig 7

(8) Reverse display ON/OFF

The “Reverse display ON/OFF” function is used to reverse the display data without changing the contents of the

DDRAM.

Table 9

REV

Display

Normal

DDRAM data → Display data

0

1

0

1

0

1

0

1

Reverse

(9) Segment direction

The “Segment direction” function is used to reverse the assignments for the segment drivers and the column

addresses, and it is possible to reduce restrictions for the placement of the LSI on LCD modules.

- 23 -

NJU6818

REF

SWAP

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

WLS

ABS

HSW

REF

256

WLS

ABS

HSW

REF

256

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

A3

A2

A1

A0

B3

B2

B1

B0

C3

C2

C1

C0

- 24 -

NJU6818

(10) The relation among the DDRAM column address, display data, and segment drivers

In the color mode and 16-bit data bus mode

HSW ABS REF SWAP

Column address / bit / segment assign

*

0

1

0

1

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

*

0

1

0

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

*

1

0

1

0

1

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

*

1

0

1

0

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

- 25 -

NJU6818

In the color mode and 8-bit data bus mode

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

1

X=00_H

X=CE_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

X=00_H

X=CE_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

1

0

1

X=00_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=CE_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

1

0

X=00_H

X=CE_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=01_H

ꢂꢃ

- 26 -

NJU6818

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

SEGA

0

SEGC

0

SEGC

0

SEGA

0

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

SEGB

0

SEGB

0

SEGB

0

SEGB

0

SEGC

0

SEGA

0

SEGA

0

SEGC

0

SEGA

1

SEGC

1

SEGC

1

SEGA

1

SEGB

1

SEGB

1

SEGB

1

SEGB

1

SEGC

1

SEGA

1

SEGA

1

SEGC

1

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

SEGA

102

SEGC

102

SEGC

102

SEGA

102

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

Palette A

Palette B

Palette C

SEGB

102

SEGB

102

SEGB

102

SEGB

102

SEGC

102

SEGA

102

SEGA

102

SEGC

102

SEGA

103

SEGC

103

SEGC

103

SEGA

103

SEGB

103

SEGB

103

SEGB

103

SEGB

103

SEGC

103

SEGA

103

SEGA

103

SEGC

103

- 27 -

NJU6818

In the color mode, 8-bit data bus mode, and C256 mode (C256=1)

HSW ABS REF SWAP

Column address / bit / segment assign

*

0

1

0

1

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

*

0

1

0

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

- 28 -

NJU6818

In the B&W mode and 16-bit data bus mode

HSW ABS REF SWAP

Column address / bit / segment assign

*

0

1

0

1

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

*

0

1

0

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

*

1

0

1

0

1

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

*

1

0

1

0

X=00_H

X=67_H

ꢂꢃ

X=67_H

X=00_H

ꢂꢃ

- 29 -

NJU6818

In the B&W mode and 8-bit data bus mode

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

1

X=00_H

X=CE_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

X=00_H

X=CE_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=01_H

0

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

1

0

1

X=00_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=CE_H

X=01_H

ꢂꢃ

HSW ABS REF SWAP

Column address / bit / segment assign

0

1

0

1

0

X=00_H

X=CE_H

X=01_H

X=CF_H

ꢂꢃ

X=CE_H

X=00_H

X=CF_H

X=01_H

ꢂꢃ

- 30 -

NJU6818

SEGA 0

SEGB 0

SEGC 0

SEGA 1

SEGB 1

SEGC 1

SEGC 0

SEGB 0

SEGA 0

SEGC 1

SEGB 1

SEGA 1

SEGC 0

SEGB 0

SEGA 0

SEGC 1

SEGB 1

SEGA 1

SEGA 0

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

SEGB 0

SEGC 0

SEGA 1

SEGB 1

SEGC 1

SEGA 102

SEGB 102

SEGC 102

SEGA 103

SEGB 103

SEGC 103

SEGC 102

SEGB 102

SEGA 102

SEGC 103

SEGB 103

SEGA 103

SEGC 102

SEGB 102

SEGA 102

SEGC 103

SEGB 103

SEGA 103

SEGA 102

SEGB 102

SEGC 102

SEGA 103

SEGB 103

SEGC 103

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

- 31 -

NJU6818

Bit assignments between write and read data (In the 16-bit data bus mode)

ABS=0

Write data

Read data

D₁₅

D₁₄

D₁₃

D₁₂

D₁₁

*

D₁₀

D₉

D₈

D₇

D₆

*

D₅

*

D₄

D₃

D₂

D₁

D₀

*

ABS=1

Write data

D₁₅

*

D₁₄

*

D₁₃

*

D₁₂

*

D₁₁

D₁₀

D₉

D₈

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

Examples of write and read data (In the 8 bit bus mode)

ABS=0, HSW=0, C256=0 (Address; 00, 02……CC,CE_H)

Write data

Read data

D₇

D₆

D₅

D₄

D₃

*

D₂

D₁

D₀

ABS=0, HSW=0, C256=0 (Address; 01,03_H……CD,CF_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

1

Read data

D₇

*

D₄

D₃

D₂

D₁

ABS=1, HSW=0, C256=0 (Address; 00, 02……CC,CE_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

*

D₃

D₂

D₁

ABS=1, HSW=0, C256=0 (Address; 01,03_H…… CD,CF_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

ABS=0, HSW=1, C256=0 (Address; 00, 01……9A,9B_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

ABS=0, HSW=0, C256=1 (Address; 00, 01…… 66 ,67_H)

Write data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Read data

D₇

D₆

D₅

D₄

D₃

D₂

D₁

*: Invalid Data

- 32 -

NJU6818

(11) Gradation palette

In the gradation mode, either variable or fixed gradation mode is selected by programming the “PWM” register of

the “Gradation control” instruction.

PWM=0:

PWM=1:

Variable gradation mode

(Select 16-gradation level out of 32-gradation level of the gradation palette)

Fixed gradation mode

(Fixed 8-gradation level)

In these modes, each of the gradation palettes of the Aj, Bj and Cj can select 16-gradation level out of 32-

gradation level by setting 5-bit data to the “PA” registers in the “Gradation palette j” instructions (j=0 to Fh).

For instance, the gradation palettes Aj correspond to the SEGAi, the Bj to the SEGBj, and the Cj to the SEGCi (j=0

to 15, i=0 to 103).

- 33 -

NJU6818

Correspondence between display data and gradation palettes

Table 10 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))

(MSB) Display data (LSB)

Gradation palette

Palette 0

Palette 1

Palette 2

Palette 3

Palette 4

Palette 5

Palette 6

Palette 7

Palette 8

Palette 9

Palette10

Palette11

Palette12

Palette13

Palette14

Palette15

Default palette value

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0 1

0 1 0 1 1

0 1 1 0 1

0 1 1 1 1

1 0 0 0 1

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gradation palette table (Variable gradation mode, PWM=”0”, MON=”0”)

Table 11 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))

Palette

Gradation

Palette

Gradation

level

Gradation palette

Palette 0(default)

Gradation palette

value

level

value

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

0

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

1 1 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

16/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

1/31

2/31

3/31

4/31

5/31

6/31

7/31

8/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

Palette 8(default)

Palette 9(default)

Palette 10(default)

Palette 11(default)

Palette 12(default)

Palette 13(default)

Palette 14(default)

Palette 15(default)

Palette 1(default)

Palette 2(default)

Palette 3(default)

Palette 4(default)

Palette 5(default)

Palette 6(default)

Palette 7(default)

- 34 -

NJU6818

Gradation palette table (Fixed gradation mode, PWM=”1”, MON=”0”)

Table 12 8-gradation segment drivers

Gradation

(MSB) Display data (LSB)

Gradation

(MSB) Display data (LSB)

level

0/7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

0/7

1/7

2/7

3/7

4/7

5/7

6/7

7/7

0

1

0

1

0

1

*

3/7

5/7

7/7

Correspondence between display data and gradation level (B&W mode, MON=”1”)

Table 13

Gradation

(MSB) Display data (LSB)

level

0

*

0

1

*

*:Don’t care

- 35 -

NJU6818

(12) Gradation control and display data

(12-1) Gradation mode

In the graduation mode, each pixel for RGB corresponds to successive 3 segment-drivers, and each segment

driver provides 16-gradation PWM output by controlling 4-bit display data of the DDRAM. Accordingly, the LSI can

drive up to 104x80 pixels in 4096-color (16-gradation x 16-gradation x 16-gradation = 4-bit x 4-bit x 4-bit).

In addition, the LSI can transfer the display data for the RGB by 16-bit at once or 8-bit two times. The data

assignment between gradation palettes and segment drivers varies in accordance with setting for the “SWAP” and

“REF” registers of the "Display control (2)" instruction.

(REF, SWAP)=(0, 0) or (1, 1)

SEGAi

SEGBi

SEGCi

(i=0 to 103)

Gradation palette

j=0 to 15

PaltetetteAAj j

PaletteBj

PaletteCj

Gradation control circuit

Display data in DDRAM

01

MSB

01

0

01

0

10

1

10

1

10

LSB

LSB MSB

0

1

Display data from MPU

Column address:2n_H:2n+1_H

D₇

D₆

D₅

D₁

D₅

D₄

D₀

D₄

*

D₂

D₇

D₃

D₄

D₁

D₆

D₂

D₃

D₀

D₅

D₁

D₂

D₇

D₄

D₀

*

D₄

D₃

D₇

D₁

D₃

D₂

D₆

D₀

D₂

D₁

D₅

*

D₁

ABS=1

HSW=1

C256=1

(D₃D₂

(D₇D₆

D₀)

D₄)

* )

Note) DDRAM column address :2n_H,2n_H+1_H

(REF=”0”)

(REF=”1”)

:CE_H-2n_H, CF_H-(2n_H+1_H)

HSW=1; 00_Hto 9B_H

C256=1; 00_Hto 67_H

(REF, SWAP)=(0, 1) or (1, 0)

SEGAi

SEGBi

SEGCi

(i=0 to 103)

Gradation palette

j=0 to 15

PaletteAj

PaletteBj

PaletteCj

Gradation control circuit

1

LSB

1

0

1

0

1

0

1

0

MSB

Display data in DDRAM

MSB LSB

0

1

Display data from MPU

Column address:2n_H:2n+1_H

D₇

D₆

D₅

D₁

D₅

D₄

D₀

D₄

*

D₂

D₇

D₃

D₄

D₁

D₆

D₂

D₃

D₀

D₅

D₁

D₂

D₇

D₄

D₀

*

D₄

D₃

D₇

D₁

D₃

D₂

D₆

D₀

D₂

D₁

D₅

*

D₁

ABS=1

HSW=1

C256=1

(D₃D₂

(D₇D₆

D₀)

D₄)

* )

Note) DDRAM column address : 2n_H,2n_H+1_H

(REF=”0”)

(REF=”1”)

: CE_H-2n_H, CF_H-(2n_H+1_H)

HSW=1; 00_Hto 9B_H

C256=1; 00_Hto 67_H

- 36 -

NJU6818

In the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in

accordance with setting for the “SWAP” and “REF” bits of the "Display control (2)" instruction as well as the

assignment in the 8-bit data bus mode.

(REF, SWAP)=(0, 0) or (1, 1)

SEGAi

SEGBi

SEGCi

(i=0 to 103)

Gradation palette

j=0 to 15

PaletteAj

PaletteBj

PaletteCj

Gradation control circuit

0

MSB

0

1

LSB

Display data in DDRAM

LSB MSB

Display data from MPU

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

(D₁₁D₁₀D₉D₈D₇D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀)

; n

Column address

H

ABS=1

Note) DDRAM column address :n_H

(REF=”0”)

:67_H- n_H(REF=”1”)

(REF, SWAP)=(0, 1) or (1, 0)

SEGAi

SEGBi

SEGCi

i=0 to 103

Gradation palette

j=0 to 15

PaletteAj

PaletteBj

PaletteCj

Gradation control circuit

Display data in DDRAM

1

LSB

1

0

1

0

1

0

1

0

1

0

MSB

MSB LSB

Display data from MPU

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

(D₁₁D₁₀D₉D₈D₇D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀)

; n

Column address

H

ABS=1

Note) DDRAM column address :n_H

(REF=”0”)

:67_H-n_H(REF=”1”)

- 37 -

NJU6818

(12-2) B&W mode (MON=”1”)

In the B&W mode, 3 bits of the MSB data are used in both of the 16-bit and 8-bit data bus modes.

In the 16-bit data bus mode (Similarly 8-bit data bus access)

(REF, SWAP)=(0, 0) or (1, 1)

SEGAi

SEGBi

SEGCi

(i=0 to 103)

Gradation palette

j=0 to 15

PaletteAj

PaletteBj

PaletteCj

Gradation control circuit

Display data in DDRAM

0

MSB

0

1

LSB

LSB MSB

Display data in DDRAM

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

(D₁₁D₁₀D₉D₈D₇D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀)

n

Column address;

H

ABS=1

Note) DDRAM column address : n_H

: 67_H-n_H

(REF=”0”)

(REF=”1”)

(REF, SWAP)=(0, 1) or (1, 0)

SEGAi

SEGBi

SEGCi

(i=0 to 103)

Gradation palette

j=0 to 15

PaletteAj

PaletteBj

PaletteCj

Gradation control circuit

Display data in DDRAM

1

0

1

0

1

0

1

0

1

0

LSB

MSB LSB

MSB

Display data in DDRAM

0

1

D₁₅D₁₄D₁₃D₁₂D₁₀D₉

(D₁₁D₁₀D₉D₈D₇D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀)

n

Column address;

H

D₄

ABS=1

4

Note ) DDRAM column address: n_H

: 67_H-n_H

(REF=”0”)

(REF=”1”)

- 38 -

NJU6818

(13) Display timing generator

The display-timing generator creates the timing pulses such as the CL, the FLM, the FR and the CLK by dividing

the oscillation frequency oscillate an external or internal resister mode. The each of timing pulses is outputted

through the each output terminals by “SON”=1.

(14) LCD line clock (CL)

The LCD line clock (CL) is used as a count-up signal for the line counter and a latch signal for the data latch circuit.

At the rising edge of the CL signal, the line counter is counted-up and 312-bit display data, corresponding to this

line address, is latched into the data latch circuit. And at the falling edge of the CL signal, this latched data output

on the segment drivers. Read out timing of the display data, from DDRAM to the latch circuits, is completely

independent of the access timing to MPU. For this reason, the MPU can access to the LSI regardless of an

internal operation.

(15) LCD alternate signal (FR) and LCD synchronous signal (FLM)

The FR and FLM signals are created from the CL signal. The FR signal is used to alternate the crystal polarization

on a LCD panel. It is programmed that the FR signal is toggle on every frame in the default setting or once every N

lines in the N-line inversion mode. The FLM signal is used to indicate a start line of a new display frame. It presets

an initial display line address of the line counter when the FLM signal becomes ”1”.

(16) Data latch circuit

The data latch circuit is used to temporarily store the display data that will output on the segment drivers. The

display data in this circuit is updated in synchronization of the CL signal.

The “All pixels ON/OFF”, “Display ON/OFF” and “Reverse display ON/OFF” instructions change the display data in

this circuit but do not change the display data of the DDRAM.

(17) Common and segment drivers

The LSI includes 312-segment drivers and 80-common drivers. The common drivers generate LCD driving

waveforms composed of the V_LCD, V₁, V₄and V_SSin accordance with the FR signal and scanning data. The

segment drivers generate waveforms composed of the V_LCD, V₂, V₃and V_SSin accordance with the FR signal and

display data.

(18) Chip Identification (ID)

The NJU6818 can read ID data, which is determined by fixing ID3, ID2, ID1 and ID0 pins to “1” (V_DD) or “0” (V_SS).

When the parallel interface is used, the ID data can be read out through the D₇, D₆, D₅and D₄pins as upper 4-bit

data of the internal register. When the serial interface is used, the ID data can be read out as follows.

In the 4-line serial interface mode, “ID read-out instruction” must be set by IDR=1 during the SDA and SCL pins

are enabled by CS=1. First, the serial data on the SDA must be input at the rising edge of the SCL clock, next the

SDA must be in high-impedance (Hi-Z) at the falling edge of the 8^thSCL clock. From the rising edge of the 9^thSCL

clock, the ID data such as ID3, ID2, ID1 and ID0 is read out. The serial data after the ID0 is undefined, and this

reading mode is returned to the writing mode at the rising edge of the 16^thSCL clock. The serial data on the SDA

at the 8^thand 16^thSCL clocks applies specified serial interface timing.

In the 3-line serial interface mode, the SDA must be in high-impedance (Hi-Z) at the falling edge of the 9^thSCL

clock. From the rising edge of the 10^thSCL clock, the ID data is read out as well as operation in the 4-line serial

interface mode. The serial data after ID0 is undefined, and this reading mode is returned to the writing mode at the

rising edge of the 18^thSCL clock. The serial data on the SDA at the 9^thand 18^thSCL clocks applies specified serial

interface timing.

Note) Refer to the “Serial Interface Timing” for the detail

- 39 -

NJU6818

ID Read in the 4-Line serial interface mode

CSb

RS

VALID

un-

SDA

SCL

D₇

1

D₆

2

D₀

ID₃

ID₂

ID₁

ID₀

unfixed

･･･

Hi-z

9

･･･

fixed

8

10

11

12

･･･

15

16

ID Read in the 4-Line serial interface mode

CSb

SDA

un-

unfixed

RS

1

D₇

2

D₀

9

ID₃

ID₂

ID₁

ID₀

Hi-z

･･･

fixed

SCL

10

11

12

13

･･･

17

18

- 40 -

NJU6818

ꢁ LCD Driving waveforms (In the B&W mode, Reverse display OFF, 1/81 duty)

COM₀

1

2

3

4

5

1

2

3

4

5

1

81

COM₁

CL

FLM

FR

V_LCD

V₁

V₂

COM₀

V₃

V₄

V_SS

V_LCD

V₁

V₂

COM₁

SEG₀

V₃

V₄

V_SS

V_LCD

V₁

V₂

V₃

V₄

V_SS

V_LCD

V₁

SEG₁

V₂

V₃

V₄

V_SS

Fig 8

- 41 -

NJU6818

(19) Oscillator

The oscillator generates internal clocks for the display timing and the voltage booster. Since the LSI has internal

capacitor (C) and resistor (R) for the oscillation, external capacitor and resistor are not usually required. However,

in case that an external resistor is used, the resister is connected between the OSC₁and OSC₂terminals. The

external resistor becomes enabled by setting “1” to the “CKS” register of “Data bus length” instruction. When the

internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the OSC₁terminal.

In addition, the feed back resister for the oscillation is varied by programming the “Rf” register of the “Frequency

control” instruction, so that it is possible to optimize the frame frequency for a LCD panel. Setting examples of the

MON (B&W /Gradation) and the PWM (Variable gradation /Fixed gradation) are described, as follows.

(19-1) Internal oscillation mode (CKS=0)

Symbol

FR1

MON

PWM

Display mode

Variable gradation mode

Fixed gradation mode

B&W mode

0

1

0

1

*

FR2

FR3

*: Don’t care

(19-2) External resistor oscillation mode (CKS=1)

The internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and

the “MON” and “PWM” registers must be set as well.

(19-3) External clock input mode (CKS=1)

The external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and

the “MON” and “PWM” registers must be set as well.

(20) Power supply circuits

The internal power supply circuits are composed of the voltage booster, the electrical variable resister (EVR), the

voltage regulator, reference voltage generator and the voltage followers.

The condition of the power supply circuits is arranged by programming the “DCON” and “AMPON” registers on the

“Power control” instruction. For this arrangement, some parts of the internal power supply circuits are activated in

using an external power supply, as shown in the following table.

Table 15

Voltage followers

DCON

AMPON

Voltage booster

Voltage regulator

EVR

External voltage

Note

0

1

0

1

Disable

Enable

Disable

Enable

V_OUT, V_LCD, V₁, V₂, V₃, V₄

1, 3

2, 3

−

V_OUT

−

+

-

+

-

+

-

Note1) Th₊e interna₊l power circuits are not used. The external V_OUTis required and the C₁, C₁, C₂, C₂, C₃, C₃,

-

C₄, C₄, C₅, C₅, V_REF, V_REGand V_EEterminals must be open.

+

Note2) The int₊ernal power circuits excep₊t the_-voltage booster are used. The external V_OUTis required and the C₁,

-

+

-

+

-

C₁, C₂, C₂, C₃, C₃, C₄, C₄, C₅, C₅and V_EEterminals must be open. The reference voltage is required

to V_REFterminal.

Note3) The relation among the voltages should be maintained as follows.

V_OUT≥ V_LCD≥ V₁≥ V₂≥ V₃≥ V₄≥ V_SS

- 42 -

NJU6818

(21) Voltage booster

The voltage booster generates maximum 6x voltage of the V_EElevel. It is programmed so that the boost level is

selected out of 1x, 2x, 3x, 4x, 5x and 6x by the “Boost level select” instruction. The boosted voltage V_OUTmust not

exceed beyond the value of 18.0V, otherwise the voltage stress may cause a permanent damage to the LSI.

Boosted voltages

V_OUT=18V

V_OUT=9.9V

V_EE=3V

V_SS=0V

V_EE=3.3V

V_SS=0V

6-time boost

3-time boost

Capacitor connections for the voltage Booster

6-time boost

5-time boost

C₁+

C₁-

C₁+

+

C₁-

C₂+

C₂-

C₂+

C₂-

C₃+

C₃-

C₃+

C₃-

C₄+

C₄-

C₄+

C₄-

C₅+

C₅-

C₅+

C₅-

V_OUT

V_SS

V_OUT

V_SS

+

4-time boost

3-time boost

2-time boost

C₁+

C₁-

C₁+

C₁-

C₁+

C₁-

+

C₂+

C₂-

C₂+

C₂-

C₂+

C₂-

C₃+

C₃-

C₃+

C₃-

C₃+

C₃-

C₄+

C₄-

C₄+

C₄-

C₄+

C₄-

C₅+

C₅-

C₅+

C₅-

C₅+

C₅-

V_OUT

V_SS

V_OUT

V_SS

V_OUT

V_SS

+

Fig 9

- 43 -

NJU6818

(22) Reference voltage generator

The reference voltage generator is used to produce the reference voltage (V_BA), which is output from the V_BA

terminal and should be input to the V_REFterminal.

V_BA= V_EEx 0.9

(23) Voltage regulator

The voltage regulator, composed of a gain control circuit and an operational amplifier, and is used to gain the

reference voltage (V_REF) and to create the regulated voltage (V_REG). The V_REGis used as an input voltage to the

EVR circuits which is programmed by the “VU” register of the “Boost level” instruction.

V_REG= V_REFx N

(N: register value for the boost level)

(24) Electrical variable resister (EVR)

The EVR is variable within 128-step, and is used to fine-tune the LCD driving voltage (V_LCD) by programming the

“DV” register of the “EVR control” instruction, so that it is possible to optimize the contrast level of LCD panels.

V_LCD= 0.5 x V_REG+ M (V_REG- 0.5 x V_REG) / 127 (M: register value for the EVR)

(25) LCD driving voltage generation circuit

LCD driving voltage generation circuit generates the V_LCDvoltage levels as V_LCD, V₁, V₂, V₃and V₄with internal

E.V.R and the bleeder resistors. The bias ratio of the LCD driving voltage is selected out of 1/4, 1/5, 1/6, 1/7, 1/8,

1/9 and 1/10.

In using the internal power supply, the capacitors CA₂must be connected to the V_LCD, V₁, V₂, V₃and V₄terminals,

and the CA₂value must be determined by the evaluation with actual LCD modules.

In using the external power supply, the external LCD driving voltages such as the V_LCD, V₁, V₂, V₃and V₄are

supplied and the internal power supply circuits must be set to “OFF” by DCON = AMPON = "0". In this mode,

voltage booster terminals such as C₁+, C₁-, C₂+, C₂-, C₃+, C₃-, C₄+, C₄-, C₅+, C₅-, V_EE, V_REFand V_REGmust be

opened.

In case that the voltage booster is not used but only some parts of internal power supply circuits (Voltage followers,

Voltage regulator and EVR) are used, the C₁+, C₁-, C₂+, C₂-, C₃+, C₃-, C₄+, C₄-, C₅+ and C₅- terminals must be

opened. And, the external power supply is input to the V_OUTterminal, and the reference voltage to the V_REFterminal.

The capacitor CA₃must connect to the V_REGterminal for voltage stabilization.

- 44 -

NJU6818

ꢀ

Connections of the capacitors for voltage booster

Using all of the internal power supply circuits

(6-time boost)

Using only external power supply circuits

V_DD

V_EE

V_DD

V_EE

V_BA

V_REF

V_REG

CA₃

V_REG

CA₃

V_SS

C₁-

C₁+

C₂-

C₂+

C₃-

C₃+

C₄-

C₄+

C₅-

C₅+

CA₁

C₁+

C₂-

CA₁

C₂+

C₃-

CA₁

C₃+

C₄-

NJU6818

CA₁

C₄+

C₅-

CA₁

C₅+

V_OUT

CA₁

V_SS

V_LCD

CA₂

V_LCD

V₁

V_LCD

V₁

CA₂

External

V₂

V₃

V₄

V₂

Power

circuit

CA₂

V₃

CA₂

V₄

CA₂

V_SS

Fig 10

Fig11

Reference values

CA₁

CA₂

CA₃

1.0 to 4.7uF

1.0 to 2.2uF

0.1uF

Note) B grade capacitors are required.

- 45 -

NJU6818

Using internal power supply circuits

without the reference voltage generator (2)

(6-time boost)

without the reference voltage generator (1)

(6-time boost)

V_DD

V_EE

V_BA

V_REF

V_EE

V_BA

V_REF

V_REG

CA₃

V_SS

CA₃

V_SS

C₁-

CA₁

C₁+

CA₁

C₁+

C₂-

CA₁

C₂-

CA₁

C₂+

C₃-

CA₁

C₃-

CA₁

C₃+

C₄-

CA₁

NJU6818

C₄+

C₅-

C₄+

C₅-

C₅+

V_OUT

CA₁

V_SS

CA₁

V_SS

V_LCD

V₁

V_LCD

V₁

CA₂

V₂

V₃

V₄

V_SS

Fig 12

Fig 13

Reference value

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note) B grade capacitors are required.

- 46 -

NJU6818

Using internal power supply circuits

without the voltage booster

V_DD

V_EE

V_BA

CA₃

V_REF

V_REG

CA₃

V_SS

C₁-

C₁+

C₂-

C₂+

C₃-

C₃+

C₄-

C₄+

C₅-

C₅+

V_SS

NJU6818

External

power

circuit

V_OUT

V_LCD

V₁

CA₂

V₂

CA₂

V₃

V₄

V_SS

Fig 14

Reference value

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

Note) B grade capacitors are required.

- 47 -

NJU6818

(26) Partial display function

The partial display function is used to partially specify some parts of display area on LCD panels. By using this

function, LCD modules can work in lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD

driving voltage. It is usually used to display a time and calendar, and is also used to optimize the LSI condition in

accordance with the display size. It can be programmed to select the duty cycle ratio (1/13, 1/17, 1/27, 1/33,

1/39,1/47, 1/57,1/69,1/77,1/81 in “DSE” is “0”), the LCD bias ratio, the boost level and the EVR value by the

instructions.

Partial display image

NJRC

LCD DRIVER

Low Power and

Low Voltage

LCD DRIVER

Partial display

Normal display

Partial display sequence

Optional status

Display OFF (ON/OFF=”0”)

Internal Power supply OFF (DCON=”0”, AMPON=”0”)

WAIT

Setting for LCD driving voltage-related functions

Internal Power supply ON (DCON=”1”, AMPON=”1”)

- Boost level

- EVR value

- LCD bias ratio

WAIT

- Duty cycle ratio

- Initial display line

- Initial COM line

- Other instructions

Setting for display-related functions

Display ON (ON/OFF =”1”)

Partial display Status

- 48 -

NJU6818

(27) Discharge circuit

Discharge circuit is used to discharge the electric charge of the capacitors on the V₁to V₄and the VLCD terminals.

This circuit is activated by setting “0” to the “DIS” register of the “Discharge” instruction or by setting the “RESb”

terminal to ”0” level. The “Discharge ON/OFF” instruction is usually required just after the internal power supply is

turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the external power supply is turned

off. During the discharge operation, the internal or external power supply must not be turned on.

(28) Reset circuit

The reset circuit initializes the LSI into the following default status. It is activated by setting the RESb terminal to “0”.

The RESb terminal is usually required to connect to MPU reset terminal in order that the LSI can be initialized at

the same timing of the MPU.

ꢁ Default status

1. DDRAM display data

2. Column address

3. Row address

:Undefined

:(00)_H

4. Initial display line

5. Display ON/OFF

6. Reverse display ON/OFF

7. Duty cycle ratio

:(0)_H(1st line)

:OFF

:OFF (normal)

:1/81 duty(DSE=0)

:OFF

8. N-line Inversion ON/OFF

9. COM scan direction

10. Increment mode

:COM₀→ COM₇₉

:OFF

11. Reverse SEG direction

12. SWAP mode

:OFF (normal)

:(0, 0, 0, 0, 0, 0, 0)

:OFF

13. EVR value

14. Internal power supply

15. Display mode

:Gradation display mode

:1/9 bias

16. LCD bias ratio

17. Gradation Palette 0

18. Gradation Palette 1

19. Gradation Palette 2

20. Gradation Palette 3

21. Gradation Palette 4

22. Gradation Palette 5

23. Gradation Palette 6

24. Gradation Palette 7

25. Gradation Palette 8

26. Gradation Palette 9

27. Gradation Palette 10

28. Gradation Palette 11

29. Gradation Palette 12

30. Gradation Palette 13

31. Gradation Palette 14

32. Gradation Palette 15

33. Gradation mode control

34. Data bus length

:(0, 0, 0, 0, 0)

:(0, 0, 0, 1, 1)

:(0, 0, 1, 0, 1)

:(0, 0, 1, 1, 1)

:(0, 1, 0, 0, 1)

:(0, 1, 0, 1, 1)

:(0, 1, 1, 0, 1)

:(0, 1, 1, 1, 1)

:(1, 0, 0, 0, 1)

:(1, 0, 0, 1, 1)

:(1, 0, 1, 0, 1)

:(1, 0, 1, 1, 1)

:(1, 1, 0, 0, 1)

:(1, 1, 0, 1, 1)

:(1, 1, 1, 0, 1)

:(1, 1, 1, 1, 1)

:Variable gradation mode

:8-bit data bus length

:(DIS/DIS2) : ”0”

35. Discharge circuit

- 49 -

NJU6818

(29) Power supply ON/OFF sequences

The following paragraphs describe power supply ON/OFF sequences, which are to protect the LSI from over

current.

(29-1) Using an external power supply

Power supply ON sequence

Logic voltage (V_DD) must be always input first, and next the LCD driving voltages (V₁to V₄and V_LCD) are turned on.

In using the external V_OUT, the V_DDmust be input first, next the reset operation must be performed, and finally the

V_OUTcan be input

Power supply OFF sequence

Either the reset operation, cutting off the V₁to V₄and V_LCDfrom the LSI, by the RESb terminal or the “Power

control” instruction must be performed first, and next the V_DDis turned off. It is recommended that a series-resister

between 50Ω and 100Ω is added on the V_LCDline (or V_OUTline in using only the external V_OUTvoltage) in order to

protect the LSI from the over current.

(29-2) Using the internal power supply circuits

Power supply ON sequence

The V_DDmust be input first, next the reset operation must be performed, and finally the V₁to V₄and the V_LCDcan

be turned on by setting “1” to the “DCON” and “AMPON” registers of the “Power control” instruction.

Power supply OFF sequence

Either the reset operation by the RESb terminal or the “Power control” instruction must be performed first, and next

the input voltage for the voltage booster (V_EE) and the V_DDcan be turned off. If the V_EEis supplied from different

power sources for the V_DD, the V_EEis turned off first and next the V_DDis turned off

- 50 -

NJU6818

(30) Referential instruction sequences

(30-1) Initialization in using the internal power supply circuits

V_DD, V_EEpower ON

Wait for power-ON stabilization

RESET Input

WAIT

Setting for LCD driving voltage-related functions

End of initialization

- EVR value

- LCD bias ratio

- Power control (DCON=”1”, AMPON=”1”)

(30-2) Display data writing

End of Initialization

Setting for display-related functions

- Initial display line

- Increment mode

- Column address

- Row address

Display data write

Display ON (ON/OFF =”1”)

- 51 -

NJU6818

(30-3) Power OFF

Optional status

- All COM/SEG output V_SSlevel.

Power save or reset operation

Discharge ON

WAIT

V_EE, V_DDpower OFF

- 52 -

NJU6818

(31) Instruction table

Instruction Table (1)

Code (80 series MPU I/F)

Code

Instructions

Functions

CSb RS RDb WRb

RE₂RE₁RE₀D₇D₆D₅D₄D₃

D₂

D₁

D₀

Display data write

0

1

0

1

0

1

0

0/1 0/1 0/1

Write Data

Read Data

Write display data to DDRAM

Display data read

Column address

Read display data from DDRAM

DDRAM column address

DDRAM row address

AX3

AX7

AY3

*

AX2

AX6

AY2

AY6

LA2

LA6

N2

AX1

AX5

AY1

AY5

LA1

LA5

N1

AX0

AX4

AY0

AY4

LA0

LA4

N0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(Lower) [0_H]

Column address

(Upper) [1_H]

Row address

(Lower) [2_H]

Row address

(Upper) [3_H]

DDRAM row address

Initial display line

(Lower) [4_H]

Row address for an initial COM line

(Scan start line)

LA3

*

Initial display line

(Upper) [5_H]

Row address for an initial COM line

(Scan start line)

N-line inversion

(Lower) [6_H]

N3

*

The number of N-line inversion

N-line inversion

(Upper) [7_H]

N6

N5

N4

The number of N-line inversion

SHIFT: Common direction

Display control (1)

ALL

ON

ON/ MON: Gradation or B/W display mode

SHIFT MON

0

1

0

1

0

1

OFF

ALLON: All pixels ON/OFF

ON/OFF: Display ON/OFF

[8_H]

[9_H]

REV: Reverse display ON/OFF

NLIN: N-line inversion ON/OFF,

SWAP: SWAP mode ON/OFF

REF: Segment direction

Display control (2)

REV NLIN SWAP REF

WIN: Window addressing mode ON/OFF

AIM: Read-modify-write ON/OFF

AYI: Row auto-increment mode ON/OFF

AXI: Column auto-increment mode

ON/OFF

AMPON: Voltage followers ON/OFF

HALT: Power save ON/OFF

DCON: Voltage booster ON/OFF

ACL: Reset

Increment control

WIN

AIM

AYI

AXI

0

1

0

1

0

1

0

1

[A_H]

Power control

AMP

ON

DC

ON

HALT

ACL

[B_H]

[C_H]

Duty cycle ratio

DS3 DS2 DS1 DS0

0

1

0

1

0

1

0

1

0

1

Set LCD duty cycle ratio

Set boost level

Boost level / ID read

[D_H]

IDR

VU2 VU1 VU0

Sets ID reading in the serial

interface

LCD bias ratio

B2

B1

B0

*

Sets LCD bias ratio

[E_H]

[F_H]

RE register

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

RE flag set

Note 1)

*

: Don’t care.

Note 2) [ N_H] : Address of instruction register

Note 3)

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 53 -

NJU6818

Instruction Table (2)

Instructions

Code (80 series MPU I/F)

Code

Functions

CSb RS RDb WRb

RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Gradation palette A0/A8

(Lower) [0_H]

Sets palette values to gradation

palette A0(PS=0)/A8(PS=1)

PA03/ PA02/ PA01/ PA00/

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PA83 PA82 PA81 PA80

Gradation palette A0/A8

(Upper) [1_H]

Sets palette values to gradation

palette A0(PS=0)/A8(PS=1)

PA04/

*

PA84

Gradation palette A1/A9

(Lower) [2_H]

Sets palette values to gradation

palette A1(PS=0)/A9(PS=1)

PA13/ PA12/ PA11/ PA10/

PA93 PA92 PA91 PA90

Gradation palette A1/A9

(Upper) [3_H]

Sets palette values to gradation

palette A1(PS=0)/A9(PS=1)

PA14/

*

PA94

Gradation palette A2/A10

(Lower) [4_H]

Sets palette values to gradation

palette A2(PS=0)/A10(PS=1)

PA23/ PA22/ PA21/ PA20/

PA103 PA102 PA101 PA100

Gradation palette A2/A10

(Upper) [5_H]

Sets palette values to gradation

palette A2(PS=0)/A10(PS=1)

PA24/

*

PA104

Gradation palette A3/A11

(Lower) [6_H]

Sets palette values to gradation

palette A3(PS=0)/A11(PS=1)

PA33/ PA32/ PA31/ PA30/

PA113 PA112 PA111 PA110

Gradation palette A3/A11

(Upper) [7_H]

Sets palette values to gradation

palette A3(PS=0)/A11(PS=1)

PA34/

*

PA114

Gradation palette A4/A12

(Lower) [8_H]

Sets palette values to gradation

palette A4(PS=0)/A12(PS=1)

PA43/ PA42/ PA41/ PA40/

PA123 PA122 PA121 PA120

Gradation palette A4/A12

(Upper) [9_H]

Sets palette values to gradation

palette A4(PS=0)/A12(PS=1)

PA44/

*

PA124

Gradation palette A5/A13

(Lower) [A_H]

Sets palette values to gradation

palette A5(PS=0)/A13(PS=1)

PA53/ PA52/ PA51/ PA50/

PA133 PA132 PA131 PA130

Gradation palette A5/A13

(Upper) [B_H]

Sets palette values to gradation

palette A5(PS=0)/A13(PS=1)

PA54/

*

PA134

Gradation palette A6/A14

(Lower) [C_H]

Sets palette values to gradation

palette A6(PS=0)/A14(PS=1)

PA63/ PA62/ PA61/ PA60/

PA143 PA142 PA141 PA140

Gradation palette A6/A14

(Upper) [D_H]

Sets palette values to gradation

palette A6(PS=0)/A14(PS=1)

PA64/

*

PA144

RE register

[F_H]

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

RE flag set

Note 1)

*

: Don’t care.

Note 2) [ N_H] : Address of instruction register

Note 3)

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 54 -

NJU6818

Instruction Table (3)

Code (80 series MPU I/F)

Code

Instructions

Functions

CSb RS RDb WRb

RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Gradation palette A7/A15

(Lower) [0_H]

Sets palette values to gradation

palette A7(PS=0)/A15(PS=1)

PA73/ PA72/ PA71/ PA70/

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PA153 PA152 PA151 PA150

Gradation palette A7/A15

(Upper) [1_H]

Sets palette values to gradation

palette A7(PS=0)/A15(PS=1)

PA74/

*

PA154

Gradation palette B0/B8

(Lower) [2_H]

Sets palette values to gradation

palette B0(PS=0)/B8(PS=1)

PB03/ PB02/ PB01/ PB00/

PB83 PB82 PB81 PB80

Gradation palette B0/B8

(Upper) [3_H]

Sets palette values to gradation

palette B0(PS=0)/B8(PS=1)

PB04/

*

PG84

Gradation palette B1/B9

(Lower) [4_H]

Sets palette values to gradation

palette B1(PS=0)/B9(PS=1)

PB13/ PB12/ PB11/ PB10/

PB93 PB92 PB91 PB90

Gradation palette B1/B9

(Upper) [5_H]

Sets palette values to gradation

palette B1(PS=0)/B9(PS=1)

PB14/

*

PB94

Gradation palette B2/B10

(Lower) [6_H]

Sets palette values to gradation

palette B2(PS=0)/B10(PS=1)

PB23/ PB22/ PB21/ PB20/

PB103 PB102 PB101 PB100

Gradation palette B2/B10

(Upper) [7_H]

Sets palette values to gradation

palette B2(PS=0)/B10(PS=1)

PB24/

*

PB104

Gradation palette B3/B11

(Lower) [8_H]

Sets palette values to gradation

palette B3(PS=0)/B11(PS=1)

PB33/ PB32/ PB31/ PB30/

PB113 PB112 PB111 PB110

Gradation palette B3/B11

(Upper) [9_H]

Sets palette values to gradation

palette B3(PS=0)/B11(PS=1)

PB34/

*

PB114

Gradation palette B4/B12

(Lower) [A_H]

Sets palette values to gradation

palette B4(PS=0)/B12(PS=1)

PB43/ PB42/ PB41/ PB40/

PB123 PB122 PB121 PB120

Gradation palette B4/B12

(Upper) [B_H]

Sets palette values to gradation

palette B4(PS=0)/B12(PS=1)

PB44/

*

PB124

Gradation palette B5/B13

(Lower) [C_H]

Sets palette values to gradation

palette B5(PS=0)/B13(PS=1)

PB53/ PB52/ PB51/ PB50/

PB133 PB132 PB131 PB130

Gradation palette B5/B13

(Upper) [D_H]

Sets palette values to gradation

palette B5(PS=0)/B13(PS=1)

PB54/

*

PB134

RE register

[F_H]

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

RE flag set

Note 1)

*

: Don’t care.

Note 2) [ N_H] : Address of instruction register

Note 3)

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 55 -

NJU6818

Instruction Table (4)

Instructions

Code (80 series MPU I/F)

Code

Functions

CSb RS RDb WRb

RE₂RE₁RE₀D₇

D₆

0

D₅

0

D₄

D₃D₂

D₁D₀

Gradation palette B6/B14

(Lower) [0_H]

Sets palette values to gradation

palette B6(PS=0)/B14(PS=1)

PB63/ PB62/ PB61/ PB60/

PB143 PB142 PB141 PB140

0

1

0

1

0

1

0

Gradation palette B6/B14

(Upper) [1_H]

Sets palette values to gradation

palette B6(PS=0)/B14(PS=1)

PB64/

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

*

PB144

Gradation palette B7/B15

(Lower) [2_H]

Sets palette values to gradation

palette B7(PS=0)/B15(PS=1)

PB73/ PB72/ PB71/ PB70/

PB153 PB152 PB151 PB150

Gradation palette B7/B15

(Upper) [3_H]

Sets palette values to gradation

palette B7(PS=0)/B15(PS=1)

PB74/

*

PB154

Gradation palette C0/C8

(Lower) [4_H]

Sets palette values to gradation

palette C0(PS=0)/C8(PS=1)

PC03/ PC02/ PC01/ PC00/

PC83 PC82 PC81 PC80

Gradation palette C0/C8

(Upper) [5_H]

Sets palette values to gradation

palette C0(PS=0)/C8(PS=1)

PC04/

*

PC84

Gradation palette C1/C9

(Lower) [6_H]

Sets palette values to gradation

palette C1(PS=0)/C9(PS=1)

PC13/ PC12/ PC11/ PC10/

PC93 PC92 PC91 PC90

Gradation palette C1/C9

(Upper) [7_H]

Sets palette values to gradation

palette C1(PS=0)/C9(PS=1)

PC14/

*

PC94

Gradation palette C2/C10

(Lower) [8_H]

Sets palette values to gradation

palette C2(PS=0)/C10(PS=1)

PC23/ PC22/ PC21/ PC20/

PC103 PC102 PC101 PC100

Gradation palette C2/C10

(Upper) [9_H]

Sets palette values to gradation

palette C2(PS=0)/C10(PS=1)

PC24/

*

PC104

Gradation palette C3/C11

(Lower) [A_H]

Sets palette values to gradation

palette C3(PS=0)/C11(PS=1)

PC33P PC32/ PC31/ PC30/

C113 PC112 PC111 PC110

Gradation palette C3/C11

(Upper) [B_H]

Sets palette values to gradation

palette C3(PS=0)/C11(PS=1)

PC34/

*

PC114

Gradation palette C4/C12

(Lower) [C_H]

Sets palette values to gradation

palette C4(PS=0)/C12(PS=1)

PC43/ PC42/ PC41/ PC40/

PC123 PC122 PC121 PC120

Gradation palette C4/C12

(Upper) [D_H]

Sets palette values to gradation

palette C4(PS=0)/C12(PS=1)

PC44/

*

PC124

RE register

[F_H]

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

RE flag set

Note 1)

*

: Don’t care.

Note 2) [ N_H] : Address of instruction register

Note 3)

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 56 -

NJU6818

Instruction Table (5)

Code (80 series MPU I/F)

Code

Instructions

Functions

CSb RS RDb WRb

RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Gradation palette C5/C13

(Lower) [0_H]

Sets palette values to gradation

palette C5(PS=0)/C13(PS=1)

PC53/ PC52/ PC51/ PC50/

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

PC133 PC132 PC131 PC130

Gradation palette C5/C13

(Upper) [1_H]

Sets palette values to gradation

palette C5(PS=0)/C13(PS=1)

PC54/

*

PC134

Gradation palette C6/C14

(Lower) [2_H]

Sets palette values to gradation

palette C6(PS=0)/C14(PS=1)

PC63/P PC62/ PC61/ PC60/

C143 PC142 PC141 PC140

Gradation palette C6/C14

(Upper) [3_H]

Sets palette values to gradation

palette C6(PS=0)/C14(PS=1)

PC64/

*

PC144

Gradation palette C7/C15

(Lower) [4_H]

Sets palette values to gradation

palette C7(PS=0)/C15(PS=1)

PC73/ PC72/ PC71/ PC70/

PC153 PC152 PC151 PC150

Gradation palette C7/C15

(Upper) [5_H]

Sets palette values to gradation

palette C7(PS=0)/C15(PS=1)

PC74/

*

PC154

Initial COM line

[6_H]

SC3 SC2 SC1 SC0

Scan-starting common driver

Display clock / Duty-1

[7_H]

SON : Display clock ON/OFF

DSE : Duty-1 ON/OFF

SON

0

1

0

1

0

1

0

1

0

1

0

*

DSE

*

Gradation mode control

[8_H]

PWM : Variable/Fixed gradation mode

C256 : 256-color mode ON/OFF

PWM C256

*

HSW : High speed access ON/OFF

ABS : ABS mode ON/OFF

Data bus length

[9_H]

HSW ABS CKS WLS

DV3 DV2 DV1 DV0

0

1

0

1

0

1

0

1

CKS : Internal/external oscillation

WLS : Display data Length

EVR control

Sets EVR level

(Lower bit)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(Lower) [A_H]

EVR control

Sets EVR level

(Upper bit)

DV6 DV5 DV4

RF2 RF1 RF0

*

(Upper) [B_H]

Frequency control

[D_H]

Oscillation frequency

Discharge ON/OFF

[E_H]

Discharge the electric charge in

Capacitors on V₁to V₄, V_LCD

DIS

DIS2

*

RE register

[F_H]

TST₀RE₂RE₁RE₀

Register address

Read Data

0/1 0/1 0/1

RE flag

Instruction register address

[C_H]

1

0

Sets instruction register address

Read out instruction register data

Instruction register read /

ID read

0/1 0/1 0/1 ID3 ID2 ID1 ID0

Note 1)

*

: Don’t care.

Note 2) [ N_H] : Address of instruction register

Note 3)

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

Note 4)

CKS=0: Internal oscillation mode (default)

CKS=1: External oscillation mode

- 57 -

NJU6818

Instruction Table (6)

Instructions

Code (80 series MPU I/F)

Code

Functions

CSb RS RDb WRb

RE₂RE₁RE₀D₇D₆D₅D₄D₃D₂D₁D₀

Window end

column address

(Lower) [0_H]

Window end

column address

(Upper) [1_H]

EX3 EX2 EX1 EX0

EX7 EX6 EX5 EX4

EY3 EY2 EY1 EY0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Sets column address for end point

Sets row address for end point

Sets address for reverse line

Window end row address

(Lower) [2_H]

Window end row address

(Upper) [3_H]

*

EY6 EY5 EY4

Initial reverse line

(Lower) [4_H]

LS3 LS2 LS1 LS0

Initial reverse line

(Upper) [5_H]

*

LS6 LS5 LS4

Last reverse line

(Lower) [6_H]

LE3 LE2 LE1 LE0

Last reverse line

(Upper) [7_H]

*

LE6 LE5 LE4

Reverse line display

ON/OFF

BT : Blink type setting

BT LREV

*

LREV : Reverse line display ON/OFF

[8_H]

Gradation palette setting

PS

*

PS : Gradation setting

Sets PWM mode

RE flag

0

[9_H]

[A_H]

[F_H]

PWM control

RE register

PWM PWM PWM PWM

0

S

A

B

C

TST₀RE₂RE₁RE₀

0/1 0/1 0/1

Note 1)

*

: Don’t care.

Note 2) [ N_H] : Address of instruction register

Note 3)

The dual instructions including upper and lower bytes is enabled after either upper or lower

bytes are set into the register. The only “EVR control” instruction is enabled after both of the

upper and lower bytes are set.

- 58 -

NJU6818

(32) Instruction descriptions

This chapter provides detail descriptions and instructions and instruction registers. Nonexistent instruction codes

must not be set into the LSI.

(32-1) Display data write

The “Display data write” instruction is used to write 8-bit display data into the DDRAM.

WRb

0

CSb

0

RS

0

RDb

1

RE2 RE1 RE0

0/1 0/1 0/1

D7

D6

D5

D4

D3

D2

D1

D0

Display data

(32-2) Display data read

The “Display data read” instruction is used to read out 8-bit display data from the DDRAM, where the column

address and row address must be specified beforehand by the “column address” and “row address” instructions.

The dummy read is required just after the “column address” and “row address” instructions.

WRb

1

CSb

0

RS

0

RDb

0

RE2 RE1 RE0

0/1 0/1 0/1

D7

D6

D5

D4

D3

D2

D1

D0

Display data

(32-3) Column address

The “column address” instruction is used to specify the column address for display data’s reading and writing

operations. It requires dual bytes for lower 4-bit and upper 4-bit data. The instruction for the lower 4-bit data must

be executed first, next the instruction for the upper 4-bit.

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

0

D3

AX3

D2

AX2

D1

D0

0

AX1 AX0

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

1

D3

AX7

D2

AX6

D1

D0

0

AX5 AX4

(32-4) Row address

The “row address” instruction is used to specify the row address for display data read and write operations. It

requires dual bytes for lower 4-bit and upper 3-bit data. The instruction for the lower 4-bit data must be executed

first, next the instruction for the upper 3-bit. The row address is specified in between 00_Hand 4F_H. The setting for

nonexistent row address between 50_Hand FF_His prohibited.

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

0

D3

AY3

D2

AY2

D1

D0

0

AY1 AY0

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

AY6

D1

D0

0

AY5 AY4

- 59 -

NJU6818

(32-5) Initial display line

The “Initial display line” instruction is used to specify the line address corresponding to the initial COM line. The

initial COM line is specified by the “Initial COM line” instruction and indicates the common driver that starts

scanning display data.

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

0

D3

LA3

D2

LA2

D1

LA1

D0

LA0

0

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

LA6

D1

LA5

D0

LA4

0

LA6

0

LA5

0

LA4

0

LA3

0

LA2

0

LA1

0

LA0

0

1

Line address

0

1

:

1

0

1

79

(32-6) N-line inversion

The “N-line inversion” instruction is used to control the alternate rates of liquid crystal direction. It is programmed to

select the N value between 2 and 80, and the FR signal toggles once every N lines by setting “1” into the “NLIN”

register of the “Display control (2)” instruction. When the N-line inversion is disabled by setting “0” into the “NLIN”

register, the FR signal toggles by the frame.

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

0

D3

N3

D2

N2

D1

N1

D0

N0

0

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

1

D3

*

D2

N6

D1

N5

D0

N4

0

N6

0

N5

0

N4

0

N3

0

N2

0

N1

0

N0

0

1

N value

Inhibited

2

:

1

0

1

80

- 60 -

NJU6818

N-line Inversion Timing (1/81 duty cycle ratio)

N-line inversion OFF

1st line

3rd line

80th line

1st line

2nd line

81th line

CL

FLM

FR

N-line inversion ON

N-line control

1st line

3rd line

N line

2nd line

1st line

CL

FR

(32-7) Display control (1)

The “Display control (1)” instruction is used to control display conditions by setting the “Display ON/OFF”, “All

pixels ON/OFF”, “Display mode” and “Common direction” registers.

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

0

D3

D2

D1

ALL

ON

D0

ON/

OFF

SHIFT

MON

0

ON/OFF register

ON/OFF=0

ON/OFF=1

: Display OFF (All COM/SEG output the Vss level.)

: Display ON

All ON register

The “All pixels ON/OFF” register is used to turn on all pixels without changing display data of the DDRAM. The

setting for the “All pixels ON/OFF” register has a priority over the “Reverse display ON/OFF” register.

ALLON=0

ALLON=1

: Normal

: All pixels turn on.

MON register

MON=0

MON=1

: Gradation mode

: B&W mode

SHIFT register

SHIFT=0

SHIFT=1

: COM₀→ COM₇₉

: COM₇₉→ COM₀

- 61 -

NJU6818

(32-8) Display control (2)

The “Display control (2)” instruction is used to control display conditions by setting the “Segment direction”, “SWAP

mode ON/OFF”, “N-line inversion ON/OFF” and “Reverse display ON/OFF” registers.

WRb

0

CSb

0

RS

1

RDb

1

RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

1

D3

D2

D1

D0

REV

NLIN

SWAP

REF

0

REF register

The “REF” register is used to reverse the assignment between segment drivers and column address, and it is

possible to reduce restrictions for placement of the LSI on the LCD module. For more information, see (10) “The

relation among the DDRAM column address, display data and segment drivers”.

SWAP register

The “SWAP” register is used to reverse the arrangement of display data in the DDRAM.

SWAP=0 : SWAP mode OFF

SWAP=1 : SWAP mode ON

(Normal)

SWAP=”0”

D₇D₆D₅D₄D₃D₂D₁D₀

SWAP=”1”

Write data

D₇D₆D₅D₄D₃D₂D₁D₀

RAM data

D7 d6 d5 d4 d3 d2 d1 d0

d0 d1 d2 d3 d4 d5 d6 d7

D₇D₆D₅D₄D₃D₂D₁D₀

Read data

D₇D₆D₅D₄D₃D₂D₁D₀

NLIN register

The “NLIN” is used to enable or disable the N-line inversion.

NLIN=0 : N-line inversion OFF

NLIN=1 : N-line inversion ON

(The FR signal toggles by the flame.)

(The FR signal toggles once every N lines.)

REV register

The “REV” register is used to enable or disable the reverse display mode that reverses the polarity of display data

without changing display data of the DDRAM.

REV=0 : Reverse display mode OFF

REV=1 : Reverse display mode ON

REV

0

Display

Normal

DDRAM data → Display data

0

1

0

1

0

1

0

1

Reverse

- 62 -

NJU6818

(32-9) Increment control

The “Increment control” instruction is used for the increment mode. In using the auto-increment mode, DDRAM

address automatically increments (+1) whenever the DDRAM is accessed by the “Display data write” or “Display

data read” instruction. Therefore, once “Display data write” or “Display data read” instruction is established, it is

possible to continuously access to the DDRAM without the “column address” and “row address” instructions. The

settings for the “AIM”, “AXI” and “AYI” registers are listed in the following tables.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

0

D3

D2

D1

AYI

D0

AXI

1

0

WIN AIM

AIM, AYI and AXI registers

AIM

0

1

Increment mode

Note

1

2

Auto-increment for the both of display data read and write operations

Auto-increment for the display write operation (Read-modify-write)

Note 1) It is effective for usual operations accessing successive addresses.

Note 2) It is effective for the read-modify-write operation.

AYI

0

AXI

0

Increment mode

Note

No auto-increment

1

2

3

4

0

1

Auto-increment for the column address

1

0

1

Auto-increment for the row address

Auto-increment for the column address and row address

Note 1) Auto-increment is disabled regardless of the “AIM” register.

Note 2) Auto-increment of the column address is enabled in accordance with the “AIM” register.

MAX_H

00_H

MAX_Hin the 8-bit data bus mode

: CF_H

MAX_Hin the 16-bit data bus mode : 67_H

Note 3) Auto-increment of the row address is enabled in accordance with the “AIM” register.

4F_H

00_H

Note 4) Auto-increments of the column address and the row address are enabled. The row address increments

whenever the column address reaches to the MAX_H.

Max_H

Column address

MAX_Hin the 8-bit data bus mode

00_H

4F_H

Row address

00_H

: CF_H

MAX_Hin the 16-bit data bus mode

: 67_H

- 63 -

NJU6818

WIN register

The “WIN” register is used to access to the DDRAM for the window display area, where the start point is

determined by the “column address” and “row address” instructions, and the end point by the “Window end column

address “and ”Window end row address” instructions. The setting sequence for the window display area is listed

as follows. For more detail, see (6) “Window addressing mode”.

WIN=0 : Window addressing mode OFF

WIN=1 : Window addressing mode ON

1. Set WIN=1, AXI=1, and AYI=1 by the “Increment control” instruction

2. Set the start point by the “column address” and “row address” instructions

3. Set the end point by the “Window end column address” and “Window end row address” instructions

4. Enable to access to the DDRAM in the window addressing mode

START

END

START

Address

Column address

Row address

- 64 -

NJU6818

(32-10) Power control

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

1

D3

D2

D1

D0

ACL

AMPON HALT DCON

1

0

ACL register

The “ACL” register is used to initialize the internal power supply circuits.

ACL=0 : Initialization OFF (Normal)

ACL=1 : Initialization ON

When the data of the “ACL register” is read out by the “Instruction register read” instruction, the read-out data is “1”

during the initialization, and “0” after the initialization. This initialization is performed by using the signal produced

by 2 clocks on the OSC₁. For this reason, the wait time for 2 clocks of the OSC₁is necessary until next instruction.

DCON register

The “DCON” register is used to enable or disable the voltage booster.

DCON=0

DCON=1

: Voltage booster OFF

: Voltage booster ON

HALT register

The “HALT” register is used to enable or disable the power save mode. It is possible to reduce operating current

down to stand-by level. The internal status in the power save mode is listed below.

HALT=0 : Power save OFF (Normal)

HALT=1 : Power save ON

Internal status in the power save mode

• The oscillation circuits and internal power supply circuits are halted.

• All segment and common drivers output the V_SSlevel.

• The clock input into the OSC₁is inhibited.

• The display data in the DDRAM is maintained.

• The operational modes before the power save mode are maintained.

• The V₁to V₄and the V_LCDare in high impedance.

As a power save ON sequence, the “Display OFF” must be executed first, next the “Power save ON” instruction,

and then all common and segment drivers output the V_SSlevel. And as power save OFF sequence, the “Power

save OFF” instruction is executed first, next the “Display ON” instruction. If the “Power save OFF” instruction is

executed in the display ON status, unexpected pixels may instantly turn on.

AMPON register

The “AMPON” register is used to enable or disable the voltage followers, voltage regulator and EVR.

AMPON=0 : The voltage followers, the voltage regulator and the EVR OFF

AMPON=1 : The voltage followers, the voltage regulator and the EVR ON

- 65 -

NJU6818

(32-11) Duty cycle ratio

The “Duty cycle ratio” instruction is used to select LCD duty cycle ratio for the partial display function. The partial

display function specifies some parts of display area on a LCD panel in the condition of lower duty cycle ratio,

lower LCD bias ratio, lower boost level and lower LCD driving voltage. Therefore, it is possible to optimize the LSI’s

conditions with extremely low power consumption.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

0

D3

D2

D1

D0

1

0

DS3 DS2 DS1 DS0

Duty cycle ratio

Row way

displays

DS3

DS2

DS1

DS0

DSE=0

DES=1

1/80

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1/81

1/77

1/69

1/57

1/47

1/39

1/33

1/27

1/17

1/13

80 commons

76 commons

68 commons

56 commons

46 commons

38 commons

32 commons

26 commons

16 commons

12 commons

1/76

1/68

1/56

1/46

1/38

1/32

1/26

1/16

1/12

Inhibited

The duty cycle ratio is controlled by the “DS3 to DS0” registers of the “Duty cycle ratio” instruction and the “DSE”

register of the “Display clock / Duty-1” instruction.

DSE=0 : The number of commons +1

(Duty cycle ratio in the default setting)

DSE=1 : The number of commons (Duty-1)

When the “DSE” is “0”, all common drivers output non-selective levels in period of lost common. And the segment

drivers output the same data for the last line as the data for previous line: For instance they output the same data

for the 80^thand 81^stlines when the duty cycle ratio is set to 1/81. For the setting of the “DSE” register, see (32-17)

“Display clock / Duty-1”.

(32-12) Boost level

The “Boost level” is used to select multiple of the voltage booster for the partial display function.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

1

D3

IDR

D2

D1

D0

1

0

VU2 VU1 VU0

a) ID read in serial interface

ID data can be read out by setting IDR=1.

b) Boost level set

VU2

0

VU1

0

VU0

0

Boost level

1-time (No boost)

2-time

0

1

0

1

0

3-time

0

1

4-time

1

0

5-time

1

0

1

6-time

1

0

Inhibited

1

- 66 -

NJU6818

(32-13) LCD bias ratio

The “LCD bias ratio” is used to select the LCD bias ratio for the partial display function.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

1

D4

0

D3

*

D2

B2

D1

B1

D0

B0

1

0

B2

0

B1

0

B0

0

LCD bias ratio

1/9

1/8

0

1

0

1

0

1/7

0

1

1/6

1

0

1/5

1

0

1

1/4

1

0

1/10

Inhibited

1

(32-14) RE flag

The “RE flag” registers are used to determine the contents for the RE registers (RE₂, RE₁and RE₀), and it is

possible to access to the instruction registers.

The data of the “TST₀” register must be “0”, and it is used for maker tests only.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

0/1 0/1 0/1

D7

1

D6

1

D5

1

D4

1

D3

D2

D1

D0

1

0

TST0 RE2 RE1 RE0

- 67 -

NJU6818

(32-15) Gradation palette A, B and C

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

PA03/ PA02/ PA01/ PA00/

PA83 PA82 PA81 PA80

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PA04/

PA84

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

0

D3

D2

D1

D0

PA13/ PA12/ PA11/ PA10/

PA93 PA92 PA91 PA90

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PA14/

PA94

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

0

D3

D2

D1

D0

PA23/ PA22/ PA21/ PA20/

PA103 PA102 PA101 PA100

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PA24/

PA104

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

0

D3

D2

D1

D0

PA33/ PA32/ PA31/ PA30/

PA113 PA112 PA111 PA110

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PA34/

PA114

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

0

D3

D2

D1

D0

PA43/ PA42/ PA41/ PA40/

PA123 PA122 PA121 PA120

1

0

1

- 68 -

NJU6818

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PA44/

PA124

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

0

D3

D2

D1

D0

PA53/ PA52/ PA51/ PA50/

PA133 PA132 PA131 PA130

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PA54/

PA134

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

0

D3

D2

D1

D0

PA63/ PA62/ PA61/ PA60/

PA143 PA142 PA141 PA140

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PA64/

PA144

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

PA73/ PA72/ PA71/ PA70/

PA153 PA152 PA151 PA150

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PA74/

PA154

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

0

D3

D2

D1

D0

PB03/ PB02/ PB01/ PB00/

PB83 PB82 PB81 PB80

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PB04/

PB84

1

0

1

0

- 69 -

NJU6818

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

0

D3

D2

D1

D0

PB13/ PB12/ PB11/ PB10/

PB93 PB92 PB91 PB90

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PB14/

PB94

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

0

D3

D2

D1

D0

PB23/ PB22/ PB21/ PB20/

PB103 PB102 PB101 PB100

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PB24/

PB104

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

0

D3

D2

D1

D0

PB33/ PB32/ PB31/ PB30/

PB113 PB112 PB111 PB110

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PB34/

PB114

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

0

D3

D2

D1

D0

PB43/ PB42/ PB41/ PB40/

PB123 PB122 PB121 PB120

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PB44/

PB124

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

0

D3

D2

D1

D0

PB53/ PB52/ PB51/ PB50/

PB133 PB132 PB131 PB130

1

0

1

0

- 70 -

NJU6818

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PB54/

PB134

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

PB63/ PB62/ PB61/ PB60/

PB143 PB142 PB141 PB140

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PB64/

1

0

1

PB144

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

0

D3

D2

D1

D0

PB73/ PB72/ PB71/ PB70/

1

0

1

PB153 PB152 PB151 PB150

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PB74/

PB154

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

0

D3

D2

D1

D0

PC03/ PC02/ PC01/ PC00/

PC83 PC82 PC81 PC80

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PC04/

PC84

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

0

D3

D2

D1

D0

PC13/ PC12/ PC11/ PC10/

PC93 PC92 PC91 PC90

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PC14/

PC94

1

0

1

- 71 -

NJU6818

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

0

D3

D2

D1

D0

PC23/ PC22/ PC21/ PC20/

PC103 PC102 PC101 PC100

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PC24/

PC104

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

0

D3

D2

D1

D0

PC33/ PC32/ PC31/ PC30/

PC113 PC112 PC111 PC110

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PC34/

PC114

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

0

D3

D2

D1

D0

PC43/ PC42/ PC41/ PC40/

PC123 PC122 PC121 PC120

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PC44/

PC124

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

PC53/ PC52/ PC51/ PC50/

PC133 PC132 PC131 PC130

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PC54/

PC134

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

0

D3

D2

D1

D0

PC63/ PC62/ PC61/ PC60/

PC143 PC142 PB141 PB140

1

0

1

0

- 72 -

NJU6818

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

*

D1

*

D0

PC64/

PC144

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

0

D3

D2

D1

D0

PC73/ PC72/ PC71/ PC70/

PC153 PC152 PC151 PC150

1

0

1

0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PC74/

PC154

1

0

1

0

Gradation palette table (Variable gradation mode, PWM=”0” and MON=”0”)

(Palette Aj, Palette Bj, Palette Cj (j=0 to 15))

Palette

value

Gradation

level

Palette

Gradation

Gradation palette

Palette 0(default)

Gradation palette

value

level

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

0

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

1 1 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

16/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

1/31

2/31

3/31

4/31

5/31

6/31

7/31

8/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

Palette 8(default)

Palette 9(default)

Palette 10(default)

Palette 11(default)

Palette 12(default)

Palette 13(default)

Palette 14(default)

Palette 15(default)

Palette 1(default)

Palette 2(default)

Palette 3(default)

Palette 4(default)

Palette 5(default)

Palette 6(default)

Palette 7(default)

- 73 -

NJU6818

(32-16) Initial COM line

The “Initial COM line” instruction is used to specify the common driver that starts scanning display data. The line

address, corresponding to the initial COM line, is specified by the “Initial display line” instruction.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

0

D3

D2

D1

D0

1

0

1

0

SC3 SC2 SC1 SC0

SC3

0

SC2

0

SC1

0

SC0

0

Initial COM line (SHIFT=0)

COM0

Initial COM line (SHIFT=1)

COM79

0

1

COM4

COM75

0

1

0

COM8

COM71

0

1

COM16

COM63

0

1

0

COM24

COM55

0

1

0

1

COM32

COM47

0

1

0

COM40

COM39

0

1

COM48

COM31

1

0

COM56

COM23

1

0

1

COM64

COM15

1

0

1

0

COM72

COM7

1

0

1

Inhibited

1

0

1

0

1

0

1

SHIFT=0: Positive scan direction

SHIFT=1: Negative scan direction

(COM₀→ COM₇₉)

(COM₇₉→ COM₀)

(32-17) Display clock / Duty-1

The “Display clock / Duty-1” instruction is used to enable or disable the display clocks (CL, FLM, FR, and CLK),

and to control ON/OFF of the “Duty-1”. For more detail about the “Duty-1”, see (32-11) “Duty cycle ratio”.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

1

D3

*

D2

*

D1

D0

1

0

1

0

DSE SON

SON=0:

SON=1:

CL, FLM, FR, and CLK are level “0”

CL, FLM, FR, and CLK outputs are active.

DSE=0:

DSE=1:

Duty-1 OFF

Duty-1 ON

- 74 -

NJU6818

(32-18) Gradation mode control

The “Gradation mode control” is used to select display mode as follows.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

0

D3

D2

D1

*

D0

*

1

0

1

0

PWM C256

PWM register

PWM=0: Variable gradation mode

(Variable 16-gradation levels out of 32-gradation level of the gradation palette)

PWM=1: Fixed gradation mode

(Fixed 8-gradation levels)

C256 register

C256=0 256-color mode OFF (4,096-color in the default setting)

C256=1 256-color mode ON

(32-19) Data bus length

The “Data bus length” instruction is used to select 8- or 16- bit data bus length and determine the internal or

external oscillation. In the 16-bit data bus mode, instruction data must be 16-bit (D₁₅to D₀) as well as display data.

However, for the access to the instruction registers, the lower 8-bit data (D₇to D₀) of the 16-bit data is valid. For

the access to the DDRAM, all of the 16-bit data (D₁₅to D₀) is valid.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

1

D3

D2

D1

D0

1

0

1

0

HSW ABS CKS WLS

HSW register

HSW =0 :High speed access mode OFF

HSW=1 :High speed access mode ON (only in the 8-bit data bus length)

ABS register

ABS=0 :ABS mode OFF (normal)

ABS=1 :ABS mode ON

WLS register

WLS=0 :8-bit data bus length

WLS =1 :16-bit data bus length

CKS register

CKS =0 :Internal oscillation

(The OSC₁terminal must be fixed “1” or “0”.)

CKS =1 :External oscillation

(By the external clock into the OSC₁or external resister between the OSC₁and OSC₂.

OSC₂should be open when clock is inputted from OSC₁.)

- 75 -

NJU6818

(32-20) EVR control

The “EVR control” instruction is used to fine-tune the LCD driving voltage (V_LCD), so that it is possible to optimize

contrast level for a LCD panel.

This instruction must be programmed by upper 3-bit data first, next lower 4-bit data. And it becomes enabled when

the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the V_LCDfrom being

generated.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

0

D3

D2

D1

D0

1

0

1

0

DV3 DV2 DV1 DV0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

1

D3

*

D2

D1

D0

1

0

1

0

DV6 DV5 DV4

DV6

DV5

0

DV4 DV3

DV2

0

DV1

0

DV0

0

VLCD

0

:

Low

0

1

:

1

High

The formula of the V_LCDis shown below.

V_LCD[V] = 0.5 x V_REG+ M (V_REG– 0.5 x V_REG) / 127

V_BA= V_EEx 0.9

V_REG= V_REFx N

V_BA

V_REF

V_REG

N

: Output voltage of the reference voltage generator

: Input voltage of the voltage regulator

: Output voltage of the voltage regulator

: Register value for the voltage booster

: Register value for the EVR

M

- 76 -

NJU6818

(32-21) Frequency control

The “Frequency control” instruction is used to control the frame frequency for a LCD panel.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

1

D3

*

D2

Rf2

D1

Rf1

D0

Rf0

1

0

1

0

Rfx register (x=0, 1, 2)

The “Rfx” register is used to determine the feed back resister value for the internal oscillator, and it is possible to

adjust the frame frequency for the LCD modules.

Rf 2

0

Rf 1

0

Rf 0

0

Feedback resistor value

Reference value

0

1

0.8 x reference value

0.9 x reference value

1.1 x reference value

1.2 x reference value

0.7 x reference value

1.3 x reference value

Inhibited

0

1

0

1

0

1

0

1

0

1

(32-22) Discharge ON/OFF

Discharge circuit is used to discharge the electric charge of the capacitors on the V₁to V₄and the V_LCDterminals.

The “Discharge ON/OFF” instruction is usually required just after the internal power supply is turned off by setting

“0” into the “DCON” and “AMPON” registers, or just after the external power supply is turned off. During the

discharge operation, the internal or external power supply must not be turned on.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

1

D4

0

D3

*

D2

*

D1

D0

1

0

1

0

DIS2 DIS

DIS=0:

DIS=1:

Discharge OFF

Discharge ON

(Capacitors on the V_LCD, V₁, V₂, V₃and V₄)

DIS2=0:

DIS2=1:

Discharge OFF

Discharge ON

(Resistance between V_OUTand V_EE)

Note ) V_OUTand V_EEare internally connected with the resistor (100kΩ typical) in the power-ON.

- 77 -

NJU6818

(32-23) Instruction register address

The “Instruction register address” is used to specify the instruction register address, so that it is possible to read

out the contents of the instruction registers in combination with the “Instruction register read” instruction.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

1

D5

0

D4

0

D3

D2

D1

D0

1

0

1

0

RA3 RA2 RA1 RA0

(32-24) Instruction register read / ID read

The “Instruction register read” instruction is used to read out the contents of the instruction register in combination

with the “Instruction register address” instruction. Upper 4-bit of the read-out data is assigned to the ID data.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

0/1 0/1 0/1

D7

ID3

D6

ID2

D5

ID1

D4

ID0

D3

D2

D1

D0

0

1

Internal register data read

(32-25) Window end column address

The “Window end column address” is used to specify the column address for the window end point. The lower 4-

bit data is required to be programmed first and then the upper 3-bit data can be programmed.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

1

0

1

0

1

EX3 EX2 EX1 EX0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

0

D4

1

D3

D2

D1

D0

1

0

1

0

1

EX7 EX6 EX5 EX4

(32-26) Window end row address set

The “Window end row address” is used to specify the row address for the window end point. The lower 4-bit data

is required to be programmed first and then the upper 3-bit data can be programmed.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

0

D3

D2

D1

D0

1

0

1

0

1

EY3 EY2 EY1 EY0

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

0

D5

1

D4

1

D3

*

D2

D1

D0

1

0

1

0

1

EY6 EY5 EY4

- 78 -

NJU6818

(32-27) Initial reverse line

The “Initial reverse line” instruction is used to specify the initial reverse line address for the reverse line display.

Lower 4-bit data must be programmed first, next upper 3-bit data. It is programmed in between 00_Hand 4F_Hand

the line address beyond 4F_His inhibited. The address relation: LSi < LEi (i=7 to 0) must be maintained in the

reverse line display.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

0

D3

LS3

D2

LS2

D1

LS1

D0

LS0

1

0

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

0

D4

1

D3

*

D2

LS6

D1

LS5

D0

LS4

1

0

1

0

1

(32-28) Last reverse line

The “Last reverse line” instruction is used to specify the last reverse line address for the reverse line display. Lower

4-bit data must be programmed first, next upper 3-bit. It is programmed in between 00_Hand 4F_Hand the line

address beyond the 4F_His inhibited. The address relation: LSi < LEi (i=7 to 0) must be maintained in the reverse

line display.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

0

D3

LE3

D2

LE2

D1

LE1

D0

LE0

1

0

1

0

1

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

0

D6

1

D5

1

D4

1

D3

*

D2

LE6

D1

LE5

D0

LE4

1

0

1

0

1

(32-29) Reverse line display ON/OFF

The “Reverse line display ON/OFF” is used to enable or disable the reverse line display for the blink operation and

determine the reverse line display mode.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

0

D3

*

D2

*

D1

D0

1

0

1

0

1

BT LREV

LREV register

The “LREV” register is used to enable or disable the reverse line display.

LREV =0:

LREV =1:

Reverse line display OFF (Normal)

Reverse line display ON

- 79 -

NJU6818

BT register

The “BT” register is used to determine the reverse line display mode in the reverse line display ON (LREV=1)

status.

BT =0:

BT =1:

Normal reverse line display

Blink once every 32 frames

Display examples in the LREV=”1” and BT=”1”

ꢂꢀꢀꢀꢂ

ꢀꢂꢂꢂꢀ

ꢀꢂꢂꢂꢂ

ꢂꢀꢀꢀꢂ

ꢂꢂꢂꢂꢀ

ꢀꢂꢂꢂꢀ

ꢂꢀꢀꢀꢂ

ꢂꢂꢂꢂꢂ

ꢀꢂꢂꢂꢀ

ꢂꢀꢀꢀꢂ

ꢂꢀꢀꢀꢀ

ꢀꢂꢂꢂꢀ

ꢀꢀꢀꢀꢂ

ꢂꢀꢀꢀꢂ

ꢀꢂꢂꢂꢀ

ꢀꢀꢀꢀꢀ

Blink once every 32 frames

NJRC

LCD DRIVER

Low Power and

Low Voltage

Blink once every 32 frames

NJRC

←Initial reverse line address

←Last reverse line address

LCD DRIVER

Low Power and

Low Voltage

- 80 -

NJU6818

(32-30) Gradation Palette setting control

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

0

D4

1

D3

*

D2

*

D1

*

D0

PS

1

0

1

0

1

PS register

PS=0:

PS=1:

Lower 8 Gradation setting

Upper 8 Gradation setting

(32-31) PWM control

The “PWM control” is used to determine the PWM type for segment waveforms, where the type can be specified

for each of the SEGAi, SEGBi and SEGCi (i=0-103) drivers.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D7

1

D6

0

D5

1

D4

0

D3

D2

D1

D0

PWMS PWMA PWMB PWMC

1

0

1

0

1

PWMS register

PWMS=0: Type 1

PWMS=1: Type 2

PWMA, B and C registers

The “PWMA, PWMB and PWMC” registers are used to select the type 1-O or type 1-E.

PWMZ=0 (Z=A, B and C): Type 1-O

PWMZ=1 (Z=A, B and C): Type 1-E

PWM type1 (PWMS=”0”)

Odd line

Even line

“H”

“L”

CL

V_LCD

V₂

→

←

Type-O

Type-E

SEG

V_LCD

V₂

→

←

PWM type2 (PWMS=”1”)

“H”

CL

“L”

V_LCD

V₂

SEG

→

- 81 -

NJU6818

(33) The relation between Common drivers and Row addresses

Row address assignment of common drivers is programmed by the “SHIFT” register of the “Display control (1)”,

“Duty cycle ratio”, “Initial display line” and “Initial COM line” instructions.

When initial display line is “0”

If the “SHIFT” is “0”, the scan direction is normal. When the “LA₀to LA₆“ registers of the “Initial display line”

instruction is “0”, the “MY” corresponding to the initial COM line is “0” and is increasing during display.

When initial display line is not “0”

If the “SHIFT” is “1”, the scan direction is inversed. When the “LA₀to LA₆“ registers of the “Initial display line”

instruction is not “0”, the “MY” corresponding to the initial COM line is this setting value and is increasing during

display.

The followings are examples of setting the start-line 0 or 5 at 1/81, or 1/13 duty.

- 82 -

NJU6818

(33-1)Initial display line “0”, 1/81 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂

,

₀=”0000”, LA₆….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0

0001

76

0010

72

0011

64

0100

56

0101

48

0110

40

0111

32

1000

24

1001

16

1010

8

COM₀

COM₁

COM₂

COM₃

79

0

COM₄

COM₅

COM₆

COM₇

79

0

COM₈

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

79

0

79

0

79

0

79

0

79

0

79

0

79

0

79

0

79

75

79

71

79

63

79

55

79

47

79

39

79

31

79

23

79

15

79

7

79

(81^thCOM period) *1

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 81^thCOM period is not selected.

- 83 -

NJU6818

(33-2) Initial display line “0”, 1/13 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂

,

₀=”1001”, LA₆….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

0

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

8

COM₀

COM₁

COM₂

COM₃

11

COM₄

0

COM₅

COM₆

COM₇

COM₈

0

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

11

0

11

0

11

0

11

0

11

0

11

0

11

0

11

0

11

7

11

(13^thCOM period) *1

11

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 13^thCOM period is not selected.

- 84 -

NJU6818

(33-3)Initial display line “0”, 1/81 duty cycle (Common backward scan)

SHIFT=”1”(Common backward scan), DS₃, ₂

,

₀=”0000”, LA₆….LA₀=”00000000”(Initial display line 0)

1

SC₃

SC₂

SC₁

SC₀

0000

79

0001

75

0010

71

0011

63

0100

55

0101

47

0110

39

0111

31

1000

23

1001

15

1010

7

COM₀

COM₁

COM₂

COM₃

COM₄

COM₅

COM₆

COM₇

0

79

COM₈

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

0

79

0

79

0

79

0

79

0

79

0

79

0

79

0

79

0

79

0

79

76

79

72

79

64

79

56

79

48

79

40

79

32

79

24

79

16

79

8

79

(81^thCOM period) *1

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 81^thCOM period is not selected.

- 85 -

NJU6818

(33-4)Initial display line “5”, 1/81 duty cycle (Common forward scan)

SHIFT=”0”(Common forward scan), DS₃, ₂

,

₀=”0000”, LA₆….LA₀=”00000101”(Initial display line 5)

1

SC₃

SC₂

SC₁

SC₀

0000

5

0001

1

0010

0011

69

0100

61

0101

53

0110

45

0111

37

1000

29

1001

21

1010

13

COM₀

77

78

79

0

COM₁

COM₂

COM₃

COM₄

5

COM₅

COM₆

COM₇

COM₈

5

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

79

0

5

79

0

5

79

0

5

79

0

5

79

0

5

79

0

5

79

0

5

79

0

5

79

0

79

0

79

4

79

76

79

68

79

60

79

52

79

44

79

36

79

28

79

20

79

12

79

(81^thCOM period) *1

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

*1 : 81^thCOM period is not selected.

- 86 -

NJU6818

(33-5)Initial display line “0”, 1/80 duty cycle (Common forward scan, DSE=”1”)

SHIFT=”0”(Common forward scan), DS₃, ₂

,

₀=”0000”, LA₆….LA₀=”00000000”(Initial display line 0) DSE=”1”

1

SC₃

SC₂

SC₁

SC₀

0000

0

0001

76

0010

72

0011

64

0100

56

0101

48

0110

40

0111

32

1000

24

1001

16

1010

8

COM₀

COM₁

COM₂

COM₃

79

0

COM₄

COM₅

COM₆

COM₇

79

0

COM₈

COM₉

COM₁₀

COM₁₁

COM₁₂

COM₁₃

COM₁₄

COM₁₅

COM₁₆

COM₁₇

COM₁₈

COM₁₉

COM₂₀

COM₂₁

COM₂₂

COM₂₃

COM₂₄

COM₂₅

COM₂₆

COM₂₇

COM₂₈

COM₂₉

COM₃₀

COM₃₁

COM₃₂

COM₃₃

COM₃₄

COM₃₅

COM₃₆

COM₃₇

COM₃₈

COM₃₉

COM₄₀

COM₄₁

COM₄₂

COM₄₃

COM₄₄

COM₄₅

COM₄₆

COM₄₇

COM₄₈

COM₄₉

COM₅₀

COM₅₁

COM₅₂

COM₅₃

COM₅₄

COM₅₅

COM₅₆

COM₅₇

COM₅₈

COM₅₉

COM₆₀

COM₆₁

COM₆₂

COM₆₃

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

79

0

79

0

79

0

79

0

79

0

79

0

79

0

79

0

79

75

71

63

55

47

39

31

23

15

7

DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line

- 87 -

NJU6818

ꢀ

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage (1)

Supply Voltage (2)

Supply Voltage (3)

Supply Voltage (4)

Supply Voltage (5)

Supply Voltage (6)

Input Voltage

SYMBOL

V_DD

CONDITION

TERMINAL

V_DD

RATING

-0.3 to +4.0

UNIT

V

V_EE

-0.3 to +4.0

V

V_OUT

-0.3 to +19.0

-0.3 to V_LCD+ 0.3

-0.3 to V_DD+ 0.3

-45 to +125

V

V_SS=0V

V_REG

V

Ta = +25°C

V_LCD

V

V₁, V₂, V₃, V₄

V_I

V₁, V₂, V₃, V₄

*1

V

Storage Temperature

T_stg

°C

Note 1) D₀to D₁₅, CSb, RS, RDb, WRb, OSC₁, RESb, TEST_1,TEST₂, terminals.

ꢁ

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Supply Voltage

SYMBOL

V_DD1

TERMINAL

V_DD

MIN

1.7

2.4

5

TYP

MAX

3.3

UNIT

NOTE

*1

V

V_DD2

3.3

*2

V_EE

V_LCD

V_OUT

V_REG

V_REF

3.3

*3

*4

V_LCD

18.0

_OUT× 0.9

3.3

V_OUT

V_REG

V_REF

Operating Voltage

V

2.1

-30

*5

Operating

T_opr

85

°C

Temperature

Note1) Applies to the condition when the reference voltage generator is not used.

Note2) Applies to the condition when the reference voltage generator is used.

Note3) Applies to the condition when the voltage booster is used.

Note4) The following relation among the supply voltages must be maintained.

V_SS<V₄<V₃<V₂<V₁<V_LCD<V_OUT

Note5) The relation: V_REF<V_EEmust be maintained.

- 88 -

NJU6818

ꢀ DC CHARACTERISTICS 1

V_SS= 0V, V_DD= +1.7 to +3.3V, Ta = -30 to +85°C

SYM

PARAMETER

BOL

CONDITION

MIN

TYP

MAX

UNIT NOTE

V_IH

V_IL

V_OH1

V_OL1

V_OH2

V_OL2

I_LI

High level input voltage

Low level input voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

Input leakage current

0.8 V_DD

0

V_DD

V

*1

*2

*3

*4

*5

0.2V_DD

I_OH= -0.4mA

V_DD- 0.4

V

I_OL= 0.4mA

0.4

V

I_OH= -0.1mA

I_OL= 0.1mA

V_I= V_SSor V_DD

V_DD- 0.4

V

0.4

10

2

4

15

445

101

14.4

V

-10

µA

I_LO

Output leakage current

V_LCD= 10V

V_LCD= 6V

V_DD= 3V

1

2

R_ON1

Driver ON-resistance

*6

|∆V_ON| = 0.5V

kΩ

µA

I_STB

*7

CSb=V_DD, Ta=25°C

Stand-by current

f_OSC1

f_OSC2

f_OSC3

f_r1

f_r2

f_r3

309

69

10.0

377

85

*8

*9

*10

V_DD= 3V

Internal oscillation

Frequency

kHz

Ta = 25°C

12.2

382

84

Rf=24kΩ

Rf=120kΩ

Rf=820kΩ

External oscillation

Frequency

kHz

V

*11

*12

12.8

N-time booster (N=2 to 6)

Voltage converter

output voltage

(N x V_EE

)

V_OUT

I_DD1

I_DD2

I_DD3

I_DD4

I_DD5

I_DD6

V_BA

x 0.95

RL = 500kΩ (V_OUT- V_SS

)

V_DD= 3V, 6-time booster

Whole ON pattern

Supply current (1)

Supply current (2)

Supply current (3)

Supply current (4)

Supply current (5)

Supply current (6)

V_BAOperating voltage

760

930

1140

1400

780

V_DD= 3V, 6-time booster

Checker pattern

V_DD= 3V, 5-time booster

Whole ON pattern

520

*13

µA

V_DD= 3V, 5-time booster

Checker pattern

650

980

V_DD= 3V, 4-time booster

Whole ON pattern

360

540

V_DD= 3V, 4-time booster

Checker pattern

450

680

(0.9 V_EE

)

(0.9 V_EE

)

V_EE= 2.4 to 3.3V

0.9 V_EE

V

*14

*15

x 0.98

x 1.02

(V_REFx N)

x 0.97

(V_REFx N)

x 1.03

V_REG

(V_REFx N)

V_REGOperating voltage

V_REF= 0.9 x V_EE

N-time booster (N=2 to 6)

V₂

V₃

V_D12

V_D34

V_D24

-100

-30

0

+100

+30

Output Voltage

mV

*16

- 89 -

NJU6818

ꢀ CLOCK and FRAME FREQUENCY

Display duty cycle ratio (1/D) <DSE=0>

PARAMETER SYMBOL

NOTE

FLM

Display mode

1/81 to 1/57

f_OSC/ (62xD)

_OSC/ (14xD)

_OSC/ (2xD)

f_CK/ (62xD)

_CK/ (14xD)

_CK/ (2xD)

1/47 to 1/27

1/17, 1/13

16 Gradation mode

f_OSC/ (62xDx2)

f_OSC/ (62xDx4)

f_OSC/ (14xDx4)

f_OSC/ (2xDx4)

f_CK/ (62xDx4)

f_CK/ (14xDx4)

f_CK/ (2xDx4)

Internal

f_OSC

Simplified

f

f_OSC/ (14xDx2)

f_OSC/ (2xDx2)

f_CK/ (62xDx2)

f_CK/ (14xDx2)

f_CK/ (2xDx2)

clock

8 gradation mode

B&W mode

f

16 Gradation mode

External

f_CK

Simplified

f

clock

8 gradation mode

B&W mode

f

- 90 -

NJU6818

APPLIED TERMINALS and CONDITIONS

Note 1) D₀-D₁₅, CSb, RS, RDb, WRb, P/S, SEL68, RESb

Note 2) D₀-D₁₅

Note 3) CL, FLM, FR, CLK

Note 4) CSb, RS, SEL68, RDb, WRb, P/S, RESb, OSC₁

Note 5) D₀-D₁₅in high impedance

Note 6) SEGA₀-SEGA₁₀₃, SEGB₀-SEGB₁₀₃, SEGC₀-SEGC₁₀₃, COM₀-COM₇₉

- Defines the resistance between the COM/SEG terminals and the power supply terminals (V_LCD, V₁, V₂, V₃and V₄)

at the condition of 0.5V deference and 1/9 LCD bias ratio

Note 7) V_DD

- The oscillator is halted, CSb=”1” (disabled), No-load on the COM/SEG drivers

Note 8) OSC

- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the variable gradation mode

Note 9) OSC

- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the fixed gradation mode

Note 10) OSC

- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the Black & White mode

Note 11)

V

_DD=3V, Ta=25°C

Note 12) V_OUT

- Applies to the condition when the internal voltage booster, the internal oscillator and the internal power circuits are

used

- V_EE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/4 to 1/10 LCD bias, 1/81 duty cycle, No-load on the COM/SEG drivers

- RL=500kΩ between the VOUT and the VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”

Note 13) V_DD

- Applies to the condition using the internal oscillator and the internal power circuits, no access between the LSI and

MPU

- EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in the gradation mode, No-load on the

COM/SEG drivers

- V_DD=V_EE, V_REF=0.9V_EE, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”, 1/81 Duty cycle, Ta=25°C

Note 14) V_BA

- Applies to the condition that V_BA=V_REFand the voltage booster N= 1, DCON=”0”, V_OUT=13.5V input.

Note 15) V_REG

- V_EE=2.4V to 3.3V, V_REF=0.9V_EE, V_OUT=18V, 1/4 to 1/10 LCD bias ratio, 1/81 duty cycle, EVR=(1,1,1,1,1,1,1),

- Checkerboard display, No-load on the COM/SEG drivers, the voltage booster N=2 to 6, CA1=CA2=1.0uF,

CA3=0.1uF, DCON=”0”, AMPON=”1”, NLIN=”0”

Note 16)

V_LCD, V₁, V₂, V₃, V₄

- V_EE=3.0V, V_REF=0.9V_EE, V_OUT=15V, 1/4 to 1/10 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, No-load on the

COM/SEG drivers, voltage booster N=5, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”

V_LCD

V₁

V_D12: (1)-(2)

V_D34: (3)-(4)

V_D24: (2)-(4)

(1)

(2)

V₂

V₃

(3)

(4)

V₄

V_SS

- 91 -

NJU6818

ꢀ AC CHARACTERISTICS

ꢀ

Write operation (80-type MPU)

t_AS8

t_AH8

CSb

RS

WRb

t_WRLW8

t_WRHW8

t_DS8

t_DH8

D₀to D₁₅

t_CYC8

MIN.

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

t_AH8

t_AS8

MAX.

UNIT

TERMINAL

Address hold time

0

ns

CSb

RS

Address setup time

0

ns

System cycle time

t_CYC8

t_WRLW8

t_WRHW8

90

35

ns

Enable ”L” level pulse width

Enable ”H” level pulse width

WRb

Data setup time

Data hold time

t_DS8

t_DH8

30

5

ns

D₀to D₁₅

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

Address hold time

Address setup time

SYMBOL

MIN.

0

MAX.

UNIT

TERMINAL

t_AH8

t_AS8

ns

CSb

RS

System cycle time

t_CYC8

t_WRLW8

t_WRHW8

160

70

ns

Enable ”L” level pulse width

Enable ”H” level pulse width

WRb

70

Data setup time

Data hold time

t_DS8

t_DH8

40

5

ns

D₀to D₁₅

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

t_CYC8

t_WRLW8

t_WRHW8

180

80

ns

Enable ”L” level pulse width

Enable ”H” level pulse width

WRb

80

Data setup time

Data hold time

t_DS8

t_DH8

70

10

ns

D₀to D₁₅

Note) Each timing is specified based on 20% and 80% of V_DD

.

- 92 -

NJU6818

ꢀ

Read operation (80-type MPU)

t_AH8

t_AS8

CSb

RS

t_WRLR8

RDb

t_WRHR8

t_RDH8

D₀to D₁₅

t_RDD8

t_CYC8

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

t_AH8

0

ns

CSb

RS

Address setup time

t_AS8

0

ns

System cycle time

t_CYC8

t_WRLR8

t_WRHR8

180

80

ns

RDb

Enable ”L” level pulse width

Enable ”H” level pulse width

80

Read Data delay time

Read Data hold time

t_RDD8

t_RDH8

60

ns

CL=15pF

D₀to D₁₅

0

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

t_CYC8

t_WRLR8

t_WRHR8

180

80

ns

RDb

Enable ”L” level pulse width

Enable ”H” level pulse width

80

Read Data delay time

Read Data hold time

t_RDD8

t_RDH8

60

ns

CL=15pF

D₀to D₁₅

0

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

t_CYC8

t_WRLR8

t_WRHR8

300

140

ns

RDb

Enable ”L” level pulse width

Enable ”H” level pulse width

Read Data delay time

Read Data hold time

t_RDD8

t_RDH8

130

ns

CL=15pF

D₀to D₁₅

0

Note) Each timing is specified based on 20% and 80% of V_DD

.

- 93 -

NJU6818

ꢀ

Write operation (68-type MPU)

t_AS6

t_AH6

CSb

RS

R/W

(WRb)

t_ELW6

t_EHW6

E

(RDb)

t_DS6

t_DH6

D₀to D₁₅

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

t_AH6

t_AS6

MIN.

MAX.

UNIT

TERMINAL

Address hold time

0

ns

CSb

RS

Address setup time

0

ns

System cycle time

t_CYC6

t_ELW6

t_EHW6

90

35

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

Data setup time

Data hold time

t_DS6

t_DH6

40

5

ns

D₀to D₁₅

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CSb

RS

System cycle time

t_CYC6

t_ELW6

t_EHW6

160

70

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

70

Data setup time

Data hold time

t_DS6

t_DH6

50

5

ns

D₀to D₁₅

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CSb

RS

System cycle time

t_CYC6

t_ELW6

t_EHW6

180

80

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

80

Data setup time

Data hold time

t_DS6

t_DH6

70

10

ns

D₀to D₁₅

Note) Each timing is specified based on 20% and 80% of V_DD

.

- 94 -

NJU6818

ꢀ

Read operation (68-type MPU)

t_AS6

t_AH6

CSb

RS

R/W

(WRb)

t_ELR6

t_EHR6

E

(RDb)

t_RDH6

D₀to D₁₅

t_RDD6

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

t_AH6

0

ns

CSb

Address setup time

t_AS6

0

ns

RS

System cycle time

t_CYC6

t_ELR6

t_EHR6

180

80

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

80

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

70

CL=15pF

D₀to D₁₅

0

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

t_AH6

0

ns

CSb

Address setup time

t_AS6

0

ns

RS

System cycle time

t_CYC6

t_ELR6

t_EHR6

180

80

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

80

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

70

CL=15pF

D₀to D₁₅

0

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

t_AH6

0

ns

CSb

Address setup time

t_AS6

0

ns

RS

300

140

System cycle time

t_CYC6

t_ELR6

t_EHR6

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

130

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

CL=15pF

D₀to D₁₅

0

Note) Each timing is specified based on 20% and 80% of V_DD

.

- 95 -

NJU6818

ꢀ

Serial interface

CSb

t_CSH

t_CSS

RS

t_ASS

t_AHS

t_SLW

t_SHW

SCL

t_CYCS

t_DSS

t_DHS

SDA

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

UNIT

PARAMETER

Serial clock cycle

SYMBOL CONDITION

t_CYCSB

MIN.

MAX.

TERMINAL

50

20

300

20

ns

SCL ”H” level pulse width

SCL ”H” level pulse width 2

SCL ”L” level pulse width

Address setup time

Address hold time

t_SHW

SCL

t_SHW2

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

Note 2)

RS

Data setup time

SDA

Data hold time

CSb – SCL time

CSb hold time

t_CSS

20

ns

CSb

t_CSH

20

ns

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

TERMINAL

Serial clock cycle

t_CYCS

50

20

400

20

ns

SCL ”H” level pulse width

SCL ”H” level pulse width 2

SCL ”L” level pulse width

Address setup time

Address hold time

t_SHW

SCL

t_SHW2

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

Note 2)

RS

Data setup time

SDA

Data hold time

CSb – SCL time

CSb hold time

t_CSS

20

ns

CSb

t_CSH

20

ns

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

TERMINAL

Serial clock cycle

t_CYCS

80

35

500

35

ns

SCL ”H” level pulse width

SCL ”H” level pulse width 2

SCL ”L” level pulse width

Address setup time

Address hold time

t_SHW

SCL

t_SHW2

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

Note 2)

RS

Data setup time

SDA

Data hold time

CSb – SCL time

t_CSS

35

ns

CSb

t_CSH

35

ns

CSb hold time

Note) Each timing is specified based on 20% and 80% of V_DD

.

Note 2) t_SHW2applies to the condition when the ID read-out. Refer to the (18) “Chip Identification” for the detail.

- 96 -

NJU6818

ꢀ

Display control timing

CLK

t_DCL

CL

t_DFLM

FLM

t_FR

FR

Output timing

PARAMETER

FLM delay time

FR delay time

CL delay time

(V_DD=2.4 to 3.3V, Ta=-30 to +85°C)

SYMBOL

CONDITION

CL=15pF

MIN.

MAX.

UNIT

TERMINAL

t_DFLM

0

500

200

ns

FLM

t_FR

FR

CL

t_DCL

Output timing

PARAMETER

FLM delay time

FR delay time

CL delay time

(V_DD=1.7 to 2.4V, Ta=-30 to +85°C)

SYMBOL

CONDITION

CL=15pF

MIN.

MAX.

UNIT

TERMINAL

t_DFLM

0

1000

200

ns

FLM

t_FR

FR

CL

t_DCL

Note) Each timing is specified based on 20% and 80% of V_DD

.

- 97 -

NJU6818

ꢀ

Input clock timing

t_CKLW

t_CKHW

OSC₁

(V_DD=1.7 to 3.3V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

TERMINAL

OSC₁

OSC₁“H” level pulse width (1)

OSC₁“L” level pulse width (1)

OSC₁“H” level pulse width (2)

OSC₁“L” level pulse width (2)

OSC₁“H” level pulse width (3)

OSC₁“L” level pulse width (3)

t_CKHW1

t_CKLW1

t_CKHW2

t_CKLW2

t_CKHW3

t_CKLW3

1.12

4.95

34.7

1.62

7.25

50.0

µs

1

OSC₁

2

OSC₁

3

Note) Each timing is specified based on 20% and 80% of V_DD

.

Note 1) Applied to the variable gradation mode /MON=”0”,PWM=”0”

Note 2) Applied to the fixed gradation mode /MON=”0”,PWM=”1”

Note 3) Applied to the B&W mode /MON=”1”

ꢀ

Reset input timing

t_RW

RESb

t_R

Internal circuit

During reset

End of reset

status

(V_DD=2.4 to 3.3V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL

CONDITION

MIN.

10.0

MAX.

Terminal

Reset time

t_R

1.0

µs

RESb “L” level pulse width

t_RW

RESb

(V_DD=1.7 to 2.4V, Ta=-30 to +85°C)

UNIT

PARAMETER

SYMBOL

MIN.

10.0

MAX.

Terminal

Reset time

t_R

1.5

µs

RESb “L” level pulse width

t_RW

RESb

Note) Each timing is specified based on 20% and 80% of V_DD

.

- 98 -

NJU6818

ꢀ

Typical characteristic

PARAMETER

Basic delay time of gate

SYMBOL

Ta=+25°C, V_SS=0V, V_DD=3.0V

MIN

TYP

10

MAX

UNIT

ns

Input output terminal type

(a) Input circuit

V_DD

Terminals:

CSb, RS, RDb, WRb, SEL68,

P/S, RESb

I

Input signal

V_SS(0V)

(b) Output circuit

Terminals:

FLM, CL, FR, CLK

V_DD

Output control signal

Output signal

O

V_SS(0V)

(c) Input/Output circuit

V_DD

Terminals:

D₀to D₁₅

I/O

Input signal

V_SS(0V)

Input control signal

V_DD

Output control signal

Output signal

V_SS(0V)

- 99 -

NJU6818

(d) Display output circuit

V_LCD

V₁/V₂

Output control

signal 1

Output control signal 2

Output control signal 4

O

Output control

signal 3

V_SS(0V)

V₃/V₄

V_SS(0V)

Terminals:

SEGA₀to SEGA₁₀₃

SEGB₀to SEGB₁₀₃

SEGC₀to SEGC₁₀₃

COM₀to COM₇₉

- 100 -

NJU6818

ꢀ APPLICATION CIRCUIT EXAMPLES

(1) MPU Connections

80-type MPU interface

1.7V to 3.3V

V_CC

V_DD

A

₀

RS

A to A₇

(80-type MPU) ¹

IORQb

Decoder

8

7

CSb

D₀to D₇

RDb

WRb

RDb

WR

RESb

V_SS

GND

RESET

68-type MPU interface

1.7V to 3.3V

V_CC

V_DD

A

₀

RS

A₁to A₁₅

(68-type MPU)

VMA

Decoder

8

15

CSb

D₀to D₇

E

R/W

RESb

D₀to D₇

RDb(E)

WRb(R/W)

RESb

V_SS

GND

RESET

Serial interface

1.7V to 3.3V

V_CC

V_DD

A

₀

A

₁

to A

₇

RS

Decoder

RESET

7

CSb

(MPU)

PORT₁

SDA

SCL

RESb

PORT₂

RESb

V_SS

GND

- 101

NJU6818

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

- 102 -


型号：	NJU6818CJ
厂家：	NEW JAPAN RADIO
描述：	Liquid Crystal Driver, 392-Segment, CMOS, DIE-748 驱动器 CD
文件：	总102页 (文件大小：844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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