NJU6821H [NJRC]
Liquid Crystal Driver, 478-Segment, CMOS, TCP;
| 型号： | NJU6821H |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Liquid Crystal Driver, 478-Segment, CMOS, TCP 驱动 接口集成电路 |
| 文件： | 总113页 (文件大小：1127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6821
Preliminary
82-common X 128RGB-Segment, in 256-Color
STN LCD DRIVER
ꢀ
GENERAL DESCRIPTION
ꢀ
PACKAGE OUTLINE
The NJU6821 is a STN LCD driver with 82-common x
128RGB-segment
in
256-color.
It
consists
of
384(128xRGB)-segment, 82-common drivers, and serial
and parallel MPU interface circuits, internal power supply
circuits, gradation palettes and 81,920-bit for graphic and
2,048-bit for icon display data RAM.
Each segment driver outputs 8-(for R and G) and 4-(for
B) gradation level out of 32-gradation level of gradation
palette.
NJU6821CJ
Since the NJU6821 provides a low operating voltage of
1.7V and low operating current, it is ideally suited for
battery-powered handheld applications.
In addition, it is possible to drive up to 164 x 128 pixels
LCD panel when use two of NJU6821 as a master and
slave LSIs.
ꢀ
FEATURES
ꢁ
ꢁ
ꢁ
256-color STN LCD driver
LCD drivers
80 and 2-icon commons, 128RGB-segments, 4RGB-icon segments
81,920-bit for graphic display
Display data RAM (DDRAM)
2,048-bit for icon display
ꢁ
Color display mode
8-(R and G) or 4-(B) gradation level out of 32-gradation level
of gradation palette
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Black & white display mode
82 x 384 pixels in B&W
8/16bit Parallel interface directly- connective to 68/80 series MPU
Programmable 8- or 16-bit data bus length for display data
3-/4-line Serial interface
Programmable duty and bias ratios
Programmable internal voltage booster (Maximum 7-times)
Programmable contrast control using 128-step EVR
Various instructions
Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF,
column address, row address, N-line inversion, Initial display line, Initial COM line, Read-modify-write,
Gradation mode control, Increment control, Data bus length, Discharge ON/OFF,
Duty cycle ratio, LCD bias ratio, Boost level, EVR control, Power save ON/OFF, etc
Low operating current
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
Low logic supply voltage
LCD driving supply voltage
C-MOS process
1.7V to 3.3V
5.0V to 18.0V
Package
Bumped chip / TCP
2003/01/28
- 1 -
NJU6821
ꢀPAD LOCATION
DMY6(L)
DMY6(R)
SEGSA2
SEGSC3
COM40
COM66
DMY7(L)
DMY7(R)
1
Note1) The PADs of (L), (R) and (C) are shorted mutually in the LSI.
Note2) The DMY PADs are electrically open.
Chip Center
Chip Size
:X= 0µm, Y= 0µm
:19.91mm x 2.55mm
Chip Thickness
Bump Size
:625µm ± 25µm
:100µm x 32µm
Bump Pitch
Bump Height
Bump Material
:50µm(Min)
:14.0~22.5µm (Typical 18µm) <tolerance : ±3µm >
:Au
Alignment marks
a
a: 30µm
b: 6µm
d
c: 120µm
d: 27µm
d
b
Alignment mark coordinates
c
a
X=-9732µm, Y=-1052µm
X= 9732µm, Y=-1052µm
b
c
- 2 -
NJU6821
DMY3(R)
DMY3(L)
SEGSC1
Y
SEGSA0
COMI0
COM0
X
COM25
DMY2(R)
DMY2(L)
PAD size
VSSA, VSS, VDD, VSSH, VEE, VOUT PADs types
17to19, 21to23, 29to31, 37to39, 43to45, 77to79, 91to93,
109to111, 112to114, 140to142
118
18
ｙ
ｙ
ｙ
x
x
x
106
50
50
- 3 -
NJU6821
ꢀPAD COORDINATES 1
Chip Size 19910µm x 2550µm (Chip Center 0µm x 0µm )
PAD
No.
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X (µm)
Y (µm)
Terminal
X (µm)
Y (µm)
No.
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
1
2
3
4
5
6
7
8
DMY0(L)
DMY0(R)
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
VSSA(L)
VSSA(C)
VSSA(R)
TEST
VDD(L)
VDD(C)
VDD(R)
RESb
CSb
RS
VSS(L)
VSS(C)
VSS(R)
M/S
VDDA
P/S
-9625 -1068 52
-9575 -1068 53
-9525 -1068 54
-9475 -1068 55
-9425 -1068 56
-9375 -1068 57
-9325 -1068 58
-9275 -1068 59
-9225 -1068 60
-9175 -1068 61
-9125 -1068 62
-9075 -1068 63
-9025 -1068 64
-8975 -1068 65
-8925 -1068 66
-8875 -1068 67
-8670 -1068 68
-8500 -1068 69
-8330 -1068 70
-8171 -1068 71
-7990 -1068 72
-7820 -1068 73
-7650 -1068 74
-7480 -1068 75
-7310 -1068 76
-7140 -1068 77
-6970 -1068 78
-6800 -1068 79
-6630 -1068 80
-6448 -1068 81
-6290 -1068 82
-6120 -1068 83
-5950 -1068 84
-5780 -1068 85
-5610 -1068 86
-5440 -1068 87
-5270 -1068 88
-5111 -1068 89
-4930 -1068 90
-4760 -1068 91
-4590 -1068 92
-4420 -1068 93
-4250 -1068 94
-3995 -1068 95
D10
D11
D12
D13
D14
-2550
-2380
-2210
-2040
-1870
-1700
-1472
-1340
-1190
-1020
-850
-680
-510
-340
-107
74
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
C4+(L)
C4+(R)
C4-(L)
6120
6290
6460
6630
6800
6970
7140
7310
7480
7650
7820
7990
8160
8330
8500
8670
8875
8925
8975
9025
9075
9125
9175
9225
9275
9325
9375
9425
9475
9525
9575
9625
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-900
-850
-800
-750
-700
-650
-600
-550
-500
-450
-400
-350
-300
-250
-200
-150
-100
C4-(R)
C5+(L)
C5+(R)
C5-(L)
D15
VSS(L)
VSS(C)
VSS(R)
CL
FLM
FR
C5-(R)
9
C6+(L)
C6+(R)
C6-(L)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
C6-(R)
CLK
VLCD(L)
VLCD(R)
VOUT(L)
VOUT(R)
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
DMY1(L)
DMY1(R)
DMY2(L)
DMY2(R)
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
OSC1
OSC2
VSSH(L)
VSSH(C)
VSSH(R)
VLCD(L)
VLCD(R)
V1(L)
V1(R)
V2(L)
V2(R)
V3(L)
196
318
510
680
850
1020
1190
1360
1530
1700
1870
2040
2210
2380
2550
2693
2879
3060
3230
3400
3570
3740
3910
4102
4250
4420
4590
4760
4930
5100
5270
5440
5610
5780
5950
V3(R)
V4(L)
V4(R)
VREG(L)
VREG(R)
VBA(L)
VBA(R)
VREF
SEL68
VSSA(L)
VSSA(C)
VSSA(R)
WRb
VEE(L)
VEE(C)
VEE(R)
VSSH(L)
VSSH(C)
VSSH(R)
C1+(L)
C1+(R)
C1-(L)
C1-(R)
C2+(L)
C2+(R)
C2-(L)
C2-(R)
C3+(L)
C3+(R)
C3-(L)
C3-(R)
RDb
VDD(L)
VDD(C)
VDD(R)
D0/SCL
D1/SDA
44 D2/EXCS
45 D3/SMODE -3740 -1068 96
46
47
48
49
50
51
D4/SPOL -3570 -1068 97
D5
D6
D7
D8
D9
-3400 -1068 98
-3230 -1068 99
-3060 -1068 100
-2890 -1068 101
-2720 -1068 102
-50
0
- 4 -
NJU6821
ꢀPAD COORDINATES 2
Chip Size 19910µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
Terminal
X(µm)
Y(µm)
Terminal
X (µm)
Y (µm) PAD No. Terminal
X (µm)
Y (µm)
No.
154
155
156
157
158
159
160
161
162
163
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMI0
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9675
9625
9575
9525
9475
9425
9375
9325
9275
9225
9175
9125
9075
9025
8975
8925
8875
8825
8775
8725
8675
8625
8575
8525
8475
8425
8375
8325
8275
8225
8175
8125
8075
50
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
SEGB10
SEGC10
SEGA11
SEGB11
SEGC11
SEGA12
SEGB12
SEGC12
SEGA13
SEGB13
SEGC13
SEGA14
SEGB14
SEGC14
SEGA15
SEGB15
SEGC15
SEGA16
SEGB16
SEGC16
SEGA17
SEGB17
SEGC17
SEGA18
SEGB18
SEGC18
SEGA19
SEGB19
SEGC19
SEGA20
SEGB20
SEGC20
SEGA21
SEGB21
SEGC21
SEGA22
SEGB22
SEGC22
SEGA23
SEGB23
SEGC23
SEGA24
SEGB24
SEGC24
SEGA25
SEGB25
SEGC25
SEGA26
SEGB26
SEGC26
SEGA27
8025
7975
7925
7875
7825
7775
7725
7675
7625
7575
7525
7475
7425
7375
7325
7275
7225
7175
7125
7075
7025
6975
6925
6875
6825
6775
6725
6675
6625
6575
6525
6475
6425
6375
6325
6275
6225
6175
6125
6075
6025
5975
5925
5875
5825
5775
5725
5675
5625
5575
5525
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
SEGB27
SEGC27
SEGA28
SEGB28
SEGC28
SEGA29
SEGB29
SEGC29
SEGA30
SEGB30
SEGC30
SEGA31
SEGB31
SEGC31
SEGA32
SEGB32
SEGC32
SEGA33
SEGB33
SEGC33
SEGA34
SEGB34
SEGC34
SEGA35
SEGB35
SEGC35
SEGA36
SEGB36
SEGC36
SEGA37
SEGB37
SEGC37
SEGA38
SEGB38
SEGC38
SEGA39
SEGB39
SEGC39
SEGA40
SEGB40
SEGC40
SEGA41
SEGB41
SEGC41
SEGA42
SEGB42
SEGC42
SEGA43
SEGB43
SEGC43
SEGA44
5475
5425
5375
5325
5275
5225
5175
5125
5075
5025
4975
4925
4875
4825
4775
4725
4675
4625
4575
4525
4475
4425
4375
4325
4275
4225
4175
4125
4075
4025
3975
3925
3875
3825
3775
3725
3675
3625
3575
3525
3475
3425
3375
3325
3275
3225
3175
3125
3075
3025
2975
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
164 SEGSA0
165 SEGSB0
166 SEGSC0
167 SEGSA1
168 SEGSB1
169 SEGSC1
170 DMY3(L)
171 DMY3(R)
172 DMY4(L)
173 DMY4(R)
1068 223
1068 224
1068 225
1068 226
1068 227
1068 228
1068 229
1068 230
1068 231
1068 232
1068 233
1068 234
1068 235
1068 236
1068 237
1068 238
1068 239
1068 240
1068 241
1068 242
1068 243
1068 244
1068 245
1068 246
1068 247
1068 248
1068 249
1068 250
1068 251
1068 252
1068 253
1068 254
1068 255
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
SEGA0
SEGB0
SEGC0
SEGA1
SEGB1
SEGC1
SEGA2
SEGB2
SEGC2
SEGA3
SEGB3
SEGC3
SEGA4
SEGB4
SEGC4
SEGA5
SEGB5
SEGC5
SEGA6
SEGB6
SEGC6
SEGA7
SEGB7
SEGC7
SEGA8
SEGB8
SEGC8
SEGA9
SEGB9
SEGC9
SEGA10
- 5 -
NJU6821
ꢀPAD COORDINATES 3
Chip Size 19910µm x 2550µm (Chip Center 0µm x 0µm )
PAD
No.
PAD
No.
Terminal
X(µm)
Y(µm)
Terminal
X (µm)
Y (µm) PAD No. Terminal
X (µm)
Y (µm)
307 SEGB44
308 SEGC44
309 SEGA45
310 SEGB45
311 SEGC45
312 SEGA46
313 SEGB46
314 SEGC46
315 SEGA47
316 SEGB47
317 SEGC47
318 SEGA48
319 SEGB48
320 SEGC48
321 SEGA49
322 SEGB49
323 SEGC49
324 SEGA50
325 SEGB50
326 SEGC50
327 SEGA51
328 SEGB51
329 SEGC51
330 SEGA52
331 SEGB52
332 SEGC52
333 SEGA53
2925
2875
2825
2775
2725
2675
2625
2575
2525
2475
2425
2375
2325
2275
2225
2175
2125
2075
2025
1975
1925
1875
1825
1775
1725
1675
1625
1575
1525
1475
1425
1375
1325
1275
1225
1175
1125
1075
1025
975
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
SEGB61
SEGC61
SEGA62
SEGB62
SEGC62
SEGA63
SEGB63
SEGC63
SEGA64
SEGB64
SEGC64
SEGA65
SEGB65
SEGC65
SEGA66
SEGB66
SEGC66
SEGA67
SEGB67
SEGC67
SEGA68
SEGB68
SEGC68
SEGA69
SEGB69
SEGC69
SEGA70
SEGB70
SEGC70
SEGA71
SEGB71
SEGC71
SEGA72
SEGB72
SEGC72
SEGA73
SEGB73
SEGC73
SEGA74
SEGB74
SEGC74
SEGA75
SEGB75
SEGC75
SEGA76
SEGB76
SEGC76
SEGA77
SEGB77
SEGC77
SEGA78
375
325
275
225
175
125
75
25
-25
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
SEGB78
SEGC78
SEGA79
SEGB79
SEGC79
SEGA80
SEGB80
SEGC80
SEGA81
SEGB81
SEGC81
SEGA82
SEGB82
SEGC82
SEGA83
SEGB83
SEGC83
SEGA84
SEGB84
SEGC84
SEGA85
SEGB85
SEGC85
SEGA86
SEGB86
SEGC86
SEGA87
SEGB87
SEGC87
SEGA88
SEGB88
SEGC88
SEGA89
SEGB89
SEGC89
SEGA90
SEGB90
SEGC90
SEGA91
SEGB91
SEGC91
SEGA92
SEGB92
SEGC92
SEGA93
SEGB93
SEGC93
SEGA94
SEGB94
SEGC94
SEGA95
-2175
-2225
-2275
-2325
-2375
-2425
-2475
-2525
-2575
-2625
-2675
-2725
-2775
-2825
-2875
-2925
-2975
-3025
-3075
-3125
-3175
-3225
-3275
-3325
-3375
-3425
-3475
-3525
-3575
-3625
-3675
-3725
-3775
-3825
-3875
-3925
-3975
-4025
-4075
-4125
-4175
-4225
-4275
-4325
-4375
-4425
-4475
-4525
-4575
-4625
-4675
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
-75
-125
-175
-225
-275
-325
-375
-425
-475
-525
-575
-625
-675
-725
-775
-825
-875
-925
-975
-1025
-1075
-1125
-1175
-1225
-1275
-1325
-1375
-1425
-1475
-1525
-1575
-1625
-1675
-1725
-1775
-1825
-1875
-1925
-1975
-2025
-2075
-2125
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
SEGB53
SEGC53
SEGA54
SEGB54
SEGC54
SEGA55
SEGB55
SEGC55
SEGA56
SEGB56
SEGC56
SEGA57
SEGB57
SEGC57
SEGA58
SEGB58
SEGC58
SEGA59
SEGB59
SEGC59
SEGA60
SEGB60
SEGC60
SEGA61
925
875
825
775
725
675
625
575
525
475
425
- 6 -
NJU6821
ꢀPAD COORDINATES 4
Chip Size 19910µm x 2550µm (Chip Center 0µm x 0µm )
PAD
No.
PAD
No.
Terminal
X(µm)
Y(µm)
Terminal
X (µm)
Y (µm) PAD No. Terminal
X (µm)
Y (µm)
460 SEGB95
461 SEGC95
462 SEGA96
463 SEGB96
464 SEGC96
465 SEGA97
466 SEGB97
467 SEGC97
468 SEGA98
469 SEGB98
470 SEGC98
471 SEGA99
472 SEGB99
473 SEGC99
474 SEGA100
475 SEGB100
476 SEGC100
477 SEGA101
478 SEGB101
479 SEGC101
480 SEGA102
481 SEGB102
482 SEGC102
483 SEGA103
484 SEGB103
485 SEGC103
486 SEGA104
487 SEGB104 -6075 1068
488 SEGC104 -6125 1068
489 SEGA105 -6175 1068
490 SEGB105 -6225 1068
491 SEGC105 -6275 1068
492 SEGA106 -6325 1068
493 SEGB106 -6375 1068
494 SEGC106 -6425 1068
495 SEGA107 -6475 1068
496 SEGB107 -6525 1068
497 SEGC107 -6575 1068
498 SEGA108 -6625 1068
499 SEGB108 -6675 1068
500 SEGC108 -6725 1068
501 SEGA109 -6775 1068
502 SEGB109 -6825 1068
503 SEGC109 -6875 1068
-4725 1068
-4775 1068
-4825 1068
-4875 1068
-4925 1068
-4975 1068
-5025 1068
-5075 1068
-5125 1068
-5175 1068
-5225 1068
-5275 1068
-5325 1068
-5375 1068
-5425 1068
-5475 1068
-5525 1068
-5575 1068
-5625 1068
-5675 1068
-5725 1068
-5775 1068
-5825 1068
-5875 1068
-5925 1068
-5975 1068
-6025 1068
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
SEGB112
SEGC112
SEGA113
SEGB113
SEGC113
SEGA114
SEGB114
SEGC114
SEGA115
SEGB115
SEGC115
SEGA116
SEGB116
SEGC116
SEGA117
SEGB117
SEGC117
SEGA118
SEGB118
SEGC118
SEGA119
SEGB119
SEGC119
SEGA120
SEGB120
-7275
-7325
-7375
-7425
-7475
-7525
-7575
-7625
-7675
-7725
-7775
-7825
-7875
-7925
-7975
-8025
-8075
-8125
-8175
-8225
-8275
-8325
-8375
-8425
-8475
-8525
-8575
-8625
-8675
-8725
-8775
-8825
-8875
-8925
-8975
-9025
-9075
-9125
-9175
-9225
-9275
-9325
-9375
-9425
-9475
-9525
-9575
-9625
-9675
-9726
-9726
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
900
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
SEGSA2
SEGSB2
SEGSC2
SEGSA3
SEGSB3
SEGSC3
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
DMY7(L)
DMY7(R)
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
-9726
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-50
-100
-150
-200
-250
-300
-350
-400
-450
-500
-550
-600
-650
-700
-750
-800
-850
-900
536 SEGC120
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
SEGA121
SEGB121
SEGC121
SEGA122
SEGB122
SEGC122
SEGA123
SEGB123
SEGC123
SEGA124
SEGB124
SEGC124
SEGA125
SEGB125
SEGC125
SEGA126
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
DMY5(L)
DMY5(R)
DMY6(L)
DMY6(R)
504
505
SEGA110 -6925 1068
SEGB110 -6975 1068
506 SEGC110 -7025 1068
507
508
509
510
SEGA111 -7075 1068
SEGB111 -7125 1068
SEGC111 -7175 1068
SEGA112 -7225 1068
850
- 7 -
NJU6821
ꢀBLOCK DIAGRAM
VSSA
VDDA
VSSH
VSS
VDD
Segment Driver
Common Driver
Shift Register
5
V
LCD, V1 -V4
Gradation Circuit
Data Latch Circuit
C1+
C1-
C2+
C2-
C3+
C3-
Voltage
booster
C4+
C4-
C5+
C5-
C6+
C6-
Display Data RAM
(DD RAM)
128x80x(3+3+2)bit
Voltage
regulator
VOUT
VEE
VREF
VBA
VREG
Icon Data RAM
(PG RAM)
128x2x(3+3+2)bit
D15
Column Address Decoder
Column Address Counter
Column Address Register
D14
FR
D13
RAM
Interface
Display
timing
Generator
FLM
CL
D12
D11
D10
D9
CLK
D8
OSC2
OSC1
Oscillator
D7
D6
D5
D4/SPOL
D3/SMODE
D2/EXCS
D1/SDA
D0/SCL
Instruction
Decoder
Register Read
Control
Bus Holder
Pole Control
Internal Bus
MPU Interface
CSb RS
M/S
RDb WRb P/S
SEL68 RESb TEST
- 8 -
NJU6821
ꢀPOWER SUPPLY CIRCUITS BLOCK DIAGRAM
+
-
Reference
VBA
-
VLCD
Voltage Generator
-
V1
Voltage regulator
VREG
VREF
+
-
-
V2
Gain
Control
(1x-7x)
-
V3
E.V.R.
1/2VRE
-
V4
EVR register
Boost level register
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
VEE
Voltage
Booster
VOUT
- 9 -
NJU6821
ꢀTERMINAL DESCRIPTION 1
No.
Symbol
VDD
I/O
Power
Function
Power supply for logic circuits
21,22,23,
39,40,41
27,28,29,
58,59,60
67,68,69,
88,89,90
31
VSS
VSSH
VDDA
Power
Power
Power
GND for logic circuits
GND for high voltage circuits
This terminal is internally connected to the VDD level.
•This terminal is used to fix the selection terminals to the VDD
level.
Note) Do not use this terminal for a main power supply.
This terminal is internally connected to the VSS level.
•This terminal is used to fix the selection terminals to the VSS
level.
17,18,19,
34,35,36
VSSA
Power
Note) Do not use this terminal for a main GND.
70,71,115,116
72,73
VLCD
V1
Power/O LCD driving voltages
•When the internal voltage booster is not used, external LCD
74,75
76,77
78,79
V2
V3
V4
driving voltages (V1 to V4 and VLCD) must be supplied on these
terminals. And the external voltages must be maintained in the
following relation.
VSS<V4<V3<V2<V1<VLCD
• When the internal voltage booster is used, the LCD driving
voltages (V1 to V4 and VLCD) are enabled by the “Power control”
instruction in the master mode operation. The capacitors
between the VSS and these terminals are necessary.
Capacitor connection terminals for the voltage booster
91,92
93,94
95,96
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
VBA
O
O
Capacitor connection terminals for the voltage booster
Capacitor connection terminals or the voltage booster
Capacitor connection terminals for the voltage booster
Capacitor connection terminals for the voltage booster
Capacitor connection terminals for the voltage booster
Output of the reference-voltage generator
97,98
99,100
101,102
103,104
105,106
107,108
109,110
111,112
113,114
82,83
O
O
O
O
O
I
84
VREF
VEE
Input of the voltage regulator
85,86,87
117,118
80,81
24
Power
Input of the voltage booster
•This terminal is normally connected to the VDD level.
Power/O Output of the voltage booster
Input for high voltage circuits in using external power supply
Output of the voltage regulator
VOUT
VREG
O
I
Reset
Active “0”
RESb
- 10 -
NJU6821
ꢀTERMINAL DESCRIPTION 2
No.
42
Symbol
D0/SCL
I/O
I/O
Function
Parallel interface:
D7 to D0 : 8-bit bi-directional bus
•In the parallel interface mode (P/S=“1”), these terminals
connect to 8-bit bi-directional MPU bus.
43
44
D1/SDA
D2/EXCS
D3/SMODE
D4/SPOL
D5,D6,D7
I/O
I/O
I/O
I/O
I/O
Serial interface:
SDA : serial data
SCL : serial clock
EXCS : extension chip-selection
SMODE : 3-/4-line serial interface mode selection
SPOL : RS polarity selection
(in the 3-line serial interface mode)
45
46
•In the 3-/4-line serial interface mode (P/S=“0”), the D0 terminal
is assigned to the SCL and the D1 terminal to the SDA.
•In the 3-line serial interface mode, the D4 terminal is assigned
to the SPOL.
47,48,49
•Serial data on the SDA is fetched at the rising edge of the
SCL signal in the order of the D7, D6…D0, and the fetched data
is converted into 8-bit parallel data at the falling edge of the 8th
SCL signal.
•The SCL signal must be set to “0” after data transmissions or
during non-access.
50,51,52,53
54,55,56,57
D8,D9,D10,D11,
D12,D13,D14,D15
I/O
8-bit bi-directional bus
•In the 16-bit data bus mode, these terminals are assigned to
upper 8-bit data bus.
•In the serial interface mode or the 8-bit data bus mode of the
parallel interface, these terminals must be fixed to “1” or “0”.
Chip select
Active “0”
Resister select
25
26
I
I
CSb
RS
•This signal distinguishes transferred data as an instruction or
display data as follows.
RS
H
L
Distinct.
Instruction
Display data
38
37
I
I
80 series MPU interface (P/S=“1”, SEL68=“0”)
RDb signal. Active “0”.
RDb (E)
68 series MPU interface (P/S=“1”, SEL68=“1”)
Enable signal. Active “1”.
80 series MPU interface (P/S=“1”, SEL68=“0”)
WRb signal. Active “0”.
WRb (R/W)
68 series MPU interface (P/S=“1”, SEL68=“1”)
R/W signal.
R/W
H
L
Status
Read
Write
- 11 -
NJU6821
ꢀTERMINAL DESCRIPTION 3
No.
33
Symbol
SEL68
I/O
I
Function
MPU interface type selection
SEL68
H
L
Status
68 series
80 series
32
P/S
I
Parallel / serial interface mode selection
Chip
Select
P/S
Data/Instruction
Data
Read/Write
Serial clock
H
L
CSb
RS
RS
D0~D7
RDb, WRb
Write only
-
CSb
SDA (D1)
SCL (D0)
•Since the D15 to D5 terminals are in the high impedance in the serial
interface mode (P/S=“0”), they must be fixed to “1” or “0”. The RDb and
WRb terminals also must be “1” or “0”.
20
61
TEST
CL
I
Maker test terminal
This terminal should be fixed to “0”.
LCD line clock
I/O
•This signal is used to count up the line counter and latch the display
data into the data latch circuit.
•At the rising edge of the CL signal, the line counter is counted-up and
the 384-bit display data, corresponding to the counted-up line address,
is latched into the data latch circuit. At the falling edge of the CL signal,
the latched data output onto the segment drivers.
M/S
H
L
Status
Master
Slave
CL
Output
Input
62
FLM
I/O
LCD frame maker signal
•This signal is used to indicate the start of a new display frame. It
presets an initial display line address into the line counter when the
FLM signal becomes “1”.
M/S
H
L
Status
Master
Slave
FLM
Output
Input
63
FR
I/O
LCD alternate signal
•This signal is toggled to alternate the crystal polarization of a LCD
panel. It can be programmed so that the FR signal will toggle at every
frame or once every N frames in the N-line inversion mode.
M/S
H
L
Status
Master
Slave
FR
Output
Input
30
M/S
I
Master / slave select
M/S
H
L
Status
Master
Slave
Oscillator
Enable
Disable
Power supply
Enable
Disable
- 12 -
NJU6821
ꢀTERMINAL DESCRIPTION 4
No.
Symbol
SEGA0-SEGA127
SEGB0-SEGB127
I/O
O
Function
,
,
Segment output
REV Mode
174−557
SEGC0-SEGC127
Turn-off
Turn-on
Normal
Reverse
0
1
1
0
•These terminals output LCD driving waveforms in accordance
with the combination of the FR signal and display data.
In the B/W mode
FR signal
Display data
Normal display mode
V2
VLCD
V2
V3
VSS
V3
Reverse display
mode
VLCD
VSS
SEGSA0-SEGSA3,
SEGSB0-SEGSB3,
SEGSC0-SEGSC3
O
O
Icon-segment output
164−169,
562−567
•These terminals are assigned at both edge of normal segment
output terminals line for out line frame display.
Common output
•These terminals output LCD driving waveforms in accordance
with the combination of the FR signal and scanning data.
COM0-COM79
162−137,
132−119,
568−594,
3−15
Data
H
L
H
L
FR
H
H
L
Output level
VSS
V1
VLCD
V4
L
163
16
65,
66
COMI0
COMI1
OSC1
OSC2
O
O
I
Icon common output
Icon common output
OSC
O
•When the internal oscillator clock is used in the master mode or
when the LSI is used in the slave mode, these terminals must be
opened. In these cases, the OSC1 outputs the VSS level.
•When an external oscillator is used, external clock is input to the
OSC1 terminal or an external resistor is connected between the
OSC1 and OSC2 terminals.
64
CLK
I/O
Display timing synchronous clock
•This signal is used to synchronize the display timing between the
master and slave LSIs.
M/S
H
L
Mode
Master
Slave
CLK
Output
Input
(Terminal No. 1,2,133,134,135,136,170,171,172,173,558,559,560,561,595, and 596 are dummy.)
- 13 -
NJU6821
ꢀ FUNCTIONAL DESCRIPTION
(1) MPU Interface
(1-1) Selection of parallel / serial interface mode
The P/S terminal is used to select parallel or serial interface mode as shown in the following table. In the
serial interface mode, it is not possible to read out display data from the DDRAM, and status from the
internal registers.
Table
WRb
WRb
-
P/S
P/S mode
Parallel I/F
Serial I/F
CSb
CSb
CSb
RS
RS
RS
RDb
RDb
-
SEL68
SEL68
-
SDA
SDA
SCL
SCL
Data
D7-D0
(D15-D0)
H
L
-
Note 1) “ -” : Fix to “1” or “0”.
(1-2) Selection of MPU interface type
In the parallel interface mode, the SEL68 terminal is used to select 80- or 68-series MPU interface type, as
shown in the following table.
Table
WRb
R/W
SEL68
MPU type
CSb
CSb
CSb
RS
RS
RS
RDb
E
Data
H
L
68 series MPU
80 series MPU
D7-D0 (D15-D0)
D7-D0 (D15-D0)
WRb
RDb
(1-3) Data distinction
In the parallel interface mode, the combination of RS, RDb, and WRb (R/W) signals distinguishes
transferred data between the LSI and MPU as instruction or display data, as shown in the following table.
Table
68 series
80 series
Function
RS
RDb
WRb
R/W
H
Read out instruction data
Write instruction data
Read out display data
Write display data
H
H
L
L
H
L
H
L
L
H
H
L
L
L
H
(1-4) Selection of serial interface mode
In the serial interface mode, the SMODE terminal is used to select the 3- or 4-line serial interface mode as
shown in the following table.
Table
SMODE
Serial interface mode
H
L
3-line
4-line
- 14 -
NJU6821
(1-5) 4-line serial interface mode
In the serial interface mode, when the chip select is active (CSb=“0”), the SDA and the SCL are enabled.
When the chip select is not active (CSb=“1”), the SDA and the SCL are disabled, and the internal shift
register and the counter are being initialized. The 8-bit serial data on the SDA is fetched at the rising edge
of the SCL signal in order of the D7, D6…D0, and the fetched data is converted into the 8-bit parallel data at
the rising edge of the 8th SCL signal.
In the 4-line serial interface mode, the transferred data on the SDA is distinguished as display data or
instruction data in accordance with the condition of the RS signal.
Table
RS
H
Data distinction
Instruction data
Display data
L
Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after data
transmissions or during non-access. To release a mal-function caused by the external noises, the chip-
selected status should be released (CSb=“1”) after each of the 8-bit data transmissions. The following
figure illustrates the interface timing for the 4-line serial interface operation.
CSb
RS
VALID
D0
SDA
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
SCL
8
4-line serial interface timing
(1-6) 3-line serial interface mode
In the serial interface mode, when the chip select is active (CSb=“0”), the SDA and SCL are enabled.
When the chip select is not active (CSb=“1”), the SDA and SCL are disabled and the internal shift register
and counter are being initialized. 9-bit serial data on the SDA is fetched at the rising edge of the SCL
signal in order of the RS, D7, D6…D0, and the fetched data is converted into the 9-bit parallel data at the
falling edge of the 9th SCL signal.
In the 3-line serial interface mode, data on the SDA is distinguished as display data or instruction data in
accordance with the condition of the RS bit of SDA data and the status of the SPOL, as follows.
Table
SPOL=L
Data distinction
SPOL=H
Data distinction
RS
L
RS
L
Display data
Instruction data
Display data
H
Instruction data
H
- 15 -
NJU6821
Since the serial interface operation is sensitive to external noises, the SCL must be set to “0” after data
transmissions or during non-access. To release a malfunction caused by the external noises, the chip-
selected status should be released (CSb=“1”) after each of 9-bit data transmissions. The following figure
illustrates the interface timing of the 3-line serial interface operation.
CSb
SDA
SCL
RS
1
D7
2
D6
D5
4
D4
5
D3
D2
D1
D0
3
6
7
8
9
3-line serial interface timing
(1-7) Unification of the CSb signals (in the serial interface mode)
When two of the NJU6821 is used as a master and slave driver in the 3- or 4-line serial interface mode,
both of the CSb signals can be notified using the EXCS terminals in order to simplify the control signals. In
this time, the master’s EXCS is assigned to output and slave’s EXCS is assigned to input. The status of
the EXCS signal is controlled by the “EXCS control” instruction.
of the master LSI.
During both of the EXCS and CSb are “0”, the slave LSI is enabled to accept instructions from MPU but
the master LSI is disabled to accept any instruction except the “EXCS control” instruction. During the
EXCS is “1” and CSb is “0”, the master LSI is enabled and the slave LSI is disabled.
RS SCL SDA CSb
EXCS: Extension CSb
CSb
EXCS=0, CSb=0: Slave LSI is enabled
SDA
EXCS=1,CSb=0: Master LSI is enabled
SCL
RS
P/S: Parallel/serial interface mode select
(MASTER)
M/S
P/S=0: Serial interface
P/S=1: Parallel interface
P/S
SMODE
SPOL
EXCS
M/S: Master/slave select
M/S=0: Slave operation
M/S=1: Master operation
CSb
SDA
SCL
SMODE: 3-/4-line serial interface mode select
RS
SMODE=0: 4-line serial interface
SMODE=1: 3-line serial interface
(SLAVE)
M/S
P/S
SMODE
SPOL
EXCS
SPOL: RS polarity select
SPOL=0, RS=0: Display data
SPOL=0, RS=1: Instruction data
SPOL=1, RS=0: Instruction data
SPOL=1, RS=1: Display data
4-line serial interface
(In the 3-line serial interface mode)
- 16 -
NJU6821
(2) Access to the DDRAM
When the CSb signal is ”0”, the transferred data from MPU is written into the DDRAM or instruction register in
accordance with the condition of the RS signal.
When the RS signal is “1”, the transferred data is distinguished as display data. After the “column address” and
“row address” instructions are executed, the display data can be written into the DDRAM by the “display data
write” instruction. The display data is written at the rising edge of the WRb signal in the 80 series MPU mode, or
at the falling edge of the E signal in the 68 series MPU mode.
Table
RS
H
Data distinction
Display RAM Data
L
Internal Command Register
In the sequence of the “display data read” operation, the transferred data from MPU is temporarily held in the
internal bus-holder and then transferred to the internal data-bus. When the “display data read” operation is
executed just after the “column address” and “row address” instructions or “display data write” instruction,
unexpected data on the bus-holder is read out at the 1st execution, then the data of designated DDRAM
address is read out from the 2nd execution. For this reason, a dummy read cycle must be executed to avoid
the unexpected 1st data read.
ꢁ Display data write operation
n
n+1
n+2
n+3
n+4
D0 to D15
WRb
n
n+1
n+2
n+3
n+4
Bus Holder
WRb
ꢁ Display data read operation
WRb
D0 to D7(D0 to D15)
n
n
n+1
Data Read
n+1 Address n+2 Address
n+2
Address Set
n
Dummy
Read
Data Read
n Address
Data Read
RDb
Note) In the 16-bit data bus mode, instruction data must be 16-bit as well as the display data.
- 17 -
NJU6821
(3) Access to the instruction register
Each of the instruction resisters is assigned to each address between 0H and FH and content of the instruction
register can be read out by the combination of the “Instruction resister address” and ”Instruction resister read”.
WRb
M
m
N
n
D0~D7
Instruction resister
address set
Instruction resister Instruction resister Instruction resister
read address set read
RDb
(4) 8-/16-bit data bus length for display data (in the parallel interface mode)
The 8- or 16-bit data bus length for display data is determined by the “WLS” of the “Data bus length” instruction.
In the 16-bit data bus mode, instruction data must be 16-bit (D15 to D0) as well as display data. However, for the
access to the instruction register, the only lower 8-bit data (D7 to D0) of the 16-bit data is valid. For the access
to the DDRAM, all of the 16-bit data (D15 to D0) is valid.
Table
WLS
L
Data bus length mode
8-bit
H
16-bit
(5) Initial display line register
The initial display line resister specifies the line address, corresponding to the initial COM line, by the “Initial
display line” instruction. The initial COM line signifies the common driver, starting scanning the display data in
the DDRAM, and specified by the “Initial COM line” instruction.
The line address, established in the initial display line resister, is preset into the line counter whenever the FLM
signal becomes “1”. At the rising edge of the CL signal, the line counter is counted-up and addressed 384-bit
display data, corresponding to the counted-up line address, is latched into the data latch circuit. At the falling
edge of the CL signal, the latched data outputs to the segment drivers.
- 18 -
NJU6821
(6) DDRAM mapping
The DDRAM is capable of 1,024-bit (8-bit x 128-segment) for the column address and 82-bit for the row
address.
In the gradation mode, each pixel for RGB corresponds to the successive 3-segment drivers that consist of 2-
segment drivers for 8-gradation and 1-segment driver for 4-gradation, so that the LSI can drive a 256-color
display (8-gradation x 8-gradation x 4-gradation) with up to 128x82 pixels. The 8-gradation level is controlled by
3-bit display data in the DDRAM and 4-gradation level is controlled by 2-bit display data in the DDRAM
respectively.
In the B&W mode, only MSB data from each 3-bit and 2-bit RGB display data group in the DDRAM is used.
Therefore, 384 x 82 pixels in the B&W display is also available.
The range of the column address varies depending on data bus length. The range between 00H and 70F is
used in the 8-bit data bus length and the range between 00H and 3FH is in the 16-bit data bus length.
ꢁ In the 8-bit data bus length mode
column-address
0H
8bit
1H
8bit
7EH
8bit
7FH
8bit
0 H
row-
address
51H
8bit
8bit
8bit
8bit
ꢁ In the 16-bit data bus length mode
column-address
0H
3FH
0 H
16bit
16bit
row-
address
51H
16bit
16bit
The DDRAM is accessing 8-bit or 16-bit unit addressed by column and row address. In the 16-bit data bus
length mode, over 40H address setting is prohibited.
The increment for the column address and row address are set to the auto-increment mode by programming
“AXI” and “AYI” registers of the “Increment control” instruction. In this mode, the contents of the column
address and row address counters automatically increment whenever the DDRAM is accessed.
The column address and row address counters, independent of the line counter. They are used to designate
the column address and row address for the display data transferred from MPU. On the other hand, the line
counter is used to generate the line address, and output display data to the segment drivers, being
synchronized with the display control timing of the FLM and CL signals.
- 19 -
NJU6821
(7) Window addressing mode
In addition to the above usual DDRAM addressing, it is possible to access some part of DDRAM in using the
window addressing mode, in which the start and end points are designated. The start point is determined by the
“column address” and “row address” instructions, and the end point is determined by the “Window end column
address “and ”Window end row address” instructions. The setting example of the window addressing is listed,
as follows.
1. Set WIN=1, AXI=1, and AYI=1 by the “Increment control” instruction
2. Set the start point by the “column address” and “row address” instructions
3. Set the end point by the “Window end column address” and “Window end row address” instructions
4. Enable to access to the DDRAM in the window addressing mode
In the window addressing mode (WIN=1, AXI=1, AYI=1), the read-modify-write operation is available by setting
“0” to the “AIM” register of the “Increment control” instruction.
And in the window addressing mode, the following start and end point must be maintained to abide a
malfunction.
AX (column address of start point) < EX (column address of end point) < Maximum of column address
AY (row address of start point) < EY (row address of end point) < Maximum of row address
column address
(X, Y)
Start point
End point
Window display area
(X, Y)
Whole DDRAM area
(8) Reverse display ON/OFF
The “Reverse display ON/OFF” function is used to reverse the display data without changing the contents of
the DDRAM.
Table
REV
0
Display
Normal
DDRAM data → Display data
0
1
0
1
0
1
1
0
1
Reverse
(9) Segment direction
The “Segment direction” function is used to reverse the assignment for the segment drivers and column
address, and it is possible to reduce the restrictions for the placement of the LSI on the LCD modules.
- 20 -
NJU6821
(10)The relationship among the DDRAM column address, display data and segment drivers
In the color mode, and 16-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=3FH
X=3FH
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=3FH
X=3FH
X=00H
In the color mode, and 8-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=7FH
X=01H
X=7EH
X=7EH
X=01H
X=7FH
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=7FH
X=01H
X=7EH
X=7EH
X=01H
X=7FH
X=00H
- 21 -
NJU6821
In the B&W mode, and 16-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=3FH
X=3FH
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=3FH
X=3FH
X=00H
In the B&W mode, and 8-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=7FH
X=01H
X=7EH
X=7EH
X=01H
X=7FH
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=7FH
X=01H
X=7EH
X=7EH
X=01H
X=7FH
X=00H
- 22 -
NJU6821
ꢀ Bit assignments bitween write and read data (in the 16-bit data bus mode)
REF=0, SWAP=0
Write data
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
D12 D13 D14
D15
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10SEG11SEG12SEG13SEG14 SEG15
D0
D1
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10 D11
D10 D11
D12 D13 D14
D12 D13 D14
D15
D15
REF=0, SWAP=1
Write data
D0
D1
D2
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10SEG11SEG12SEG13SEG14 SEG15
D0
D1
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10 D11
D10 D11
D12 D13 D14
D12 D13 D14
D15
D15
REF=1, SWAP=0
Write data
D0
D1
D2
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10SEG11SEG12SEG13SEG14 SEG15
D0
D1
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10 D11
D10 D11
D12 D13 D14
D12 D13 D14
D15
D15
REF=1, SWAP=1
Write data
D0
D1
D2
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10SEG11SEG12SEG13SEG14 SEG15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
D12 D13 D14
D15
- 23 -
NJU6821
ꢀ Examples for write and read data (in the 16-bit data bus mode)
REF=0, SWAP=0
D15
D0
0
Write data
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
(E4F2H)
D1
5
1
D0
0
Read data
Write data
Read data
Write data
Read data
Write data
Read data
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
(E4F2H)
(E4F2H)
(4F27H)
(E4F2H)
(E4F2H)
(E4F2H)
(4F27H)
REF=0, SWAP=1
D15
D0
0
1
1
1
D15
0
D0
1
1
0
REF=1, SWAP=0
D15
D0
0
1
1
1
D15
1
D0
0
1
1
REF=1, SWAP=1
D15
D0
0
1
1
1
D15
0
D0
1
1
0
- 24 -
NJU6821
ꢀ Bit assignments between write and read data (in the 8-bit data bus mode)
REF=0, SWAP=0
Write data
D0
D1
D2
D3
D4
D5
D6
D7
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
REF=0, SWAP=1
Write data
D0
D1
D2
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
REF=1, SWAP=0
Write data
D0
D1
D2
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
REF=1, SWAP=1
Write data
D0
D1
D2
Segment data
Read data
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D4
D5
D6
D7
- 25 -
NJU6821
ꢀ Examples for write and read data (in the 8-bit data bus mode)
REF=0, SWAP=0
D15
1
D0
0
Write data
Read data
Write data
Read data
Write data
Read data
Write data
Read data
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
(E4H)
(E4H)
(E4H)
(27H)
(E4H)
(E4H)
(E4H)
(27H)
D15
1
D0
0
1
1
REF=0, SWAP=1
D15
D0
0
1
1
1
D15
0
D0
1
0
1
REF=1, SWAP=0
D15
D0
0
1
1
1
D15
1
D0
0
1
1
REF=1, SWAP=1
D15
D0
0
1
1
1
D15
0
D0
1
0
1
- 26 -
NJU6821
ꢀ The relationship among the PGRAM column address, display data and segment drivers
In the color mode, and 16-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=01H
X=01H
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=01H
X=01H
X=00H
In the color mode, and 8-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
- 27 -
NJU6821
In the B&W mode, and 16-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=01H
X=01H
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=01H
X=01H
X=00H
In the B&W mode, and 8-bit data bus mode
REF SWAP
column address / bit / segment assign
0
1
0
1
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
REF SWAP
column address / bit / segment assign
0
1
1
0
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
- 28 -
NJU6821
(11) Gradation palette
In the gradation mode, each of the gradation palettes Aj can select 8-gradation levels out of a palette consisting
of 32-gradation levels by setting 5-bit palette value into the “PA” registers in the “Gradation palette Aj”
instructions (j=0 to 7). Each of the gradation palettes Bj and Cj can select 8-gradation levels as well as the
gradation palette Aj.
The gradation palettes Aj correspond to the SEGAi, the Bj to SEGBj and the Cj to SEGCi (j=0 to 7, i=0 to 127).
The display data (0,0,0) corresponds to the gradation palettes Z0, the data (0,0,1) to the Z1, the data (0,1,0) to
the Z2…the data (1,1,1) to the Z7 (Z=A, B and C).
(12) Gradation LSB (GLSB)
In the graduation mode, each pixel for RGB corresponds to the successive 3-segment drivers that consist of 2-
segment drivers for 8-graduation and 1-segment driver for 4-gradietion. The 8-gradation segment drivers can
generate 8-gradation levels controlled by 3-bit display data in the DDRAM. The 4-gradation segment drivers
can generate 4-gradation levels by 2-bit in the DDRAM and 1-bit in the GLSB.
All of the selected 8-gradation palettes Zj (Z=A, B and C, j=0 to 7) are available for the 8-gradation segment
drivers. However, the only 4-gradation palettes Zj (Z=A, B and C, j= either 0,2,4,6 or 1,3,5,7) are available for
the 4-gradation segment drivers, because the GLSB is fixed to either “0” or “1” by setting the “GLSB” register in
the “Gradation control” instruction and adopted to all of the 4-gradation segment derivers.
GLSB=0:
The LSB of display data is always set to “0”.
Display data: (0,0,0), (0,1,0), (1,0,0), (1,1,0) → Gradation palettes: Z0, Z2, Z4, Z6
(Z=A, B and C)
GLSB=1:
The LSB of display data is always set to “1”.
Display data: (0,0,1), (0,1,1), (1,0,1), (1,1,1) → Gradation palettes: Z1, Z3, Z5, Z7
(Z=A, B and C)
(13) Variable or fixed gradation mode
In the gradation mode, either variable or fixed gradation mode is selected by programming the “PWM” register
of the “Gradation control” instruction.
PWM=0:
PWM=1:
Variable gradation mode
(Select 8 gradation levels out of 32-gradation level of the gradation palette)
Fixed gradation mode
(Fixed 8-gradation levels)
- 29 -
NJU6821
ꢀ Correspondence between display data and gradation palettes (MON=”0”; Gradation mode)
(Z=A, B and C, j=0 to 7)
(MSB) Display data (LSB)
Gradation palette Zj
Palette Z0
Default palette value
0 0 1 0 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Palette Z1
Palette Z2
Palette Z3
Palette Z4
Palette Z5
Palette Z6
Palette Z7
0 0 1 0 1
0 1 0 1 0
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0
1 1 1 1 1
ꢀ Gradation palette table (Variable gradation mode, PWM=”0”, MON=”0”)
(Z=A, B and C, j=0 to 7)
Palette value
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
Gradation level
0
Gradation palette Zj
Palette Z0 (default)
Palette value
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
Gradation level
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
Gradation palette Zj
Palette Z4 (default)
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
Palette Z1 (default)
Palette Z5 (default)
Palette Z6 (default)
Palette Z7 (default)
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Palette Z2 (default)
Palette Z3 (default)
ꢀ Gradation palette table (Fixed gradation mode, PWM=”1”, MON=”0”)
8-gradation segment drivers
Display data
4-gradation segment drivers
Display data
Gradation level
Gradation level
0
(MSB) DDRAM (LSB)
DDRAM
GLSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/7
2/7
3/7
4/7
5/7
6/7
7/7
2/7
3/7
4/7
5/7
7/7
ꢀ Correspondence between display data and gradation level (B&W mode, MON=”1”)
8-gradation segment drivers
Display data
4-gradation segment drivers
Display data
Gradation level
Gradation level
(MSB) DDRAM (LSB)
DDRAM
GLSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
*
*
*
*
0
0
1
1
*: Don’t care
- 30 -
NJU6821
(14)Gradation control and display data
(14-1) Gradation mode
In the graduation mode, each pixel for RGB corresponds to the successive 3 segment drivers that consist
of 2 segment drivers for 8-graduation and 1 segment driver for 4-gradietion, so that NJU6821 can drive a
256-color display (8-gradation x 8-gradation x 4-gradition) with up to 128x82 pixels. The 8-gradation
segment drivers can generate 8-gradation levels controlled by using 3-bit of display data in the DDRAM.
The 4-gradation segment drivers can generate 4-gradation levels by using 2-bit in the DDRAM and 1-bit in
the GLSB.
In addition, the LSI can transfer 8-bit display data for 1-pixel the RGB or 16-bit for 2-pixels RGB to the
DDRAM at one-time access. The data assignment between gradation palettes and segment drivers varies
in accordance with the setting for the “SWAP” and “REF” registers of the "Display control (2)" instruction.
ꢀ (REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
(j=0 to 7)
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
0
0
0
1
0
0
1
1
1
Display data in DDRAM
GLSB
MSB
LSB
MSB
LSB
MSB
Display data from MPU
column address: nH
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
Note) DDRAM column address
: 7H → 7FH (REF=”0”)
:7FH → nH (REF=”1”)
ꢀ (REF, SWAP)=(0, 1) or (1, 0)
(i=0 to 127)
SEGAi
SEGBi
SEGCi
Gradation palette
(j=0 to 7)
Palette Cj
Palette Bj
Palette Aj
Gradation control circuit
Display data in DDRAM
0
1
1
1
0
0
1
0
0
GLSB
MSB
LSB
MSB
LSB
MSB
Display data from MPU
column address: nH
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
Note) DDRAM column address
: nH (REF=”0”)
: 7FH → nH (REF=”1”)
- 31 -
NJU6821
In the 16-bit data bus mode, the data assignments between the gradation palettes and the segment
drivers vary in accordance with setting for the “SWAP” and “REF” bit of the "Display control (2)" instruction
as well as the assignment in the 8-bit data bus mode.
ꢀ (REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
SEGAi+1
SEGBi+1
SEGCi+1
(i=0 to 126)
Gradation palette
(j=0 to 7)
Palette Aj
Palette Bj
Palette Cj
Palette Aj
Palette Bj
Palette Cj
Gradation
control circuit
0
Display data in DDRAM
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
GLSB
MSB LSB
MSBLSB
MSB
MSB LSB
MSBLSB
MSB
Display data from MPU
column address: nH
0
1
0
0
1
1
0
1
0
1
1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Note) DDRAM column address
: nH (REF=”0”)
: 3FH → nH (REF=”1”)
ꢀ (REF, SWAP)=(0, 0) or (1, 1)
(i=0 to 126)
SEGAi
SEGBi
SEGCi
SEGAi+1
SEGBi+1
SEGCi+1
Palette Cj
Palette Bj
Palette Aj
Palette Cj
Palette Bj
Palette Aj
Gradation palette
(j=0 to 7)
Gradation
control circuit
0
Display data in DDRAM
1
1
0
1
0
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
GLSB
MSB
LSB MSB
LSB MSB
MSB
LSB MSB
LSB MSB
Display data from MPU
column address: nH
0
1
0
0
1
1
1
0
1
0
1
1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Note) DDRAM column address
:nH (REF=”0”)
:3FH → nH (REF=”1”)
- 32 -
NJU6821
(14-2) B&W mode (MON=”1”)
In the B&W mode and 8-bit data bus mode, only 3 of MSB of each display data is used for the display. In
the 16-bit data bus mode, 6 of MSB of each display data are used.
In the 8-bit data bus mode (Similarly 16-bit data bus access)
ꢀ (REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
(j=0 to 7)
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
0
0
1
0
0
1
1
1
GLSB
MSB LSB
MSB LSB
MSB
Display data from MPU
column address: nH
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
Note) DDRAM column address
: nH (REF=”0”)
: 7FH → nH (REF=”1”)
ꢀ (REF, SWAP)=(0, 1) or (1, 0)
(i=0 to 127)
SEGAi
SEGBi
SEGCi
Gradation palette
(j=0 to 7)
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
1
1
1
0
0
1
0
0
GLSB
MSB
LSB MSB
LSB MSB
Display data from MPU
column address: nH
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
Note) DDRAM column address
: nH (REF=”0”)
: 7FH → nH (REF=”1”)
- 33 -
NJU6821
(15) Display timing generator
The display-timing generator creates the timing pulses such as the CL, the FLM, the FR and the CLK by
dividing the oscillation frequency oscillate an external or internal resister mode. The timming pulse terminals
and timing generator status is setting by the Master/Slave (M/S) terminal as described in the following table.
The statuses of timing pulse terminal and generator
M/S
L
Mode
Slave
CL
Input
FR
Input
FLM
Input
CLK
Input
H
Master
Output
Output
Output
Output
(16) LCD line clock (CL)
The LCD line clock (CL) is used as a count-up signal for the line counter and a latch signal for the data latch
circuit. At the rising edge of the CL signal, the line counter is counted-up and the 384-bit display data,
corresponding to this line address, is latched into the data latch circuit. And at the falling edge of the CL signal,
this latched data output on the segment drivers. Read out timing of the display data, from DDRAM to the latch
circuits, is completely independent of the accsess timing to the MPU. For this reason, the MPU can access to
the LSI regardless of an internal operation.
(17) LCD alternate signal (FR) and LCD synchronous signal (FLM)
The FR and FLM signals are created from the CL signal. The FR signal is used to alternate the crystal
polarization on a LCD panel. It is programmed that the FR signal is toggle on every frame in the default setting
or once every N lines in the N-line inversion mode. The FLM signal is used to indicate a start line of a new
display frame. It presets an initial display line address of the line counter when the FLM signal becomes ”1”.
When two of NJU6821 is using as a Master and Slave, the CL, the FLM, the FR, and the CLK signals should
be supplied from Master NJU6821 to Slave NJU6821.
(18) Data latch circuit
The data latch circuit is used temporarily store the display data that will output to the segment drivers. The
display data in this circuit is updated in synchronization of the CL signal.
The “All pixels ON/OFF”, “Display ON/OFF” and “Reverse display ON/OFF” instructions change the display
data in this circuit but do not change the display data of the DDRAM.
- 34 -
NJU6821
ꢀ LCD Driving waveforms (In the B&W mode, Reverse display OFF, 1/82 duty)
COM0
82 1
2
3
4
5
82 1
2
3
4
5
82 1
COM1
CL
FLM
FR
VLCD
V1
V2
V3
COM0
V4
VSS
VLCD
V1
V2
V3
V4
VSS
COM1
SEG0
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
SEG1
V3
V4
VSS
- 35 -
NJU6821
(19) Common and segment drivers
The LSI includes 384-segment drivers and 82-commom drivers for a graphic display. 2 out of 82-common
drivers are assigned to the COMI0 and COMI1 for an icon display. The common drivers generate the LCD
driving waveforms composed of the VLCD, V1, V4 and VSS in accordance with the FR signal and scanning data.
The segment drivers generate the waveforms composed of the VLCD, V2, V3 and VSS in accordance with the FR
signal and display data.
(20) Icon segment drivers
The 12-icon-segment drivers: SEGSAk, SEGSBk and SEGSCk (k=0 to 3) are mainly used for an outer-frame
display. 6-icon-segment drivers each are positioned in both sides of the segment drivers’ block. The icon
segment drivers are controlled by the display data entered in the icon segment registers instead of the DDRAM.
The dummy segment drivers SEGAk correspond to the gradation palette Aj, the SEGSBk to the palette Bj and
the SEGSCk to the palette Cj (k=0 to 3, j=0 to 7). The icon segment registers are capable of 4-byte display data,
in which each byte is corresponding to 1-set of the icon segment drivers such as the SEGSA0, SEGSB0 and
SEGSC0.
The icon segment registers are enabled by setting “1” into the “DMY” register in the “Icon segment register
ON/OFF” instruction and then the “column address” instruction, where the column address such as 00H, 01H,
02H and 03H are available in the 8-bit data bus mode and the column address such as 00H and 01H in the 16-
bit mode. The icon segment drivers are independent of the “row address set” instruction.
ꢀ 8-bit data bus mode (DMY=”1”)
column address
00H:
01H:
02H:
03H:
SEGSA0, SEGSB0, SEGSC0
SEGSA1, SEGSB1, SEGSC1
SEGSA2, SEGSB2, SEGSC2
SEGSA3, SEGSB3, SEGSC3
ꢀ 16-bit data bus mode (DMY=”1”)
column address
00H:
01H:
SEGSA0, SEGSB0, SEGSC0, SEGSA1, SEGSB1, SEGSC1
SEGSA2, SEGSB2, SEGSC2, SEGSA3, SEGSB3, SEGSC3
The icon segment drivers can support the “ALLON” and “REV” registers in the “Display control (1), (2)”
instructions but they cannot support the “LREV” and “BT” registers in the “Line inverse control” instruction. As
well as the read sequence for the DDRAM, the sequence for the segment registers also requires the dummy
read.
68 series
R/W
80 series
RS
DMY
Function
Read data from DDRAM
Write data into DDRAM
Read data from icon segment register
Write data into icon segment register
RD
WR
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
0
- 36 -
NJU6821
ꢀ Examples for the icon segment registers (DMY=”1”)
(In the 8-bit data bus mode, gradation mode, (REF, SWAP)=(0,0))
column address: 00H
SEGSA0
SEGSB0
SEGSC0
Gradation palette
(j=0 to 7)
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Icon segment register
0
0
0
1
0
0
1
1
1
GLSB
MSB LSB
MSB LSB
MSB
Display data from MPU
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
column address: 03H
SEGSA3
SEGSB3
SEGSC3
Gradation palette
(j=0 to 7)
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Icon segment register
0
GLSB
0
0
1
0
0
1
1
1
MSB LSB
MSB LSB
MSB
Display data from MPU
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
- 37 -
NJU6821
(21)Oscillator
The oscillator generates the internal clocks for the display timing and the voltage booster. It is enabled only in
the master mode operation by setting the “M/S” terminal to “1”. The C and R for the oscillator are on chipped,
therefore, there is no C, R required as an external components. Use an external R instead of internal R is also
available(CKS=1), in this time connect the resister between OSC1 and OSC2 terminals. However, when the
internal oscillator is not used, an external clock inputs to the OSC1 terminal.
In addition, the feed back resister for the oscillator is varied by programming the “Rf” register in the “Frequency
control” instruction, so that it is possible to optimize the frame frequency for a LCD panel. Setting examples of
the MON(B&W /Gradation) and the PWM(Variable gradation /Fixed gradation) are described, as follows.
Internal oscillation mode (CKS=0)
Symbol
FFL MON PWL
Display mode
f1
f2
f3
f4
f5
f6
1
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
*
Variable gradation mode
Fixed gradation mode
B&W mode
*
*: Don’t care
•
•
External resistor oscillation mode (CKS=1)
The internal clocks must be adjusted to the same frequency as the one in using the internal oscillation
mode, and the “FFL”, “MON” and “PWM” register must be set as well.
External clock input mode (CKS=1)
The external clocks must be adjusted to the same frequency as the one in using the internal oscillation
mode, and the “FFL”, “MON” and “PWM” register must be set as well.
(22)Power supply circuits
The internal power supply circuits are composed of the voltage booster, the electrical variable resister (EVR),
voltage regulator, reference voltage generator and the voltage followers.
The condition of the power supply circuits is arranged by programming the “DCON” and “AMPON” registers on
the “Power control” instruction. For this arrangement, some parts of the internal power supply circuits are
activated in using an external power supply, as shown in the following table.
Voltage followers
DCON
AMPON
Voltage booster
Voltage regulator
EVR
External voltage
Note
0
0
1
0
1
1
Disable
Disable
Enable
Disable
Enable
Enable
VOUT, VLCD, V1, V2, V3, V4
1, 3
2, 3
−
VOUT
−
Note1) The internal power circuits are not used. The external VOUT is required and C1+, C1-, C2+, C2-, C3+, C3-, C4+,
C4-, C5+, C5-, C6+, C6-, VREF, VREG and VEE terminals must be open.
Note2) The internal power circuits except the voltage booster are used. The external VOUT is required and the C1+,
C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+ and C6- terminals must be open. The reference voltage is
required to VREF terminal.
Note3) The relation among the voltages should be maintained as follows.
VOUT ≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
- 38 -
NJU6821
(23)Voltage booster
The voltage booster generates maximum 7x voltage of the VEE level. It is programmed so that the boost level is
selected out of 1x, 2x, 3x, 4x, 5x, 6x and 7x by the “Boost level select” instruction. The boosted voltage VOUT
must not exceed beyond the value of 18.0V, otherwise the voltage stress may cause a permanent damage to
the LSI.
ꢀ Boosted voltages
VOUT=17.5V
VOUT=9V
VEE=2.5V
VSS=0V
VEE=3V
VSS=0V
7-time boost
5-time boost
3-time boost
ꢀ Capacitor connections for the voltage Booster
7-time boost
6-time boost
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
VOUT
VOUT
VOUT
+
+
+
4-time boost
3-time boost
2-time boost
C1+
C1-
C2+
C2-
C3+
C3-
C1+
C1-
C2+
C2-
C3+
C3-
C1+
C1-
C2+
C2-
C3+
C3-
+
+
+
+
+
C4+
C4-
C4+
C4-
C4+
C4-
C5+
C5-
C5+
C5-
C5+
C5-
C6+
C6-
C6+
C6-
C6+
C6-
VOUT
VOUT
VOUT
+
+
+
- 39 -
NJU6821
(24)Reference voltage generator
The reference voltage generator is used to produce the reference voltage (VBA), which is output from the VBA
terminal and should be input to the VREF terminal.
VBA = VEE x 0.9
(25)Voltage regulator
The voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to gain the
reference voltage (VREF) and to create the regulated voltage (VREG). The VREG is used as an input voltage to the
EVR circuits, which is programming by the “VU” register of the “Boost level” instruction.
VREG = VREF x N
(N: register value for the boost level)
(26)Electrical variable resister (EVR)
The EVR is variable within 128-step, and is used to fine-tune the LCD driving voltage (VLCD) by programming
the “DV” register in the “EVR control” instruction, so that it is possible to optimize the contrast level of LCD
panels.
VLCD = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127
(M: register value for the EVR)
(27)LCD driving voltage generation circuit
LCD driving voltage generation circuit generates the VLCD voltage levels as VLCD, V1, V2, V3 and V4 with internal
E.V.R and the Bleeder resistors. The bias ratio of the LCD driving voltage is selected out of 1/5, 1/6, 1/7, 1/8,
1/9, and 1/10.
In using the internal power supply, the capacitors CA2 must be connected to the VLCD, V1, V2, V3 and V4
terminals, and the CA2 value must be determined by the evaluation with actual LCD modules.
In using the external power supply, the external LCD driving voltages such as the VLCD, V1, V2, V3 and V4 are
supplied and the internal power supply circuits must be set to “OFF” by DCON = AMPON = "0". In this mode,
voltage booster terminals such as C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6-, VEE, VREF and VREG
must be opened.
In case that the voltage booster is not used but only some parts of internal power supply circuits (Voltage
followers, Voltage regulator and EVR) are used, the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+ C5-, C6+, and
C6- terminals must be opened. And, the external power supply is input to the VOUT terminal, and the reference
voltage to the VREF terminal. The capacitor CA3 must connect to the VREG terminal for voltage stabilization.
- 40 -
NJU6821
ꢀ Connections of the capacitors for the voltage booster
Using all of the internal power supply circuits
(7-time boost)
Using only external power supply circuits
VDD
CA1
VDD
VDD
VEE
VDD
VEE
CA1
VBA
VBA
CA3
VSS
VREF
VREG
VREF
VREG
CA3
VSS
C1-
C1-
CA1
C1+
C1+
C2-
C2-
CA1
C2+
C3-
C2+
C3-
CA1
C3+
C4-
C3+
C4-
CA1
NJU6821
C4+
C5-
C4+
NJU6821
C5-
CA1
C5+
C5+
C6-
C6-
CA1
C6+
VOUT
C6+
VOUT
CA1
CA1
VSS
VLCD
V1
VLCD
V1
VLCD
CA2
V1
V2
V3
V4
External
power
circuit
CA2
CA2
CA2
CA2
V2
V2
V3
V3
V4
V4
VSS
CA2
CA2
CA2
CA2
Reference values
CA1
CA2
CA3
1.0 - 4.7µF
1.0 - 2.2µF
0.1µF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation
and display quality. To minimize this impact, use the shortest possible wires and place the capacitors
to be as close as possible to the LSI.
- 41 -
NJU6821
Using internal power supply circuits
Without the reference voltage generator (1)
(7-time boost)
Using internal power supply circuits
Without the reference voltage generator (2)
(7-time boost)
VDD
VDD
VDD
VDD
VEE
VEE
CA1
CA1
VBA
VBA
VREF
VREF
VREG
VREG
CA3
VSS
CA3
VSS
C1-
C1-
CA1
C1+
CA1
C1+
C2-
C2-
CA1
CA1
CA1
CA1
CA1
CA1
C2+
C2+
C3-
C3-
CA1
C3+
C3+
C4-
C4-
CA1
NJU6821
NJU6821
C4+
C4+
C5-
C5-
CA1
C5+
C5+
C6-
C6-
CA1
C6+
C6+
VOUT
VOUT
CA1
VSS
CA1
VSS
VLCD
CA2
VLCD
V1
CA2
CA2
CA2
CA2
CA2
V1
CA2
V2
V2
CA2
V3
V3
CA2
V4
V4
CA2
VSS
VSS
Reference values
CA1
CA2
CA3
1.0 - 4.7µF
1.0 - 2.2µF
0.1µF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation
and display quality. To minimize this impact, use the shortest possible wires and place the capacitors
to be as close as possible to the LSI.
- 42 -
NJU6821
Using nternal power supply circuits
Without the voltage booster
VDD
VDD
VEE
CA1
VBA
CA3
VSS
VREF
VREG
CA3
VSS
C1-
C1+
C2-
C2+
C3-
C3+
C4-
NJU6821
C4+
C5-
C5+
C6-
C6+
VOUT
External
power
circuit
CA1
VLCD
V1
CA2
CA2
CA2
CA2
CA2
V2
V3
V4
VSS
Reference values
CA1
CA2
CA3
1.0 - 4.7µF
1.0 - 2.2µF
0.1µF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation
and display quality. To minimize this impact, use the shortest possible wires and place the capacitors
to be as close as possible to the LSI.
- 43 -
NJU6821
(28) Partial display function
The partial display function is used to specify some parts of display area on a LCD panels. By using this
function, LCD modules can work in lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower
LCD driving voltage. It is usually used to display a time and calendar in the extremely low power consumption. It
can be programmed to select the duty cycle ratio (1/17, 1/26, 1/32, 1/38, 1/47, 1/66, 1/77), the LCD bias ratio,
the boost level and EVR value by the instructions.
ꢀ Partial display image
NJRC
LCD DRIVER
Low Power and
Low Voltage
LCD DRIVER
Partial display
Normal display
ꢀ Partial display sequence
Optional status
Display OFF (ON/OFF=”0”)
Internal Power supply OFF (DCON=”0”, AMPON=”0”)
WAIT
Setting for LCD driving voltage-related functions
Internal Power supply ON (DCON=”1”, AMPON=”1”)
- Boost level
- EVR value
- LCD bias ratio
WAIT
- Duty cycle ratio
- Initial display line
- Initial COM line
- Other instructions
Setting for display-related functions
Display ON (ON/OFF =”1”)
Partial display Status
- 44 -
NJU6821
(29) Discharge circuit
Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and VLCD terminals.
This circuit is activated by setting “1” to the “DIS” register of the “Discharge” instruction or by setting the “RESb”
terminal to ”0” level. The “Discharge ON/OFF” instruction is usually required just after the internal power supply
is turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the external power supply is
turned off. During the discharge operation, the internal or external power supply must not be turned on.
(30) Reset circuit
The reset circuit initializes the LSI into the following default status. It is activated by setting the RESb terminal to
“0” level. The RESb terminal is usually required to connect to MPU reset terminal in order that the LSI can be
initialized at the same timing of the MPU.
ꢀ Default status
1. DDRAM display data
2. column address
3. row address
:Undefined
:00H
:00H
4. Initial display line
5. Display ON/OFF
6. Reverse display ON/OFF
7. Duty cycle ratio
:0H(1st line)
:OFF
:OFF (normal)
:1/82 duty
8. N-line Inversion ON/OFF
9. COM scan direction
10. Increment mode
11. Reverse SEG direction
12. SWAP mode
13. EVR value
14. Internal power supply
15. Display mode
:OFF
:COM0 → COM79, COMI0, COMI1
:OFF
:OFF (normal)
:OFF (normal)
:(0, 0, 0, 0, 0, 0, 0)
:OFF
:Gradation display mode
:1/9 bias
16. LCD bias ratio
17. Gradation Palette 0
18. Gradation Palette 1
19. Gradation Palette 2
20. Gradation Palette 3
21. Gradation Palette 4
22. Gradation Palette 5
23. Gradation Palette 6
24. Gradation Palette 7
25. Gradation mode control
26. GLSB
:(0, 0, 0, 0, 0)
:(0, 0, 1, 0, 1)
:(0, 1, 0, 1, 0)
:(0, 1, 1, 1, 0)
:(1, 0, 0, 0, 1)
:(1, 0, 1, 0, 1)
:(1, 1, 0, 1, 0)
:(1, 1, 1, 1, 1)
:Variable gradation mode
:GLSB=0
27. Data bus length
28. Discharge circuit
:8-bit data bus length
:OFF
- 45 -
NJU6821
(31)Power supply ON/OFF sequences
The following paragraphs describe power supply ON/OFF sequences, which are to protect the LSI from over
current.
(31-1) Using an external power supply
•
•
Power supply ON sequence
Logic voltage (VDD) must be always input first, and next the LCD driving voltages (V1 to V4 and VLCD) are
turned on. In using the external VOUT, the VDD must be input first, next the reset operation must be
performed, and finally the VOUT can be input.
Power supply OFF sequence
Either the reset operation, cutting off the V1 to V4 and VLCD from the LSI by the RESb terminal or the
“Power control” instruction must be performed first, and next the VDD is turned off. It is recommended that
a series-resister between 50Ω and 100Ω is added on the VLCD line (or VOUT line in using only the external
VOUT voltage) in order to protect the LSI from the over current.
(31-2) Using the internal power supply circuits
•
•
Power supply ON sequence
The VDD must be input first, next the reset operation must be performed, and finally the V1 to V4 and VLCD
can be turned on by setting “1” to the “DCON” and “AMPON” registers of the “Power control” instruction.
Power supply OFF sequence
Either the reset operation by the RESb terminal or the “Power control” instruction must be performed first,
and next the input voltage for the voltage booster (VEE) and the VDD can be turned off. If the VEE is supplied
from different power sources for VDD, the VEE is turned off first, and next the VDD is turned off.
- 46 -
NJU6821
(32)Referential instruction sequences
(32-1) Initialization in using the internal power supply circuits
VDD, VEE power ON
Wait for power-ON stabilization
RESET Input
WAIT
Setting for LCD driving voltage-related functions
End of initialization
- EVR value
- LCD bias ratio
- Power control (DCON=”1”, AMPON=”1”)
(32-2) Display data writing
End of Initialization
Setting for display-related functions
- Initial display line
- Increment mode
- Column address
- Row address
Display data write
Display ON (ON/OFF =”1”)
- 47 -
NJU6821
(32-3) Power OFF
Optional status
- All COM/SEG output VSS level.
Power save or reset operation
Discharge ON
WAIT
VEE, VDD power OFF
- 48 -
NJU6821
(33)Instruction table
Instruction Table (1)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Display data write
Display data read
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0/1 0/1 0/1
0/1 0/1 0/1
Write Data
Read Data
Write display data to DDRAM
Read display data from DDRAM
DDRAM column address
DDRAM column address
DDRAM row address
column address
(Lower) [0H]
AX3 AX2 AX1 AX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
column address
(Upper) [1H]
*
AX6 AX5 AX4
row address
AY3 AY2 AY1 AY0
(Lower) [2H]
row address
*
AY6 AY5 AY4
DDRAM row address
(Upper) [3H]
Initial display line
(Lower) [4H]
Row address for an initial COM line
(Scan start line)
LA3 LA2 LA1 LA0
Initial display line
(Upper) [5H]
Row address for an initial COM line
(Scan start line)
*
N3
*
LA6 LA5 LA4
N-line inversion
(Lower) [6H]
N2
N6
N1
N5
N0
N4
The number of N-line inversion
N-line inversion
(Upper) [7H]
The number of N-line inversion
SHIFT: Common direction
Display control (1)
[8H]
SHI MO ALL ON/ MON: Gradation or B/W display mode
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
FT
N
ON OFF
ALLON: All pixels ON/OFF
ON/OFF: Display ON/OFF
REV: Reverse display ON/OFF
Display control (2)
[9H]
RE
V
NL SW RE NLIN: N-line inversion ON/OFF,
IN
AP
F
SWAP: SWAP mode ON/OFF
REF: Segment direction
WIN: Window addressing mode ON/OFF
AIM: Read-modify-write ON/OFF
AYI: Row auto-increment mode ON/OFF
AXI: Column auto-increment mode
ON/OFF
Increment control
[AH]
WIN AIM AYI AXI
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
AMPON: Voltage followers ON/OFF
Power control
[BH]
AMP HA DC AC HALT: Power save ON/OFF
ON
LT
ON
L
DCON: Voltage booster ON/OFF
ACL: Reset
Duty cycle ratio
[CH]
*
DS2 DS1 DS0
VU2 VU1 VU0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Sets LCD duty cycle ratio
Sets boost level
Boost level
[DH]
*
*
LCD bias ratio
[EH]
B2
B1
B0
Sets LCD bias ratio
RE flag set
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
Note 1)
*
: Don’t care.
Note 2) [NH] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 49 -
NJU6821
Instruction Table (2)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette A0
(Lower) [0H]
Sets palette values to gradation
palette A0
PA03 PA02 PA01 PA00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Gradation palette A0
(Upper) [1H]
Sets palette values to gradation
palette A0
*
*
*
PA04
Gradation palette A1
(Lower) [2H]
Sets palette values to gradation
palette A1
PA13 PA12 PA11 PA10
Gradation palette A1
(Upper) [3H]
Sets palette values to gradation
palette A1
*
*
*
PA14
Gradation palette A2
(Lower) [4H]
Sets palette values to gradation
palette A2
PA23 PA22 PA21 PA20
Gradation palette A2
(Upper) [5H]
Sets palette values to gradation
palette A2
*
*
*
PA24
Gradation palette A3
(Lower) [6H]
Sets palette values to gradation
palette A3
PA33 PA32 PA31 PA30
Gradation palette A3
(Upper) [7H]
Sets palette values to gradation
palette A3
*
*
*
PA34
Gradation palette A4
(Lower) [8H]
Sets palette values to gradation
palette A4
PA43 PA42 PA41 PA40
Gradation palette A4
(Upper) [9H]
Sets palette values to gradation
palette A4
*
*
*
PA44
Gradation palette A5
(Lower) [AH]
Sets palette values to gradation
palette A5
PA53 PA52 PA51 PA50
Gradation palette A5
(Upper) [BH]
Sets palette values to gradation
palette A5
*
*
*
PA54
Gradation palette A6
(Lower) [CH]
Sets palette values to gradation
palette A6
PA63 PA62 PA61 PA60
Gradation palette A6
(Upper) [DH]
Sets palette values to gradation
palette A6
*
*
*
PA64
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
*
: Don’t care.
Note 2) [NH] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 50 -
NJU6821
Instruction Table (3)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette A7
(Lower) [0H]
Sets palette values to gradation
palette A7
PA73 PA72 PA71 PA70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Gradation palette A7
(Upper) [1H]
Sets palette values to gradation
palette A7
*
*
*
PA74
Gradation palette B0
(Lower) [2H]
Sets palette values to gradation
palette B0
PB03 PB02 PB01 PB00
Gradation palette B0
(Upper) [3H]
Sets palette values to gradation
palette B0
*
*
*
PB04
Gradation palette B1
(Lower) [4H]
Sets palette values to gradation
palette B1
PB13 PB12 PB11 PB10
Gradation palette B1
(Upper) [5H]
Sets palette values to gradation
palette B1
*
*
*
PB14
Gradation palette B2
(Lower) [6H]
Sets palette values to gradation
palette B2
PB23 PB22 PB21 PB20
Gradation palette B2
(Upper) [7H]
Sets palette values to gradation
palette B2
*
*
*
PB24
Gradation palette B3
(Lower) [8H]
Sets palette values to gradation
palette B3
PB33 PB32 PB31 PB30
Gradation palette B3
(Upper) [9H]
Sets palette values to gradation
palette B3
*
*
*
PB34
Gradation palette B4
(Lower) [AH]
Sets palette values to gradation
palette B4
PB43 PB42 PB41 PB40
Gradation palette B4
(Upper) [BH]
Sets palette values to gradation
palette B4
*
*
*
PB44
Gradation palette B5
(Lower) [CH]
Sets palette values to gradation
palette B5
PB53 PB52 PB51 PB50
Gradation palette B5
(Upper) [DH]
Sets palette values to gradation
palette B5
*
*
*
PB54
RE register
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
[FH]
Note 1)
*
: Don’t care.
Note 2) [NH] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 51 -
NJU6821
Instruction Table (4)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette B6
(Lower) [0H]
Sets palette values to gradation
palette B6
PB63 PB62 PB61 PB60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Gradation palette B6
(Upper) [1H]
Sets palette values to gradation
palette B6
*
*
*
PB64
Gradation palette B7
(Lower) [2H]
Sets palette values to gradation
palette B7
PB73 PB72 PB71 PB70
Gradation palette B7
(Upper) [3H]
Sets palette values to gradation
palette B7
*
*
*
PB74
Gradation palette C0
(Lower) [4H]
Sets palette values to gradation
palette C0
PC03 PC02 PC01 PC00
Gradation palette C0
(Upper) [5H]
Sets palette values to gradation
palette C0
*
*
*
PC04
Gradation palette C1
(Lower) [6H]
Sets palette values to gradation
palette C1
PC13 PC12 PC11 PC10
Gradation palette C1
(Upper) [7H]
Sets palette values to gradation
palette C1
*
*
*
PC14
Gradation palette C2
(Lower) [8H]
Sets palette values to gradation
palette C2
PC23 PC22 PC21 PC20
Gradation palette C2
(Upper) [9H]
Sets palette values to gradation
palette C2
*
*
*
PC24
Gradation palette C3
(Lower) [AH]
Sets palette values to gradation
palette C3
PC33 PC32 PC31 PC30
Gradation palette C3
(Upper) [BH]
Sets palette values to gradation
palette C3
*
*
*
PC34
Gradation palette C4
(Lower) [CH]
Sets palette values to gradation
palette C4
PC43 PC42 PC41 PC40
Gradation palette C4
(Upper) [DH]
Sets palette values to gradation
palette C4
*
*
*
PC44
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
*
: Don’t care.
Note 2) [NH] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 52 -
NJU6821
Instruction Table (5)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette C5
(Lower) [0H]
Sets palette values to gradation
palette C5
PC53 PC52 PC51 PC50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
*
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
*
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
*
Gradation palette C5
(Upper) [1H]
Sets palette values to gradation
palette C5
*
*
*
PC54
Gradation palette C6
(Lower) [2H]
Sets palette values to gradation
palette C6
PC63 PC62 PC61 PC60
Gradation palette C6
(Upper) [3H]
Sets palette values to gradation
palette C6
*
*
*
PC64
Gradation palette C7
(Lower) [4H]
Sets palette values to gradation
palette C7
PC73 PC72 PC71 PC70
Gradation palette C7
(Upper) [5H]
Sets palette values to gradation
palette C7
*
*
*
*
*
PC74
Initial COM line
[6H]
SC2 SC1 SC0
EX
Sets scan-starting common driver
Controls EXCS signal
EXCS control
[7H]
*
*
CS
Gradation mode control
[8H]
Sets variable or fixed gradation
mode
PW
M
GL
SB
*
*
Data bus length
[9H]
WL
S
*
*
CKS
Sets 8- or 16-bit data bus length
EVR control
Sets EVR level
(Lower bit)
DV3 DV2 DV1 DV0
(Lower) [AH]
EVR control
Sets EVR level
(Upper bit)
*
DV6 DV5 DV4
(Upper) [BH]
Frequency control
[DH]
FFL RF2 RF1 RF0
Oscillation frequency
Discharge ON/OFF
[EH]
Discharge the electric charge in
capacitors on V1 to V4 and VLCD
*
*
*
DIS
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag
Instruction register address
[CH]
RA3 RA 2 RA 1 RA 0
Read Data
1
0
0
Sets instruction register address
Read out instruction register data
Instruction register read
0/1 0/1 0/1
Note 1)
*
: Don’t care.
Note 2) [NH] : Address of Instruction register
Note 3)
Note 4)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
CKS=0: Internal oscillation mode (default)
CKS=1: External oscillation mode
- 53 -
NJU6821
Instruction Table (6)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Window end
column address
(Lower) [0H]
Window end
column address
(Upper) [1H]
EX3 EX2 EX1 EX0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Sets column address for end point
Sets column address for end point
Sets row address for end point
Sets row address for end point
Sets address for reverse line
Sets address for reverse line
Sets address for reverse line
Sets address for reverse line
Controls reverse line display
Controls icon segment register
Sets PWM mode
*
EX6 EX5 EX4
Window end row address
(Lower) [2H]
EY3 EY2 EY1 EY0
Window end row address
(Upper) [3H]
*
EY6 EY5 EY4
Initial reverse line
(Lower) [4H]
LS3 LS2 LS1 LS0
Initial reverse line
(Upper) [5H]
*
LS6 LS5 LS4
Last reverse line
(Lower) [6H]
LE3 LE2 LE1 LE0
Last reverse line
(Upper) [7H]
*
*
*
LE6 LE5 LE4
Reverse line display
ON/OFF
LR
*
*
BT
*
EV
[8H]
Dummy segment register
ON/OFF
[9H]
DM
Y
PWM control
[AH]
PW PW PW PW
MS MA MB MC
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag
Note 1)
*
: Don’t care.
Note 2) [NH] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 54 -
NJU6821
(34)Instruction descriptions
This chapter provides detail descriptions and instruction registers. Nonexistent instruction codes must not be
set into the LSI.
(34-1) Display data write
The “Display data write” instruction is used to write 8-bit display data into the DDRAM.
CSb RS RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Display data
(34-2) Display data read
The “Display data read” instruction is used to read out 8-bit display data from the DDRAM, where the
column address and row address must be specified beforehand by the “column address” and “row
address” instructions. The dummy read is required just after the “column address” and “row address”
instructions.
CSb RS RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
Display data
(34-3) Column address
The “column address” instruction is used to specify the column address for display data’s reading and
writting operations. It requires dual bytes for lower 4-bit and upper 3-bit data. The instruction for the lower
4-bit data must be executed first, next the instruction for the upper 3-bit.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
AX3 AX2 AX1 AX0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
AX6 AX5 AX4
(34-4) Row address
The “row address” instruction is used to specify the row address for the display data read and write
operations. It requires dual bytes for lower 4-bit and upper 3-bit data. The instruction for the lower 4-bit
data must be executed first, next the instruction for upper 3-bit.
The row address is specified in between 00H and 51H, where the address 50H and 51H are assigned to the
PGRAM for the icon display. The setting for the nonexistent row address between 52H and FFH is
prohibited.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
AY3 AY2 AY1 AY0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
AY6 AY5 AY4
- 55 -
NJU6821
(34-5) Initial display line
The “Initial display line” instruction is used to specify the line address corresponding to the initial COM line.
The initial COM line specified by the “Initial COM line” instruction and indicates the common driver that
starts scanning data.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
LA3 LA2 LA1 LA0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
LA6 LA5 LA4
LA6
0
LA5
0
LA4
0
LA3
0
LA2
0
LA1
LA0
0
Line address
0
0
0
1
0
0
0
0
0
1
:
:
:
:
1
0
0
1
1
1
1
79
(34-6) N-line inversion
The “N-line inversion” instruction is used to control the alternate rates of the liquid crystal direction. It is
programmed to select the N value between 2 and 80, and the FR signal toggles once every N lines by
setting “1” into the “NLIN” register of the “Display control (2)” instruction. When the N-line inversion is
disabled by setting “0” into the “NLIN” register, the FR signal toggles by the frame.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
N3
D2
N2
D1
N1
D0
N0
0
1
1
0
0
0
0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
N6
D1
N5
D0
N4
0
1
1
0
0
0
0
N6
N5
N4
0
N3
0
N2
0
N1
N0
0
N value
0
0
0
0
0
0
Inhibited
2
0
0
0
1
:
:
:
:
1
0
0
1
1
1
1
80
- 56 -
NJU6821
ꢀ N-line Inversion Timing (1/82 duty cycle ratio)
N-line inversion OFF
1st line
3rd line
81st line
1st line
82nd line
2nd line
CL
FLM
FR
N-line inversion ON
N-line control
1st line
3rd line
Nst line
2nd line
2nd line
1st line
CL
FR
(34-7) Display control (1)
The “Display control (1)” instruction is used to control display conditions by setting the “Display ON/OFF”,
“All pixels ON/OFF”, Display mode” and “Common direction” registers.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
SHIFT
MON
ALLON ON/OFF
0
1
1
0
0
0
0
ꢀ ON/OFF register
ON/OFF=0
: Display OFF (All COM/SEG output Vss level.)
ON/OFF=1: Display ON
ꢀ All ON register
The “All pixels ON/OFF” register is used to turn on all pixels without changing display data of the DDRAM.
The setting for the “All pixels ON/OFF” register has a priority over the “Reverse display ON/OFF” register.
ALLON=0 : Normal
ALLON=1 : All pixels turn on.
ꢀ MON register
MON=0
MON=1
: Gradation mode
: B&W mode
ꢀ SHIFT register
SHIFT=0 : COM0 → COM79
SHIFT=1 : COM79 → COM0
- 57 -
NJU6821
(34-8) Display control (2)
The “Display control (2)” instruction is used to control display conditions by setting the “Segment direction”,
“SWAP mode ON/OFF”, “N-line inversion ON/OFF” and “Reverse display ON/OFF” registers.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
D2
D1
D0
REV
NLIN
SWAP
REF
0
1
1
0
0
0
0
ꢀ REF register
The “REF” register is used to reverse the assignment between segment drivers and column address, and
it is possible to reduce restrictions for placement of the LSI on the LCD module. For more information, see
(10) “The relation among the DDRAM column address, display data and segment drivers”.
ꢀ SWAP register
The “SWAP” register is used to reverse the arrangement of the display data in the DDRAM.
SWAP=0 : SWAP mode OFF
SWAP=1 : SWAP mode ON
(Normal)
SWAP=”0”
SWAP=”1”
Write data
RAM data
Read data
D7 D6 D5 D4 D3 D2 D1 D0
d7 d6 d5 d4 d3 d2 d1 d0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
d0 d1 d2 d3 d4 d5 d6 d7
D7 D6 D5 D4 D3 D2 D1 D0
ꢀ NLIN register
The “NLIN” is used to enable or disable the N-line inversion.
NLIN=0
NLIN=1
: N-line inversion OFF
: N-line inversion ON
(The FR signal toggles by the flame.)
(The FR signal toggles once every N frames.)
ꢀ REV register
The “REV” register is used to enable or disable the reverse display mode that reverses the polarity of the
display data without changing the display data of the DDRAM.
REV=0
REV=1
: Reverse display mode OFF
: Reverse display mode ON
REV
Display
Normal
DDRAM data → Display data
0
1
0
1
0
1
1
0
0
1
Reverse
- 58 -
NJU6821
(34-9) Increment control
The “Increment control” instruction is used for the increment mode. In using the auto-increment mode,
DDRAM address automatically increment (+1) whenever the DDRAM is accessed by the “Display data
write” or “Display data read” instruction, Therefore, once “Display data write” or “Display data read”
instruction is established, it is possible to continuously access to the DDRAM without the “column address”
and “row address” instructions. The settings for the “AIM”, “AXI” and “AYI” registers are listed in the
following tables.
CS
0
RS
1
RD WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
0
0
0
WIN AIM AYI AXI
ꢀ AIM, AYI and AXI registers
AIM
Increment mode
Note
Auto-increment for both of the display data read and write operations
Auto-increment for the display write operation (Read modify write)
0
1
-
-
AYI
0
0
AXI
0
1
Increment mode
Note
No auto-increment
1
2
3
Auto-increment for the column address
Auto-increment for the row address
1
0
Auto-increment for the column address and row
address
1
1
4
Note 1) Auto-increment is disabled independent of the “AIM” register.
Note 2) Auto-increment of the column address is enabled in accordance with the “AIM” register.
MAXH
MAXH in the 8-bit data bus mode
00H
: 7FH
MAXH in the 16-bit data bus mode : 3FH
Note 3) Auto-increment of the row address is enabled in accordance with the “AIM” register.
51H
00H
Note 4) Auto-increment of the column address and row address are enabled. The row address increments
whenever the column address reaches to the MAXH.
MaxH
00H
51H
00H
column address
row address
MAXH in the 8-bit data bus mode
: 7FH
MAXH in the 16-bit data bus mode : 3FH
- 59 -
NJU6821
ꢀ WIN register
The “WIN” register is used to access to the DDRAM for the window display area, where the start point is
determined by the “column address” and “row address” instructions, and the end point by the “Window end
column address “and ”Window end row address” instructions. The setting sequence for the window display
area is listed as follows. For more detail, see (7) “Window addressing mode”.
WIN=0 :Window addressing mode OFF
WIN=1 :Window addressing mode ON
1. Set WIN=1, AXI=1, and AYI=1 by “Increment control” instruction
2. Set the start point by the “column address” and “row address” instructions
3. Set the end point by the “Window end column address” and “Window end row address” instructions
4. Enable to access to the DDRAM in the window addressing mode
START
Address
END
Address
END
Address
START
Address
column address
row address
- 60 -
NJU6821
(34-10) Power control
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
D2
D1
D0
AMPON HALT DCON
ACL
0
1
1
0
0
0
0
ꢀ ACL register
The “ACL” register is used to initialize the internal power supply circuits. It is available only in the master
mode.
ACL=0
ACL=1
: Initialization OFF (Normal)
: Initialization ON
When the data of the “ACL register” is read out by the “Instruction register read” instruction, the read-out
data is “1” during the initialization and “0” after the initialization. This initialization is performed by using the
signal produced by 2 clocks on the OSC1. For this reason, the wait time for 2 clocks of the OSC1 is
necessary until next instruction after the initialization by programming “ACL” register.
ꢀ DCON register
The “DCON” register is used to enable or disable the voltage booster.
DCON=0
DCON=1
: Voltage booster OFF
: Voltage booster ON
ꢀ HALT register
The “HALT” register is used to enable or disable the power save mode. It is possible to reduce operating
current down to stand-by level. The internal status in the power save mode is listed below.
HALT=0
HALT=1
: Power save OFF (Normal)
: Power save ON
Internal status in the power save mode
• The oscillation circuits and internal power supply circuits are halted.
• All segment and common drivers output Vss level.
• The clock input into the OSC1 is inhibited.
• The display data in the DDRAM is maintained.
• The operational modes before the power save mode are maintained.
• The V1 to V4 and VLCD are in the high impedance.
As a power save ON sequence, the “Display OFF” must be executed first, next the “Power save ON”
instruction, and then all common and segment drivers output the Vss level. And as power save OFF
sequence, the “Power save OFF” instruction is executed first, next the “Display ON” instruction. If the
“Power save OFF” instruction is executed in the display ON status, unexpected pixels may instantly turn
on.
ꢀ AMPON register
The “AMPON” register is used to enable or disable the voltage followers, voltage regulator and EVR.
AMPON=0
AMPON=1
: The voltage followers, voltage regulator and the EVR OFF
: The voltage followers, voltage regulator and the EVR ON
- 61 -
NJU6821
(34-11) Duty cycle ratio
The “Duty cycle ratio” instruction is used to select LCD duty cycle ratio for the partial display function. The
partial display function specifies some parts of display area on a LCD panel in the condition of lower duty
cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage. Therefore, it is possible
to optimize the LSI’s conditions with extremely low power consumption.
It can be also programmed to select not only the duty cycle ratio but also the LCD bias ratio, boost level
and EVR value by the instructions so that it is possible to optimize the LSI conditions in accordance with
the display.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
*
D2
D1
D0
0
1
1
0
0
0
0
DS2 DS1 DS0
DS2 DS1 DS0
Duty cycle ratio
1/82
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/77
1/66
1/47
1/32
1/17
1/38
1/26
(34-12) Boost level
The “Boost level” is used to select the multiple of the voltage booster for the partial display function.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
VU2 VU1 VU0
VU2 VU1
VU0
0
1
0
1
0
1
0
1
Boost level
1-time (No boost)
2-time
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
3-time
4-time
5-time
6-time
7-time
Inhibited
- 62 -
NJU6821
(34-13) LCD bias ratio
The “LCD bias ratio” is used to select the LCD bias ratio for the partial display function.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
B2
D1
B1
D0
B0
0
1
1
0
0
0
0
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
LCD bias ratio
1/
9
1/8
1/7
1/6
1/5
1/10
Inhibited
Inhibited
(34-14) RE flag
The “RE flag” registers are used to determine the contents for the Rf registers (RE2, RE1 and RE0) and it
is possible to access to the instruction registers.
The data in the “TST0” register must be “0”, and it is used only for maker tests only.
CSb RS RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
1
D6
1
D5
1
D4
1
D3
D2
D1
D0
0
1
1
0
TST0 RE2 RE1 RE0
- 63 -
NJU6821
(34-15) Gradation palette A, B and C
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
1
PA03 PA02 PA01 PA00
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
0
1
PA04
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
1
PA13 PA12 PA11 PA10
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
0
1
PA14
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
1
PA23 PA22 PA21 PA20
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
0
1
PA24
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
1
PA33 PA32 PA31 PA30
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
0
1
PA34
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
1
PA43 PA42 PA41 PA40
- 64 -
NJU6821
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
0
1
PA44
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
1
PA53 PA52 PA51 PA50
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
0
1
PA54
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
1
PA63 PA62 PA61 PA60
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
0
1
PA64
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
0
PA73 PA72 PA71 PA70
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
0
PA74
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
0
PB03 PB02 PB01 PB00
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
0
PB04
- 65 -
NJU6821
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
0
PB13 PB12 PB11 PB10
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
0
PB14
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
0
PB23 PB22 PB21 PB20
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
0
PB24
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
0
PB33 PB32 PB31 PB30
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
0
PB34
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
0
PB43 PB42 PB41 PB40
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
0
PB44
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
0
PB53 PB52 PB51 PB50
- 66 -
NJU6821
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
0
PB54
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
1
PB63 PB62 PB61 PB60
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
1
PB64
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
1
PB73 PB72 PB71 PB70
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
1
PB74
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
1
PC03 PC02 PC01 PC00
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
1
PC04
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
1
PC13 PC12 PC11 PC10
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
1
PC14
- 67 -
NJU6821
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
1
PC23 PC22 PC21 PC20
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
1
PC24
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
1
PC33 PC32 PC31 PC30
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
1
PC34
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
1
1
PC43 PC42 PC41 PC40
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
0
1
1
PC44
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
PC53 PC52 PC51 PC50
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
1
0
0
PC54
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
PC63 PC62 PC61 PC60
- 68 -
NJU6821
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
1
0
0
PC64
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
PC73 PC72 PC71 PC70
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
1
0
0
PC74
Gradation palette table (Variable gradation mode, PWM=”0” and MON=”0”)
(Palette Aj, Palette Bj, Palette Cj (j=0 to 7))
Gradation
Gradation
level
Palette value
Gradation palette
Palette 0 (default)
Palette value
Gradation palette
level
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Palette 4 (default)
Palette 1 (default)
Palette 5 (default)
Palette 6 (default)
Palette 7 (default)
Palette 2 (default)
Palette 3 (default)
- 69 -
NJU6821
(34-16) Initial COM line
The “Initial COM line” instruction is used to specify the common driver that starts scanning the display data.
The line address, corresponding to the initial COM line, is specified by the “Initial display line” instruction.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
*
D2
D1
D0
0
1
1
0
1
0
0
SC2 SC1 SC0
SC2 SC1 SC0
Initial COM line (SHIFT=0)
Initial COM line (SHIFT=1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COM0
COM15
COM30
COM45
COM60
COM75
Inhibited
Inhibited
COM79
COM64
COM49
COM34
COM19
COM4
Inhibited
Inhibited
SHIFT=0: Positive direction
SHIFT=1: Negative direction
(for instance, COM0 → COM79)
(for instance, COM79 → COM0)
(34-17) EXCS control
The “EXCS control” instruction is available only in the master mode, where it is used to control the polarity
for the EXCS output.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
EXCS
0
1
1
0
1
0
0
EXCS=0: Output level “0”
EXCS=1: Output level “1”
(34-18) Gradation mode control
The “Gradation mode control” is used to determine the display data for the GLSB and select the gradation
mode.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
*
D0
*
PWM GLSB
0
1
1
0
1
0
0
ꢀ GLSB register
GLSB=0: GLSB “0”
GLSB=1: GLSB “1”
ꢀ PWM register
PWM=0: Variable gradation mode
(Variable 8-gradation levels out of 32-gradation level of the gradation palette)
PWM=1: Fixed gradation mode
(Fixed 8-gradation levels)
- 70 -
NJU6821
(34-19) Data bus length
The “Data bus length” instruction is used to select the 8- or 16- bit data bus length and determine the
internal or external oscillation. In the 16-bit data bus mode, instruction data must be 16-bit data (D15 to D0)
as well as display data. However, for the access to the instruction registers, the lower 8-bit data (D7 to D0)
of the 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0) is valid.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
D0
0
1
1
0
1
0
0
CKS WLS
ꢀ WLS register
WLS =0: 8-bit data bus length
WLS =1: 16-bit data bus length
ꢀ CKS register
CKS =0: Internal oscillation
(The OSC1 and OSC2 must be fixed “1” or “0”.)
CKS =1: External oscillation
(By the external clock into the OSC1 or external resister between the OSC1 and OSC2.
OSC2 should be open when clock is inputted from OSC1.)
(34-20) EVR control
The “EVR control” instruction is used to fine-tune the LCD driving voltage (VLCD) so that it is possible to
optimize the contrast level for a LCD panel.
This instruction must be programmed by the upper 3-bit data first, next lower 4-bit data. And it becomes
enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the
VLCD from being generated.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
DV3 DV2 DV1 DV0
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
0
DV6 DV5 DV4
DV6 DV5 DV4 DV3 DV2 DV1 DV0
VLCD
0
0
0
0
0
0
0
0
:
0
0
0
0
0
1
Low
:
:
:
:
1
1
1
1
1
1
1
High
The formula of the VLCD is shown below.
VLCD [V] = 0.5 x VREG + M (VREG – 0.5 x VREG) / 127
VBA = VEE x 0.9
VREG = VREF x N
VBA
VREF
VREG
N
: Output voltage of the reference voltage generator
: Input voltage of the voltage regulator
: Output voltage of the voltage regulator
: Register value for the voltage booster
: Register value for the EVR
M
- 71 -
NJU6821
(34-21) Frequency control
The “Frequency control” instruction is used to control the frame frequency for a LCD panel.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
D2
D1
D0
0
1
1
0
1
0
0
FFL Rf2 Rf1 Rf0
ꢀ Rfx register (x=0, 1, 2)
The “Rfx” register is used to determine the feed back resister value for the internal oscillator and it is
possible to adjust the frame frequency for the LCD modules.
Rf 2
0
0
0
0
Rf 1
0
0
1
1
Rf 0
0
1
0
1
Feedback resistor value
Reference value
0.8 x reference value
0.9 x reference value
1.1 x reference value
1.2 x reference value
Inhibited
1
1
0
0
0
1
1
1
0
Inhibited
1
1
1
Inhibited
ꢀ FFL register
The “FFL” register is used to select normal or high-speed frame frequency mode.
FFL =0:
FFL =1:
Normal
(Frame frequency: 73Hz typical)
High-speed mode (Frame frequency: 150Hz typical)
Note) The above values for the typical frame frequency are based on the following conditions.
Variable gradation mode, 1/82 duty cycle ratio, (Rf2, Rf1, Rf0) = (0,0,0)
(34-22) Discharge ON/OFF
Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and the VLCD
terminals. The “Discharge ON/OFF” instruction is usually required just after the internal power supply is
turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the external power supply is
turned off. During the discharge operation, the internal or external power supply must not be turned on.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
*
D1
*
D0
0
1
1
0
1
0
0
DIS
DIS =0:
DIS =1:
Discharge OFF
Discharge ON
- 72 -
NJU6821
(34-23) Instruction register address
The “Instruction register address” is used to specify the instruction register address, so that it is possible to
read out the contents of the instruction registers in combination with the “Instruction register read”
instruction.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
RA3 RA2 RA1 RA0
(34-24) Instruction register read
The “Instruction register read” instruction is used to read out the contents of the instruction register in
combination with the “Instruction register address” instruction.
CSb RS RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
*
D6
*
D5
*
D4
*
D3
D2
D1
D0
0
1
0
1
Internal register data read
(34-25) Window end column address
The “Window end column address” is used to specify the column address for the window end point. The
lower 4-bit data is required to be programmed first and then the upper 3-bit data can be programmed.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
EX3 EX2 EX1 EX0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
1
EX6 EX5 EX4
(34-26) Window end row address set
The “Window end row address” is used to specify the row address for the window end point. The lower 4-
bit data is required to be programmed first and then the upper 3-bit data can be programmed.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
EY3 EY2 EY1 EY0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
1
EY6 EY5 EY4
- 73 -
NJU6821
(34-27) Initial reverse line
The “Initial reverse line” instruction is used to specify the initial line address for the reverse line display.
Lower 4-bit data must be programmed first, next upper 3-bit data. It is programmed in between 00H and
4FH and the line address beyond 4FH is inhibited. The address relation: LSi < LEi (i=6 to 0) must be
maintained in the reverse line display.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
LS3 LS2 LS1 LS0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
1
LS6 LS5 LS4
(34-28) Last reverse line
The “Last reverse line” instruction is used to specify the last reverse line address for the reverse line
display. Lower 4-bit must be programmed first, next upper 3-bit data. It is programmed in between 00H and
4FH and the line address beyond 4FH is inhibited. The address relation: LSi < LEi (i=6 to 0) must be
maintained in the reverse line display.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
LE3 LE2 LE1 LE0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
1
LE6 LE5 LE4
(34-29) Reverse line display ON/OFF
The “Reverse line display ON/OFF” is used to enable or disable the reverse line display for the blink
operation and determine the reverse line display mode.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
*
D2
*
D1
D0
0
1
1
0
1
0
1
BT LREV
ꢀ LREV register
The “LREV” register is used to enable or disable the reverse line display.
LREV =0: Reverse line display OFF (Normal)
LREV =1: Reverse line display ON
- 74 -
NJU6821
ꢀ BT register
The “BT” register is used to determine the reverse line display mode in the reverse line display ON
(LREV=1) status.
BT =0:
BT =1:
Normal reverse line display
Blink once every 32 frames
Display examples in the LREV=”1” and BT=”1”
ꢁꢂꢂꢂꢁ
ꢂꢁꢁꢁꢂ
ꢂꢁꢁꢁꢁ
ꢁꢂꢂꢂꢁ
ꢁꢁꢁꢁꢂ
ꢂꢁꢁꢁꢂ
ꢁꢂꢂꢂꢁ
ꢁꢁꢁꢁꢁ
ꢂꢁꢁꢁꢂ
ꢁꢂꢂꢂꢁ
ꢁꢂꢂꢂꢂ
ꢂꢁꢁꢁꢂ
ꢂꢂꢂꢂꢁ
ꢁꢂꢂꢂꢁ
ꢂꢁꢁꢁꢂ
ꢂꢂꢂꢂꢂ
Blink once every 32 frames
NJRC
LCD DRIVER
Low Power and
Low Voltage
Blink once every 32 frames
NJRC
←Initial reverse line address
←Last reverse line address
LCD DRIVER
Low Power and
Low Voltage
(34-30) Icon segment register ON/OFF
The “Icon segment address ON/OFF” is used to enable or disable to access to the icon segment register.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
0
1
1
0
1
0
1
DMY
ꢀ DMY register
DMY=0: Access to the DDRAM
DMY=1: Access to the icon segment register
- 75 -
NJU6821
(34-31) PWM control
The “PWM control” is used to determine the PWM type for the segment waveforms, where the type can be
specified for each of the SEGAi, SEGBi and SEGCi (i=0-127) drivers.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PWMS PWMA PWMB PWMC
0
1
1
0
1
0
1
ꢀ PWMS register
PWMS=0: Type 1
PWMS=1: Type 2
ꢀ PWMA, B and C registers
The “PWMA, PWMB and PWMC” registers are used to select the type 1-O or type 1-E.
PWMZ=0 (Z=A, B and C): Type 1-O
PWMZ=1 (Z=A, B and C): Type 1-E
PWM type1 (PWMS=”0”)
Odd line
Even line
“H”
“L”
CL
VLCD
V2
→
←
Type-O
Type-E
SEG
VLCD
V2
→
←
PWM type2 (PWMS=”1”)
“H”
CL
“L”
VLCD
SEG
→
→
V2
- 76 -
NJU6821
(35)The relationship between Common drivers and row addresses
Row address assignment for common drivers is programmed by the “SHIF” register of the “Display control (1),
and “Duty cycle ratio”, “Initial display line” and “Initial COM line” instructions. The assignment for the COMI0 and
COMI1 are independent of these instructions and always fixed.
•
When initial display line is “0”
The relation between common drivers and row address of DDRAM (MY) is changing each 15dots unit by the
“Duty cycle ratio” and “Initial COM line” instructions. If the shift bit is “0”, the order of common scanning is
normal and if it is “1”, the common scanning order is inversed. When LA0 to LA6 of initial display line setting is
“0”, the “MY” corresponding to the Initial COM line is also “0”. And “MY” is increasing.
Regardless above, COMI0 and COMI1 is fixed to MY80 and MY81 respectively.
•
When initial display line is not “0”
The relation between common drivers and row address of DDRAM (MY) is changing each 15dots unit by the
“Duty cycle ratio” and “Initial COM line” instructions. If the shift bit is “0”, the order of common scanning is
normal and if it is “1”, the common scanning order is inversed. When LA0 to LA6 of initial display line setting is
not “0”, the “MY” corresponding to the Initial COM line is biased by the setting value. During the display, “MY” is
increasing up to “79”. When “MY” over than “79”, its back to “0”. And “MY” is increasing from 0 continuously.
Regardless above, COMI0 and COMI1 is fixed to MY80 and MY81 respectively.
- 77 -
NJU6821
(35-1) Initial display line “0”, 1/82 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“000” (1/82 duty)
DS2
DS1
SC1
DS0
“000” (1/82 duty)
“010” “011”
“0000000” (Initial display line 0)
SC2
LA6
SC0
LA0
“000”
“001”
“100”
“101”
“000”
“001”
“010”
“011”
“100”
“101”
!!!!!!!!
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
65
80
50
80
35
80
20
80
5
80
79
80
64
80
49
80
34
80
19
80
4
COM1
COM2
COM3
COM4
0
COM5
79
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
79
0
0
79
79
0
0
79
79
0
0
79
79
0
0
79
79
0
79
81
64
81
49
81
34
81
19
81
4
81
0
81
65
81
50
81
35
81
20
81
5
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 78 -
NJU6821
(35-2) Initial display line “0”, 1/77 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“001” (1/77 duty)
“010” “011”
“0000000” (Initial display line 0)
SHIFT=”1” (Common backward scan)
“001” (1/77 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
65
80
50
80
35
80
20
80
5
80
64
80
49
80
34
80
19
80
4
COM1
COM2
COM3
COM4
0
COM5
74
COM6
COM7
COM8
COM9
74
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
74
0
0
74
74
0
0
74
74
0
0
74
74
0
0
74
74
74
81
0
64
81
49
81
34
81
19
81
4
81
0
81
65
81
50
81
35
81
20
81
5
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 79 -
NJU6821
(35-3) Initial display line “0”, 1/66 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“010” (1/66 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“010” (1/66 duty)
“010” “011”
“0000000” (Initial display line 0)
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
80
50
80
35
80
20
80
5
80
63
80
49
80
34
80
19
80
4
COM1
COM2
COM3
COM4
0
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
63
0
63
0
63
63
0
0
63
63
0
0
63
63
0
63
0
63
0
63
81
49
81
34
81
19
81
4
81
0
81
50
81
35
81
20
81
5
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 80 -
NJU6821
(35-4) Initial display line “0”, 1/47 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“011” (1/47 duty)
“010” “011”
“0000000” (Initial display line 0)
SHIFT=”1” (Common backward scan)
“011” (1/47 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
80
80
35
80
20
80
5
80
80
80
34
80
19
80
4
COM1
COM2
COM3
COM4
0
COM5
44
COM6
COM7
COM8
COM9
44
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
0
0
44
44
0
0
44
44
44
44
0
0
44
44
0
0
44
44
81
0
34
81
19
81
4
81
0
81
35
81
20
81
5
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 81 -
NJU6821
(35-5) Initial display line “0”, 1/32 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“100” (1/32 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“100” (1/32 duty)
“010” “011”
“0000000” (Initial display line 0)
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
80
80
80
20
80
5
80
80
80
80
19
80
4
COM1
COM2
COM3
COM4
0
COM5
29
COM6
COM7
COM8
COM9
29
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
0
0
29
29
29
0
0
29
29
0
0
29
29
29
0
0
29
29
81
0
19
81
4
81
0
81
20
81
5
81
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 82 -
NJU6821
(35-6) Initial display line “0”, 1/17 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“101” (1/17 duty)
“010” “011”
“0000000” (Initial display line 0)
SHIFT=”1” (Common backward scan)
“101” (1/17 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
80
80
80
80
5
80
80
80
80
80
4
COM1
COM2
COM3
COM4
0
COM5
14
COM6
COM7
COM8
COM9
14
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
14
0
0
14
14
0
0
14
14
0
0
14
14
0
0
14
14
14
81
0
4
81
0
81
5
81
81
81
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 83 -
NJU6821
(35-7) Initial display line “0”, 1/38 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“110” (1/38 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“110” (1/38 duty)
“010” “011”
“0000000” (Initial display line 0)
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
80
80
35
80
20
80
5
80
80
80
34
80
19
80
4
COM1
COM2
COM3
COM4
0
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
35
0
35
0
35
0
35
0
35
35
0
0
35
35
0
0
35
35
0
34
81
19
81
4
81
0
81
35
81
20
81
5
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 84 -
NJU6821
(35-8) Initial display line “0”, 1/26 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“111” (1/26 duty)
“010” “011”
“0000000” (Initial display line 0)
SHIFT=”1” (Common backward scan)
“111” (1/26 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000000” (Initial display line 0)
COMI0
COM0
80
0
80
80
80
80
20
80
5
80
80
80
80
19
80
4
COM1
COM2
COM3
23
COM4
0
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
23
0
23
0
23
23
0
0
23
23
0
0
23
23
0
23
0
23
0
23
19
81
4
81
0
81
20
81
5
81
81
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 85 -
NJU6821
(35-9) Initial display line “5”, 1/82 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“000” (1/82 duty)
DS2
DS1
SC1
DS0
“000” (1/82 duty)
“010” “011”
“0000101” (Initial display line 5)
SC2
LA6
SC0
LA0
“000”
“001”
“100”
“101”
“000”
“001”
“010”
“011”
“100”
“101”
!!!!!!!!
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
70
80
55
80
40
80
25
80
10
80
4
80
69
80
54
80
39
80
24
80
9
COM1
COM2
COM3
COM4
0
5
COM5
79
COM6
COM7
COM8
COM9
79
0
0
79
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
5
5
79
0
0
79
5
5
79
0
0
79
5
5
79
0
0
79
5
5
79
0
0
79
79
0
5
4
81
69
81
54
81
39
81
24
81
9
81
5
81
70
81
55
81
40
81
25
81
10
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 86 -
NJU6821
(35-10) Initial display line “5”, 1/77 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“001” (1/77 duty)
“010” “011”
“0000101” (Initial display line 5)
SHIFT=”1” (Common backward scan)
“001” (1/77 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
70
80
55
80
40
80
25
80
10
80
69
80
54
80
39
80
24
80
9
COM1
COM2
COM3
COM4
5
COM5
79
COM6
COM7
COM8
COM9
79
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
79
5
5
79
79
5
5
79
79
5
5
79
79
5
5
79
79
79
81
5
69
81
54
81
39
81
24
81
9
81
5
81
70
81
55
81
40
81
25
81
10
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 87 -
NJU6821
(35-11) Initial display line “5”, 1/66 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“010” (1/66 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“010” (1/66 duty)
“010” “011”
“0000101” (Initial display line 5)
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
80
55
80
40
80
25
80
10
80
68
80
54
80
39
80
24
80
9
COM1
COM2
COM3
COM4
5
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
68
5
68
5
68
68
5
5
68
68
5
5
68
68
5
68
5
68
5
68
81
54
81
39
81
24
81
9
81
5
81
55
81
40
81
25
81
10
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 88 -
NJU6821
(35-12) Initial display line “5”, 1/47 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“011” (1/47 duty)
“010” “011”
“0000101” (Initial display line 5)
SHIFT=”1” (Common backward scan)
“011” (1/47 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
80
80
40
80
25
80
10
80
80
80
39
80
24
80
9
COM1
COM2
COM3
COM4
5
COM5
49
COM6
COM7
COM8
COM9
49
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
5
5
49
49
5
5
49
49
49
49
5
5
49
49
5
5
49
49
81
5
39
81
24
81
9
81
5
81
40
81
25
81
10
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 89 -
NJU6821
(35-13) Initial display line “5”, 1/32 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“100” (1/32 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“100” (1/32 duty)
“010” “011”
“0000101” (Initial display line 5)
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
80
80
80
25
80
10
80
80
80
80
24
80
9
COM1
COM2
COM3
COM4
5
COM5
34
COM6
COM7
COM8
COM9
34
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
5
5
34
34
34
5
5
34
34
5
5
34
34
34
5
5
34
34
81
5
24
81
9
81
5
81
25
81
10
81
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 90 -
NJU6821
(35-14) Initial display line “5”, 1/17 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“101” (1/17 duty)
“010” “011”
“0000101” (Initial display line 5)
SHIFT=”1” Common backward scan)
“101” (1/17 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
80
80
80
80
10
80
80
80
80
80
9
COM1
COM2
COM3
COM4
5
COM5
19
COM6
COM7
COM8
COM9
19
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
19
5
5
19
19
5
5
19
19
5
5
19
19
5
5
19
19
19
81
5
9
81
5
81
10
81
81
81
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 91 -
NJU6821
(35-15) Initial display line “5”, 1/38 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
SHIFT=”1” (Common backward scan)
“110” (1/38 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“110” (1/38 duty)
“010” “011”
“0000101” (Initial display line 5)
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
80
80
40
80
25
80
10
80
80
80
39
80
24
80
9
COM1
COM2
COM3
COM4
5
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
40
5
40
5
40
5
40
5
40
40
5
5
40
40
5
5
40
40
5
39
81
24
81
9
81
5
81
40
81
25
81
10
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 92 -
NJU6821
(35-16) Initial display line “5”, 1/26 duty cycle
SHIFT set value
SHIFT=”0” (Common forward scan)
“111” (1/26 duty)
“010” “011”
“0000101” (Initial display line 5)
SHIFT=”1” (Common backward scan)
“111” (1/26 duty)
DS2
SC2
LA6
DS1
SC1
!!!!!!!!
DS0
SC0
LA0
“000”
“001”
“100”
“101”
“000”
80
“001”
“010”
“011”
“100”
“101”
“0000101” (Initial display line 5)
COMI0
COM0
80
5
80
80
80
80
25
80
10
80
80
80
80
24
80
9
COM1
COM2
COM3
28
COM4
5
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
28
5
28
5
28
28
5
5
28
28
5
5
28
28
5
28
5
28
5
28
24
81
9
81
5
81
25
81
10
81
81
81
81
81
81
81
81
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
- 93 -
NJU6821
ꢀ ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
Supply Voltage (3)
Supply Voltage (4)
Supply Voltage (5)
Supply Voltage (6)
Input Voltage
SYMBOL
VDD
VEE
VOUT
VREG
VLCD
V1, V2, V3, V4
VI
CONDITION
TERMINAL
VDD
RATING
-0.3 to +4.0
-0.3 to +4.0
UNIT
V
V
V
V
V
V
V
°C
VEE
VOUT
VREG
VLCD
-0.3 to +20.0
-0.3 to +20.0
-0.3 to +20.0
-0.3 to VLCD + 0.3
-0.3 to VDD + 0.3
-45 to +125
VSS=0V
Ta = +25°C
V1, V2, V3, V4
*1
Storage Temperature
Tstg
Note 1) D0 to D15, CSb, RS, M/S, RDb, WRb, OSC1, CL, FLM, FR, CLK, RESb, TEST terminals.
Note 2) To stabilize the voltage booster operation, decoupling capacitors must be connected between the
VDD and VSS pins and between the VEE and VSSH pins.
ꢀ RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD1
VDD2
VEE
VLCD
VOUT
VREG
VREF
TERMINAL
VDD
MIN
1.7
2.4
2.4
5
TYP
MAX
3.3
3.3
UNIT
V
V
V
V
V
V
V
NOTE
*1
*2
*3
*4
Supply Voltage
VEE
VLCD
VOUT
VREG
VREF
3.3
18.0
18.0
OUT × 0.9
3.3
Operating Voltage
V
2.1
-30
*5
Operating
Temperature
Topr
85
°C
Note1) Applies to the condition when the reference voltage generator is not used.
Note2) Applies to the condition when the reference voltage generator is used.
Note3) Applies to the condition when the voltage booster is used.
Note4) The following relationship among the supply voltages must be maintained.
VSS<V4<V3<V2<V1<VLCD<VOUT
Note5) The relationship: VREF<VEE must be maintained.
- 94 -
NJU6821
ꢀ DC CHARACTERISTICS 1
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85°C
SYMB
PARAMETER
OL
CONDITION
MIN
TYP
MAX
UNIT NOTE
VIH
VIL
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input leakage current
0.8 VDD
0
VDD - 0.4
VDD
0.22VDD
V
V
V
V
V
V
µA
µA
*1
*1
*2
*2
*3
*3
*4
*5
VOH1
VOL1
VOH2
VOL2
ILI
IOH = -0.4mA
IOL = 0.4 mA
IOH = -0.1mA
IOL = 0.1 mA
VI = VSS or VDD
VI = VSS or VDD
0.4
VDD - 0.4
0.4
10
10
2
-10
-10
ILO
Output leakage current
VLCD = 10V
VLCD = 6V
1
2
RON1
Driver ON-resistance
Stand-by current
*6
|∆VON| = 0.5V
kΩ
µA
4
ISTB
VDD = 3V
15
*7
CSb=VDD, Ta=25°C
fOSC1
fOSC2
fOSC3
fOSC4
fOSC5
305
68
9.8
625.3
141.2
20.1
726
401
175
86.2
25.2
12
372
84
12
762.6
172.2
24.6
807
445
194
95.8
28
439
99.2
14.2
899.9
203.2
29.1
888
490
213
105.4
30.8
*8
*9
*10
*8
*9
*10
FFL = “0”
(Standard)
VDD = 3V
Ta = 25°C
Internal oscillation
Frequency
kHz
FFL = “1”
(Hi-speed)
fOSC6
fr1
Rf=10kΩ
Rf=20kΩ
Rf=51kΩ
Rf=110kΩ
Rf=390kΩ
Rf=820kΩ
fr2
fr3
External oscillation
Frequency
kHz
V
*16
fr4
fr5
fr6
13.3
14.6
N-time booster (N=2 to 7)
Voltage converter
output voltage
VOUT
NxVEEx0.95
*11
RL = 500kΩ (VOUT - VSS)
VDD = 2.5V
IDD1
IDD2
IDD3
Supply current (1)
Supply current (2)
Supply current (3)
Supply current (4)
Supply current (5)
Supply current (6)
Supply current (7)
Supply current (8)
FFL = “0”
580
870
670
1060
490
760
580
930
870
1300
1010
1590
740
7-time booster
(Whole ON pattern)
VDD = 2.5V
7-time booster
(Checker pattern)
VDD = 3V
6-time booster
(Whole ON pattern)
VDD = 3V
6-time booster
(Checker pattern)
VDD = 3V
5-time booster
(Whole ON pattern)
VDD = 3V
5-time booster
(Checker pattern)
VDD = 3V
4-time booster
(Whole ON pattern)
VDD = 3V
4-time booster
(Checker pattern)
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
IDD4
IDD5
IDD6
IDD7
IDD8
1140
870
1400
*12
µA
IDD9
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
IDD16
Supply current (9)
Supply current (10)
Supply current (11)
Supply current (12)
Supply current (13)
Supply current (14)
Supply current (15)
Supply current (16)
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
330
520
390
650
220
360
260
450
500
780
590
980
330
540
390
680
(0.9 VEE
x 0.98
)
(0.9 VEE
x 1.02
)
VBA
VBA Operating Voltage
VREG Operating Voltage
VEE = 2.4 to 3.3V
0.9 VEE
V
V
*13
*14
VEE = 2.4 to 3.3V
(VREF
x
(VREF ×N)
x 0.97
VREG
V
REF = 0.9 x VEE
(VREF x N)
N) x 1.03
N-time booster (N=2 to 7)
- 95 -
NJU6821
SYMB
OL
PARAMETER
Output voltage
CONDITION
MIN
TYP
MAX
UNIT NOTE
V2
V3
VD12
VD34
VD24
-100
-100
-30
-30
-30
0
0
0
0
0
+100
+100
+30
+30
+30
mV
*15
- 96 -
NJU6821
ꢀ
CLOCK and FRAME FREQUENCY
Display duty cycle ratio (1/D)
PARAMETER SYNBOL
Display mode
Gradation mode
NOTE
1/82, 1/77, 1/66
1/47, 1/38, 1/32, 1/26
fOSC / (62xDx2)
fOSC / (14xDx2)
fOSC / (2xDx2)
fCK / (62xDx2)
fCK / (14xDx2)
fCK / (2xDx2)
1/17
fOSC / (62xD)
fOSC / (14xD)
fOSC / (2xD)
fCK / (62xD)
fCK / (14xD)
fCK / (2xD)
fOSC / (62xDx4)
fOSC / (14xDx4)
fOSC / (2xDx4)
fCK / (62xDx4)
fCK / (14xDx4)
fCK / (2xDx4)
Internal clock
External clock
fOSC
Simplified gradation mode
B&W mode
Gradation mode
FLM
Simplified gradation mode
fCK
B&W mode
APPLIED TERMINALS and CONDITIONS
Note 1) D0-D15, CSb, RS, M/S, RDb, WRb, P/S, SEL68, CLK, CL, FLM, FR, RESb
Note 2) D0-D15
Note 3) CL, FLM, FR, CLK
Note 4) CSb, RS, M/S, SEL68, RDb, WRb, P/S, RESb, OSC1
Note 5) D0-D15, CL, FLM, FR, CLK in the high impedance
Note 6) SEGA0-SEGA127, SEGB0-SEGB127, SEGC0-SEGC127, COM0-COM79, COMI0, COMI1
- Defines the resistance between the COM/SEG terminals and the power supply terminals
(VLCD, V1, V2, V3 and V4) at the condition of 0.5V deference and 1/9 LCD bias ratio.
Note 7) VDD
- The oscillator is halted, CSb=”1” (disabled), No-load on the COM/SEG drivers.
Note 8) OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the variable gradation mode.
Note 9) OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the fixed gradation mode.
Note 10) OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(1,0,0) (12kHz),
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,1,1) (24kHz),
in the black and white mode.
Note 11) VOUT
- Applies to the condition when the internal voltage booster (N=2-7), the internal oscillator and the internal
power circuits are used.
- VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1)
- 1/5 to 1/10 LCD bias, 1/82 duty cycle, No-load on the COM/SEG drivers.
- RL=500Kohm between VOUT and VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”
Note 12) VDD
- Applies to the condition using the internal oscillator and internal power circuits, no accsess between the
LSI and MPU.
- EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in gradation mode.
- 1/82 duty cycle, No-load on the COM/SEG drivers
- VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”,
1/82 Duty, Ta=25°C
- 97 -
NJU6821
Note 13) VREG
- Applies to the condition that VBA=VREF and voltage booster N= 1.
DCON=”0”, VOUT=13.5V input.
Note 14) VREG
- VEE=2.4V to 3.3V, VREF=0.9VEE, VOUT=18.0V, 1/5 to 1/10 LCD bias ratio, 1/82 duty cycle,
EVR=(1,1,1,1,1,1,1)
- Checkerboard display, No-load on the COM/SEG drivers, the voltage booster N=2 to 7
CA1=CA2=1.0 uF, CA3=0.1 uF, DCON=”0”, AMPON=”1”, NLIN=”0”
Note 15) VLCD, V1, V2, V3, V4
- VEE = 3.0V, VREF = 0.9 VEE, VOUT =15.0V, bias=1/5~1/10, EVR= “1111111”.
Display OFF, No-load on the COM/SEG drivers, the voltage booster N=5
CA2=1.0µF, CA3=0.1µF, DCON=“0”, AMPON=“1”
VLCD
(1)
V1
VD12 : (1) – (2)
VD34 : (3) – (4)
VD24 : (2) – (4)
(2)
V2
V3
(3)
(4)
V4
VSS
Note 16) VDD=3V, Ta=25°C
- 98 -
NJU6821
ꢀ
AC CHARACTERISTERISTICS
ꢁ Write operation (80-type MPU)
tAS8
tAH8
CSb
RS
WRb
tWRLW8
tWRHW8
tDS8
tDH8
D0 D15
tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
90
35
35
ns
ns
ns
WRb
Data setup time
Data hold time
tDS8
tDH8
30
5
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
160
70
70
ns
ns
ns
WRb
Data setup time
Data hold time
tDS8
tDH8
40
5
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
180
80
80
ns
ns
ns
WRb
Data setup time
Data hold time
tDS8
tDH8
70
10
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
- 99 -
NJU6821
ꢁ
Read operation (80-type MPU)
tAH8
tAS8
CSb
RS
tWRLR8
RDb
tWRHR8
tRDH8
D0 D15
tRDD8
tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
180
80
80
ns
ns
ns
RDb
Read Data delay time
Read Data hold time
tRDD8
tRDH8
CL=15pF
60
ns
ns
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
180
80
80
ns
ns
ns
RDb
Read Data delay time
Read Data hold time
tRDD8
tRDH8
CL=15pF
60
ns
ns
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
250
120
120
ns
ns
ns
RDb
Read Data delay time
Read Data hold time
tRDD8
tRDH8
CL=15pF
110
ns
ns
D0 to D15
0
Note) Each timing is specified based on 20% and 80% of VDD.
- 100 -
NJU6821
ꢁ Write operation (68-type MPU)
tAS6
tAH6
CSb
RS
R/Wb
(WRb)
tELW6
tEHW6
E
(RDb)
tDS6
tDH6
D0 D15
tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
90
35
35
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
40
5
ns
ns
D0 to D15
(VDD=2.4 to 2.7V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CS
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
160
70
70
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
50
5
ns
ns
D0 to D15
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
PRMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
180
80
80
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
70
10
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
- 101
NJU6821
ꢁ Read operation (68-type MPU)
tAS6
tAH6
CSb
RS
R/Wb
(WRb)
tELR6
tEHR6
E
(RDb)
tRDH6
D0 D15
tRDD6
tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PRMETER
SYMBOL
tAH6
tAS6
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
180
80
80
ns
ns
ns
E
Read Data delay time
Read Data hold time
tRDD6
tRDH6
CL=15pF
70
ns
ns
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PRMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR8
180
80
80
ns
ns
ns
E
Read Data delay time
Read Data hold time
tRDD6
tRDH6
CL=15pF
70
ns
ns
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PRMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
250
120
120
ns
ns
ns
E
110
Read Data delay time
Read Data hold time
tRDD6
tRDH6
CL=15pF
ns
ns
D0 D15
0
Note) Each timing is specified based on 20% and 80% of VDD.
- 102 -
NJU6821
ꢁ Serial interface
tCSH
tCSS
CSb
RS
tASS
tAHS
tSLW
tSHW
SCL
tCYCS
tDSS
tDHS
SDA
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
Serial clock cycle
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
tCSH
20
20
ns
ns
CSb
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
tCSH
20
20
ns
ns
CSb
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
80
35
35
35
35
35
35
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
tCSH
35
35
ns
ns
CSb
Note) Each timing is specified based on 20% and 80% of VDD.
- 103
NJU6821
ꢁ Display control timing
tCLKHW
tCLKLW
tDCL
CLK
tCLLW
tCLHW
CL
tDFLM
tDFLM
tFRLM
tFRHW
tFR
FLM
FR
<FFL=1>
Input timing (Slave mode)
(VDD=1.7 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
CLK ”H” level pulse width
CLK ”L” level pulse width
tCLKHW
tCLKLW
tCLHW
tCLLW
tDCL
tDFLM
tFR
530
530
ns
ns
CLK
CL ”H” level pulse width
CL ”L” level pulse width
CL delay time
FLM delay time
FR delay time
32.9
32.9
0
-1.0
-1.0
µs
µs
ns
µs
µs
CL
250
1.0
1.0
CL
FLM
FR
Output timing (Master mode)
PARAMETER
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
UNIT
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
CLK ”H” level pulse width
CLK ”L” level pulse width
tCLKHW
tCLKLW
tCLHW
tCLLW
tFRHW
tFRLW
tDCL
tDFLM
tFR
540
540
ns
ns
CLK
CL ”H” level pulse width
CL ”L” level pulse width
33.5
33.5
µs
µs
CL
FLM ”H” level pulse width
FLM ”L” level pulse width
CL delay time
FLM delay time
FR delay time
67
5427
0
0
0
µs
µs
ns
ns
FLM
CL=15pF
CL=15pF
200
500
500
CL
FLM
FR
CL=15pF
ns
Output timing (Master mode)
PARAMETER
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
CLK ”H” level pulse width
CLK ”L” level pulse width
tCLKHW
tCLKLW
tCLHW
tCLLW
tFRHW
tFRLW
tDCL
tDFLM
tFR
540
540
ns
ns
CLK
CL ”H” level pulse width
CL ”L” level pulse width
33.5
33.5
µs
µs
CL
FLM ”H” level pulse width
FLM ”L” level pulse width
CL delay time
FLM delay time
FR delay time
67
5427
0
0
0
µs
µs
ns
ns
ns
FLM
CL=15pF
CL=15pF
CL=15pF
200
1000
1000
CL
FLM
FR
Note) Each timing is specified based on 20% and 80% of VDD.
1/82 Duty
- 104 -
NJU6821
<FFL=0>
Input timing (Slave mode)
(VDD=1.7 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
CLK ”H” level pulse width
CLK ”L” level pulse width
tCLKHW
tCLKLW
tCLHW
tCLLW
tDCL
tDFLM
tFR
1100
1100
ns
ns
CLK
CL ”H” level pulse width
CL ”L” level pulse width
CL delay time
FLM delay time
FR delay time
80
80
0
-1.0
-1.0
µs
µs
ns
µs
µs
CL
250
1.0
1.0
CL
FLM
FR
Output timing (Master mode)
PARAMETER
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
UNIT
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
CLK ”H” level pulse width
CLK ”L” level pulse width
tCLKHW
tCLKLW
tCLHW
tCLLW
tFRHW
tFRLW
tDCL
tDFLM
tFR
1120
1120
ns
ns
CLK
CL ”H” level pulse width
CL ”L” level pulse width
81
81
µs
µs
CL
FLM ”H” level pulse width
FLM ”L” level pulse width
CL delay time
FLM delay time
FR delay time
138
11250
µs
µs
ns
ns
FLM
CL=15pF
CL=15pF
0
0
0
200
500
500
CL
FLM
FR
CL=15pF
ns
Output timing (Master mode)
PARAMETER
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
CLK ”H” level pulse width
CLK ”L” level pulse width
tCLKHW
tCLKLW
tCLHW
tCLLW
tFRHW
tFRLW
tDCL
tDFLM
tFR
1120
1120
ns
ns
CLK
CL ”H” level pulse width
CL ”L” level pulse width
81
81
µs
µs
CL
FLM ”H” level pulse width
FLM ”L” level pulse width
CL delay time
FLM delay time
FR delay time
138
11250
µs
µs
ns
ns
ns
FLM
CL=15pF
CL=15pF
CL=15pF
0
0
0
200
1000
1000
CL
FLM
FR
Note) Each timing is specified based on 20% and 80% of VDD.
1/82 Duty
- 105
NJU6821
ꢁ Input clock timing
tCKLW
tCKHW
OSC1
(VDD=1.7 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
1.64
1.64
7.35
7.35
51.0
51.0
TERMINAL
OSC1 “H” level pulse width (1)
OSC1 “L” level pulse width (1)
OSC1 “H” level pulse width (2)
OSC1 “L” level pulse width (2)
OSC1 “H” level pulse width (3)
OSC1 “L” level pulse width (3)
tCKHW1
tCKLW1
tCKHW2
tCKLW2
tCKHW3
tCKLW3
0.525
0.525
2.45
2.45
17.2
17.2
OSC1
1
OSC1
2
OSC1
3
µs
µs
µs
µs
µs
µs
Note) Each timing is specified based on 20% and 80% of VDD.
Note *1) Applied to the variable gradation mode / MON=”0”, PWM=”0”
Note *2) Applied to the fixed gradation mode / MON=”0”, PWM=”1”
Note *3) Applied to the B&W mode / MON=”1”
- 106 -
NJU6821
ꢁ Reset input timing
tRW
RESb
tR
Internal circuit
status
During reset
End of reset
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
Reset time
SYMBOL CONDITION
MIN.
10.0
MAX.
Terminal
tR
1.0
µs
µs
RESb “L” level pulse width
tRW
RESb
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
UNIT
PARAMETER
Reset time
SYMBOL CONDITION
MIN.
10.0
MAX.
Terminal
tR
1.5
µs
µs
RESb “L” level pulse width
tRW
RESb
Note) Each timing is specified based on 20% and 80% of VDD.
- 107
NJU6821
ꢀ
ꢁ
APPLICATION CIRCUIT EXAMPLES
MPU Connections
80-type MPU interface
1.7V to 3.3V
VCC
VDD
A0
RS
A1 to A7
Decoder
8
7
CSb
(80-type CPU)
IORQb
D0 to D7
D0 to D7
RDb
RDb
WRb
WRb
RESb
RESb
VSS
GND
Reset input
68-type MPU interface
1.7V to 3.3V
VCC
VDD
A0
RS
A1 to A15
Decoder
8
15
CSb
(68-typeCPU) VMA
D0 to D7
E
D0 to D7
RDb(E)
R/W
WRb(R/W)
RESb
GND
RESb
VSS
Reset input
Serial interface
1.7V to 3.3V
VCC
VDD
A0
RS
A1 to A7
Decoder
7
CSb
(CPU)
PORT1
PORT2
SDA
SCL
RESb
RESb
VSS
GND
Reset input
- 108 -
NJU6821
ꢀ
Master LSI and Slave LSI Connections
a) Input interface
(Parallel interface)
(Slave)
(Master)
VDD
RESb
CSb1
CSb2
RS
WRb(R/W)
RDb(E)
D0 to D7
SEL68
8
(4-line serial interface)
(Master)
(Slave)
VDD
RESb
CSb1
CSb2
RS
SDA
SCL
(4-line serial interface, EXCS unification)
(Master)
(Slave)
VDD
RESb
CSb
RS
SDA
SCL
- 109
NJU6821
(3-line serial interface)
(Master)
(Slave)
VDD
RESb
CSb 1
CSb 2
SDA
SCL
(3-line serial interface, EXCS unification)
(Master)
(Slave)
VDD
RESb
CSb
SDA
SCL
- 110 -
NJU6821
b) LCD driving generation circuit
VDD
VDD
VDD
VEE
VBA
VREF
C1+
VDD
VEE
VBA
VREF
C1+
CA1
VSS
CA1
VSS
CA1
CA1
C1-
C2+
C1-
C2+
C2-
C3+
C2-
C3+
CA1
CA1
C3-
C4+
C3-
C4+
C4-
C4-
C5+
C5+
CA1
CA1
C5-
C6+
C5-
C6+
C6-
C6-
VOUT
CA1
VOUT
VSS
CA1
VSS
VREG
VLCD
VREG
VLCD
CA3
VSS
VLCD
V1
CA2
V1
V2
V3
V4
V1
V2
V3
V4
CA2
CA2
V2
V3
CA2
CA2
V4
CLK
CL
CLK
CL
FLM
FR
FLM
FR
The following paragraphs describes the caution of Master/Slave operation.
1) Display timing is controlled by Master chip. The CL, FLM, FR, CLK signals are stopped when Master
chip is display OFF. When “Display OFF” executions, Slave chip must execute “Display OFF”
before Master.
2) When “HALT” command is executed in Master chip, the voltage booster circuit and voltage regulator
circuit is turned off. LCD driver outputs VSS level voltage then display goes to turn off. And VLCD for
Slave chip goes to stop supply. When “HALT” command is executed in Master chip, Display off must
be executed before. Because VLCD for Slave chip is stopped.
3) The EVR control is valid in only Master chip (on this circuit diagram).
4) VOUT terminal should connect to VLCD to prevent condition of floating.
5) OSC1 terminal and OSC2 in Slave chip should be open.
- 111
NJU6821
•
Typical characteristic
PARAMETER
Basic delay time of gste
SYMBOL
MIN
TYP
10
MAX
UNIT
ns
Ta=+25°C, VSS=0V, VDD=3.0V
•
Input output terminal type
(a) Input circuit1
VDD
Terminals:
CSb, RS, RDb, WRb, SEL68, M/S
P/S, RESb
I
Input signal
VSS(0V)
(b-1) Input/Output circuit 1
VDD
Terminals:
FLM, CL, FR, CLK
I/O
Input signal
VSS(0V)
VDD
Output control signal
Output signal
VSS(0V)
(b-2) Input/Output circuit 2
VDD
Terminals:
D0~D15
I/O
Input signal
VSS(0V)
VSS(0V)
Input control signal
VDD
Output control signal
Output signal
VSS(0V)
- 112 -
NJU6821
(c) Display output circuit
VLCD
VLCD
VLCD
V1/V2
Output control
signal 1
Output control signal 2
O
Output control
signal 3
Output control signal 4
VSS(0V)
V3/V4
VSS(0V)
VSS(0V)
Terminals:
SEGA0 to SEGA127
SEGB0 to SEGB127
SEGC0 to SEGC127
COM0 to COM79
COMI0, to COMI1
SEGSA0, to SEGSA3
SEGSB0, to SEGSB3
SEGSC0, to SEGSC3
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 113
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