NJU6825H [NJRC]
Liquid Crystal Driver, 546-Segment, CMOS, TCP;
| 型号： | NJU6825H |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Liquid Crystal Driver, 546-Segment, CMOS, TCP 驱动 接口集成电路 |
| 文件： | 总102页 (文件大小：1297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6825
162COMMON x 128RGB LCD DRIVER
FOR 4,096-COLOR STN DISPLAY
ꢀ GENERAL DESCRIPTION
PACKAGE
The NJU6825 is a 162COMMON x 128RGB LCD driver
for 4,096-color STN display. It contains common drivers,
RGB drivers, a serial and a parallel MPU interface circuit, an
internal LCD power supply, grayscale palettes and
248,832-bit display data RAM. The segment drivers for RGB
(Red, Green, Blue) independently produce optimum 16
grayscales from a built-in 32-grayscale palette, and the LSI
achieves 4,096 colors (16x16x16).
In addition, the NJU6825 operates with a low voltage of
1.7V and a low operating current, therefore it is ideally suited
for battery-powered handheld applications.
TCP
ꢀ FEATURES
ꢁ
ꢁ
ꢁ
ꢁ
4,096-color STN LCD driver
Built-in LCD Drivers
: 162-common Drivers
x
128RGB Drivers (384-segment Drivers in B&W)
Built-in Display Data RAM (DDRAM) : 248,832 bits for Graphic Display
Programmable Display Mode
- Variable 16-grayscale Mode
- Variable 8-grayscale Mode
- Fixed 8-grayscale Mode
- B&W Mode
: 4,096 Colors
: 256 Colors
: 256 Colors
: Black & White
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
8-/16-bit Parallel Interface Selectable
8-/16-bit Bus Length for Display Data Selectable
3-/4-line Serial Interface Selectable
Programmable Duty Ratio and Bias Ratio
Programmable Internal Voltage Booster : Maximum 7 times
Programmable Contrast Control
Various Useful Instructions
Low Operating Current
Low Logic Voltage
: 128-step Electrical Variable Resistor (EVR)
: 450uA Typical at VDD=3V, 4-time Boost, Checker Flag Display
: 1.7V to 3.3V
: 5.0V to 18.0V
Wide LCD Voltage Range
C-MOS Technology
Package
: TCP
Ver.2004-05-12
- 1 -
NJU6825
TABLE OF CONTENTS
ꢀ GENERAL DESCRIPTION
PACKAGE .............................................................................................. 1
ꢀ FEATURES ................................................................................................................................................... 1
ꢀ BLOCK DIAGRAM ....................................................................................................................................... 5
ꢀ LCD POWER SUPPLY BLOCK DIAGRAM................................................................................................. 6
ꢀ TERMINAL DESCRIPTION 1....................................................................................................................... 7
ꢀ TERMINAL DESCRIPTION 2....................................................................................................................... 8
ꢀ TERMINAL DESCRIPTION 3....................................................................................................................... 9
ꢀ FUNCTIONAL DESCRIPTION ................................................................................................................... 10
(1) MPU INTERFACE......................................................................................................................................... 10
(1-1) Selection of Parallel/Serial Interface Mode .....................................................................................................10
(1-2) Selection of MPU Mode...................................................................................................................................10
(1-3) Data Recognition.............................................................................................................................................10
(1-4) Selection of 3-/4-line Serial Interface Mode ....................................................................................................10
(1-5) 4-line Serial Interface Mode ............................................................................................................................10
(1-6) 3-line Serial Interface Mode ............................................................................................................................11
(1-7) Accessing DDRAM..........................................................................................................................................12
(1-8) Accessing Instruction Register........................................................................................................................13
(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode) ...........................................................................13
(2) INITIAL DISPLAY LINE REGISTER ............................................................................................................. 13
(3) COLUMN AND ROW ADDRESS COUNTERS ............................................................................................ 13
(4) DDRAM......................................................................................................................................................... 14
(4-1) DDRAM Address Range..................................................................................................................................14
(4-2) Window Area for DDRAM Access ...................................................................................................................15
(4-3) Segment Direction...........................................................................................................................................15
(4-4) Bit Assignment of Display Data .......................................................................................................................16
(4-4-1) Bit Assignment Overview ......................................................................................................................................16
(4-4-2) Bit Assignment in Variable 16-grayscale Mode .....................................................................................................17
(4-4-3) Bit Assignment in Variable 8-level Gradation Mode ..............................................................................................20
(4-4-4) Bit Assignment in Fixed 8-level Gradation Mode...................................................................................................21
(4-4-5) Bit Assignment in B&W Mode ...............................................................................................................................25
(4-5) Write Data and Read Data ..............................................................................................................................29
(5) GRAYSCALE CONTROL CIRCUIT.............................................................................................................. 30
(5-1) Display Mode Selection...................................................................................................................................30
(5-1-1) Variable 16-grayscale Mode..................................................................................................................................30
(5-1-2) Variable 8-grayscale Mode....................................................................................................................................30
(5-1-3) Fixed 8-grayscale Mode........................................................................................................................................30
(5-1-4) B&W Mode............................................................................................................................................................30
(6) GRAYSCALE PALETTE................................................................................................................................ 31
(6-1) Grayscale Selection in Variable 16-grayscale Mode.......................................................................................31
(6-2) Grayscale Selection in Variable 8-grayscale Mode.........................................................................................32
(6-3) Grayscale Selection in Fixed 8-grayscale Mode.............................................................................................33
(6-4) Grayscale Selection in B&W Mode .................................................................................................................33
(7) DISPLAY TIMING GENERATOR.................................................................................................................. 34
(8) DATA LATCH CIRCUIT................................................................................................................................. 34
(9) COMMON DRIVERS AND SEGMENT DRIVERS........................................................................................ 34
(10) OSCILLATOR.............................................................................................................................................. 35
(10-1) Using Internal Resistor (CKS=0) ...................................................................................................................35
(10-2) Using External Resistor (CKS=1)..................................................................................................................35
(10-3) Using External Clock (CKS=1) ......................................................................................................................35
(11) LCD POWER SUPPLY................................................................................................................................ 35
Ver.2004-05-12
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NJU6825
(11-1) Voltage Booster .............................................................................................................................................36
(11-2) Voltage Converter..........................................................................................................................................37
(11-2-1)
(11-2-2)
(11-2-3)
(11-2-4)
Reference Voltage Generator ...........................................................................................................................37
Voltage Regulator..............................................................................................................................................37
Electrical Variable Resistor (EVR).....................................................................................................................37
LCD Bias Voltage Generator.............................................................................................................................37
(11-3) External Components for LCD Power Supply ...............................................................................................38
(11-4) Discharge Circuit ...........................................................................................................................................41
(11-5) Power ON/OFF..............................................................................................................................................41
(11-5-1)
(11-5-2)
Power ON/OFF in Using Internal LCD Power Supply .......................................................................................41
Power ON/OFF in Using External LCD Power Supply......................................................................................41
(12) RESET FUNCTION..................................................................................................................................... 42
(13) INSTRUCTION TABLES............................................................................................................................. 43
(13-1) Instruction Table and Register Address.........................................................................................................43
(13-2) Instruction Table 0 (RE2, RE1, RE0)=(0, 0, 0)............................................................................................44
(13-3) Instruction Table 1 (RE2, RE1, RE0)=(0, 0, 1)............................................................................................45
(13-4) Instruction Table 2 (RE2, RE1, RE0)=(0, 1, 0)............................................................................................46
(13-5) Instruction Table 3 (RE2, RE1, RE0)=(0, 1, 1)............................................................................................47
(13-6) Instruction Table 4 (RE2, RE1, RE0)=(1, 0, 0)............................................................................................48
(13-7) Instruction Table 5 (RE2, RE1, RE0)=(1, 0, 1)............................................................................................49
(14) INSTRUCTION DESCRIPTIONS ............................................................................................................... 50
(14-1) Display Data Write.........................................................................................................................................50
(14-2) Display Data Read.........................................................................................................................................50
(14-3) Column Address ............................................................................................................................................50
(14-4) Row Address .................................................................................................................................................50
(14-5) Initial Display Line..........................................................................................................................................50
(14-6) N-line Inversion..............................................................................................................................................51
(14-7) Display Control (1).........................................................................................................................................52
(14-8) Display Control (2).........................................................................................................................................53
(14-9) Increment Control..........................................................................................................................................54
(14-10) Power Control..............................................................................................................................................55
(14-11) Duty Cycle Ratio ..........................................................................................................................................56
(14-12) Boost Level..................................................................................................................................................56
(14-13) LCD Bias Ratio ............................................................................................................................................57
(14-14) Instruction Table Select................................................................................................................................57
(14-15) Palette A / B / C............................................................................................................................................58
(14-16) Initial COM...................................................................................................................................................64
(14-17) Duty-1 /Display Clock ON/OFF....................................................................................................................64
(14-18) Display Mode Control ..................................................................................................................................64
(14-19) Bus Length...................................................................................................................................................65
(14-20) EVR Control.................................................................................................................................................65
(14-21) Frequency Control .......................................................................................................................................66
(14-22) Discharge ON/OFF......................................................................................................................................66
(14-23) Register Address .........................................................................................................................................67
(14-24) Register Read..............................................................................................................................................67
(14-25) Window End Column Address.....................................................................................................................67
(14-26) Window End Row Address ..........................................................................................................................67
(14-27) Initial Line-reverse Address .........................................................................................................................67
(14-28) Last Line-reverse Address...........................................................................................................................68
(14-29) Line Reverse ON/OFF.................................................................................................................................68
(14-30) Upper/Lower Palette Select.........................................................................................................................69
(14-31) PWM Control ...............................................................................................................................................69
(15) PARTIAL DISPLAY FUNCTION.................................................................................................................. 70
(16) SWAP FUNCTION ...................................................................................................................................... 71
(16-1) Swap Function in Variable 16-grayscale Mode .............................................................................................72
(16-2) Swap Function in Variable 8-grayscale Mode ...............................................................................................74
(16-3) Swap Function in Fixed 8-grayscale Mode ...................................................................................................75
(16-4) Swap Function in B&W Mode........................................................................................................................77
(17) RELATION BETWEEN ROW ADDRESS AND COMMON DRIVER.......................................................... 78
Ver.2004-05-12
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NJU6825
(17-1) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/163”..........................................................................79
(17-2) SHIFT=1, Initial Display Line “0”, Duty Cycle Ratio “1/163”..........................................................................80
(17-3) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/16” ............................................................................81
(17-4) SHIFT=0, Initial Display Line “5”, Duty Cycle Ratio “1/163”..........................................................................82
(17-5) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/162”..........................................................................83
(18) TYPICAL INSTRUCTION SEQUENCES.................................................................................................... 84
(18-1) Initialization Sequence in Using Internal LCD Power Supply........................................................................84
(18-2) Initialization Sequence in Using External LCD Power Supply.......................................................................85
(18-3) Display Data Write Sequence........................................................................................................................86
(18-4) Partial Display Sequence ..............................................................................................................................87
(18-5) Power OFF Sequence...................................................................................................................................88
ꢀ ABSOLUTE MAXIMUM RATINGS............................................................................................................. 89
ꢀ RECOMMENDED OPERATING CONDITIONS......................................................................................... 89
ꢀ DC CHARACTERISTICS............................................................................................................................ 90
ꢀ OSCILLATION FREQUENCY AND FRAME FREQUENCY...................................................................... 91
ꢀ AC CHARACTERISTICS............................................................................................................................ 93
(1) Write Operation (Parallel Interface / 80-series MPU)................................................................................... 93
(2) Read Operation (Parallel Interface / 80-series MPU)................................................................................... 94
(3) Write Operation (Parallel Interface / 68-series MPU)................................................................................... 95
(4) Read Operation (Parallel Interface / 68-series MPU)................................................................................... 96
(5) Write Operation (Serial Interface)................................................................................................................. 97
(6) Display Control Timing.................................................................................................................................. 98
(7) Input Clock Timing ........................................................................................................................................ 99
(8) Reset Input Timing........................................................................................................................................ 99
(9) Delay Time of Gate ....................................................................................................................................... 99
ꢀ INPUT/OUTPUT BLOCK DIAGRAMS..................................................................................................... 100
ꢀ MPU CONNECTIONS............................................................................................................................... 101
Ver.2004-05-12
- 4 -
NJU6825
ꢀ BLOCK DIAGRAM
VSSH
VSS
VSSA
VDDA
VDD
Segment Driver
Common Driver
5
VLCD, V1 -V4
Shift Register
VREF
Grayscale Control Circuit
Data Latch Circuit
Grayscale
Palette
(A/B/C)
Voltage
VBA
VREG
Converter
VEE
C1+/C1-
C2+/C2-
C3+/C3-
Voltage
Booster
C4+/C4-
Display Data RAM
(DD RAM)
128x162x(4+4+4)bits
C5+/C5-
C6+/C6-
VOUT
D15
D14
D13
D12
D11
D10
D9
Column Address Decoder
Column Address Counter
Column Address Register
FR
RAM
Interface
Display
Timing
FLM
CL
Generator
CLK
OSC2
OSC1
D8
Oscillator
D7
D6
D5
D4/SPOL
D3/SMODE
D2
Instruction
Decoder
Register Read
Control
Bus Holder
Internal bus
N-line Control
D1/SDA
D0/SCL
MPU Interface
CSb RS
RDb WRb P/S
SEL68 RESb
Ver.2004-05-12
- 5 -
NJU6825
ꢀ LCD POWER SUPPLY BLOCK DIAGRAM
Voltage Converter
LCD Bias Voltage Generator
+
VBA
Reference Voltage Generator
+
VLCD
-
-
Voltage Regulator
VREG
+
-
V1
V2
VREF
+
+
-
-
EVR
Gain
+
-
V3
V4
Control
1/2 VREG
(1x-７x)
+
-
EVR Register
Booster Level Register
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
Voltage Booster
VEE
VOUT
Ver.2004-05-12
- 6 -
NJU6825
ꢀ TERMINAL DESCRIPTION 1
No.
Terminal
VDD
I/O
Function
30~32,
Power
Power Supply for Logic Circuits
GND for Logic Circuits
83-85
50-52,
VSS
Power
Power
120-122
143~145
185~187
VSSH
GND for High Voltage Circuits
VDDA is internally connected to VDD to fix SEL68 or P/S to “H” if necessary, and
cannot be used as main power supply.
58~60
VDDA
Power
Power
• VDDA should be open if not used.
VSSA is internally connected to VSS to fix SEL68 or P/S to “L” if necessary, and
cannot be used as main GND.
16~18,
70~72
VSSA
• VSSA should be open if not used.
LCD Bias Voltages
148-150,
151-153,
155-157,
158-160,
162-164
VLCD
V1
• When the internal LCD power supply is used, internal LCD bias voltages (VLCD
and V1-V4) are activated by the “Power Control” instruction. Stabilizing capacitors
V2
Power
are required between each bias voltage and VSS.
V3
• When the external LCD power supply is used, LCD bias voltages are externally
supplied on VLCD, V1, V2, V3 and V4 individually, with the following relation
maintained: VSSH<V4<V3<V2<V1<VLCD
V4
190-192,
194-196
198-200,
202-204
206-208,
210-212
214-216,
218-220
222-224,
226-228
230-232,
234-236
174-176
170-172
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
C6+
C6-
VBA
VREF
Power
Power
Power
Power
Power
Power
Capacitor Connection for Voltage Booster
Capacitor Connection for Voltage Booster
Capacitor Connection for Voltage Booster
Capacitor Connection for Voltage Booster
Capacitor Connection for Voltage Booster
Capacitor Connection for Voltage Booster
Power
Power
Reference-Voltage Generator Output
Voltage Regulator Input
Voltage Booster Input
180-182
VEE
Power
• VEE is normally connected to VDD
.
Voltage Booster Output
242-244
165-167
39
VOUT
VREG
Power
Power
I
• Input if an external LCD power supply is used.
Voltage Regulator Output
Reset
RESb
• Active “L”
Ver.2004-05-12
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NJU6825
ꢀ TERMINAL DESCRIPTION 2
No.
Terminal
I/O
Function
1. Parallel Interface
D7 to D0 : 8-bit Bi-directional Bus
D0
88
I/O
/SCL
•
In the parallel interface mode (P/S=“H”), D7-D0 are connected to 8-bit
bi-directional MPU bus.
D1
90
94
96
I/O
I/O
I/O
/SDA
Serial Interface
SDA : Serial Data
SCL : Serial Clock
D3
SMODE : 3-/4-line Serial Mode Select
SPOL : RS Polarity Select (3-line Serial Interface Mode)
/SMODE
• In the 3 or 4-line serial interface mode (P/S=“L”), D0 is assigned to SCL, and D1
to SDA.
D4
/SPOL
• In the 3-line serial interface mode, D4 is assigned to SPOL.
• Serial data on SDA is latched at the rising edge of SCL signal in order of D7,
D6,… and D0, and then converted into 8-bit parallel data at the timing of the internal
signal produced from the 8th SCL.
D2
D5
D6
D7
92, 98,
I/O
I/O
100,102
• SCL should be set to “L” right after data transmission or during non-access.
D8
D9
8-bit Bi-directional Bus
D10
D11
D12
D13
D14
D15
104,106,108,
110,112,114,
116,118
• In the 16-bit bus length mode, D15-D8 are assigned to upper 8-bit data bus.
• In the serial interface mode or the 8-bit parallel interface mode, D15-D8 should be
fixed to “H” or “L”.
Chip Select
• Active “L”
43
47
CSb
I
I
Register Select
• This signal interprets transferred data as display data or instruction.
RS
RS
H
L
Data
Instruction
Display Data
80-series MPU Interface (P/S=“H”, SEL68=“L”)
Data Read (RDb) Signal
• Active “L”
79
75
RDb (E)
I
I
68-series MPU Interface (P/S=“H”, SEL68=“H”)
Enable Signal
• Active “H”
80-series MPU Interface (P/S=“H”, SEL68=“L”)
Data Write (WRb) Signal
• Active “L”
68-series MPU Interface (P/S=“H”, SEL68=“H”)
Data Read or Write (R/W) Signal
WRb (R/W)
R/W
H
L
Status
Read
Write
Maker test terminal
24
55
TEST1
TEST2
I
I
This terminal must be fixed to “L” in the user’s application.
Maker test terminal
This terminal must be fixed to “H” in the user’s application.
Ver.2004-05-12
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NJU6825
ꢀ TERMINAL DESCRIPTION 3
No.
Terminal
I/O
Function
MPU Mode Select
67
SEL68
I
SEL86
MPU
H
L
68-series
80-series
Parallel/Serial Interface Mode Select
Chip
Select
CSb
Display /
Instruction
RS
Read
Serial
Clock
-
P/S
Data
/Write
63
P/S
I
H
L
D0 ~ D7
RDb, WRb
CSb
RS
SDA (D1)
Write Only
SCL (D0)
• In the serial interface mode (P/S=“L”), RDb, WRb, D2 and D5-D15 should be fixed
to “H” or “L”,.
Line Clock
124
127
130
133
CL
FLM
FR
O
O
O
O
• CL is normally open.
First Line Maker
• FLM is normally open.
Frame Rate
• FR is normally open.
Clock Output
CLK
• CLK is normally open.
OSC
• When the internal oscillator is used, fix OSC1 to “H” or “L” and leave OSC2 open.
137,
140
OSC1
OSC2
I
To attain more accurate frequency, connect OSC1 and OSC2 with an external
O
resistor.
• When the internal oscillator is not used, input external clock to OSC1 and leave
OSC2 open.
Segment Drivers
REV Register
Normal
OFF
0
1
ON
1
0
Reverse
SEGA0
• Segment drivers output the following voltage levels.
B/W Mode (Example)
~SEGA127
SEGB0
331-714
O
~SEGB127
FR Signal
SEGC0
Display Data
~SEGC127
Reverse Display OFF
V2
VLCD
V2
V3
VSSH
VSSH
V3
(Normal)
Reverse Display ON
Common Drivers
VLCD
• Common drivers output the following voltage levels.
311-330,
260-308,
246-257,
715-734,
737-785,
2-13
Data
H
L
H
L
FR
H
H
L
Output Levels
COM0 ~
COM161
VSSH
V1
VLCD
V4
O
L
NOTE) DUMMY PADs: No. 14, 15, 20-23, 25-29, 33-38, 40-42, 44-46, 48, 49, 53, 54, 56, 57, 61, 62, 64-66, 68, 69, 73, 74,
76-78, 80-82, 86, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 123, 125, 126, 128, 129,
131, 132, 134-136, 138, 139, 141, 142, 146, 147, 154, 161, 168, 169, 173, 177-179, 183, 184, 188, 189, 193, 197, 201,
205, 209, 213, 217, 221, 225, 229, 233, 237-241, 245, 258, 259, 309, 310, 735, 736, and 786.
Ver.2004-05-12
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NJU6825
ꢀ FUNCTIONAL DESCRIPTION
(1) MPU INTERFACE
(1-1) Selection of Parallel/Serial Interface Mode
The P/S selects a parallel or a serial interface mode, as shown in Table 1. In the serial interface mode, neither
display data in the DDRAM nor instruction data in the registers can be read out.
Table 1 Selection of Parallel/Serial Interface Mode
P/S
H
I/F Mode
Parallel I/F
Serial I/F
CSb
CSb
CSb
RS
RS
RS
RDb
RDb
-
WRb
WRb
-
SEL68
SEL68
-
SDA
SDA
SCL
SCL
Data
D7-D0 (D15-D0)
-
L
NOTE) “ -” : Fix to “H” or “L”.
(1-2) Selection of MPU Mode
In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 2.
Table 2 Selection of MPU Mode
SEL68
MPU Mode
68-series MPU
80-series MPU
CSb
CSb
CSb
RS
RS
RS
RDb
E
WRb
R/W
Data
D7-D0 (D15-D0)
D7-D0 (D15-D0)
H
L
RDb
WRb
(1-3) Data Recognition
In the parallel interface mode, the data from MPU is interpreted as display data or instruction according to the
combination of the RS, RDb and WRb (R/W) signals, as shown in Table 3.
Table 3 Data Recognition (Parallel Interface Mode)
68-series
80-series
RS
Function
R/W
H
RDb
L
WRb
H
H
L
H
L
Read Instruction
L
H
Write Instruction
Read Display Data
Write Display Data
H
L
H
H
L
L
L
(1-4) Selection of 3-/4-line Serial Interface Mode
In the serial interface mode, the SMODE selects 3- or 4-line serial interface mode, as shown in Table 4.
Table 4 Selection of 3-/4-line Serial Interface Mode
SMODE
Serial Interface Mode
H
L
3-line
4-line
(1-5) 4-line Serial Interface Mode
While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is inactive
(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.
8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6,…, and D0, and converted
into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The data on the SDA is
interpreted as display data or instruction according to the RS.
Table 5 Data Recognition (4-line Serial Interface)
RS
H
Data Recognition
Instruction
L
Display Data
Ver.2004-05-12
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NJU6825
Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface
is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)
temporary whenever 8-bit data transmission is completed. Fig 1 illustrates the interface timing of the 4-line serial
interface mode.
CSb
RS
VALID
D
SDA
D7
D6
D5
D4
D3
D2
D1
SCL
1
2
3
4
5
6
7
8
Fig 1 4-line Serial Interface Timing
(1-6) 3-line Serial Interface Mode
While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is not active
(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.
9-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of RS, D7, D6,…, and D0, and then
converted into 9-bit parallel data at the timing of the internal signal produced from the 9th SCL signal. The data on the
SDA is interpreted as display data or instruction according to the combination of the RS bit and the SPOL status, as
follows.
Table 6 Data Recognition (3-line Serial Interface)
SPOL=L
SPOL=H
Data Recognition
Instruction
RS
0
Data Recognition
Display Data
Instruction
RS
0
1
1
Display Data
Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface
is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)
temporary whenever 9-bit data transmission is completed. Fig 2 illustrates the interface timing of the 3-line serial
interface mode.
CSb
SDA
SCL
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
Fig 2 3-line Serial Interface Timing
Ver.2004-05-12
- 11 -
NJU6825
(1-7) Accessing DDRAM
While the chip select is active (CSb=“L”), the data from MPU can be written into the DDRAM or the instruction
register. When the RS is “L”, the data is interpreted as display data which is stored in the DDRAM. The display data is
latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of the E signal in the
68-series MPU mode.
Table 7 Data Recognition
RS
L
Data Recognition
Display Data
Instruction
H
In the DDRAM read sequence, be sure to execute a dummy read right after setting an address or right after writing
display data or instruction. The data from MPU is temporarily held in the internal bus-holder, then released on the
internal data-bus, therefore a dummy data is read out by the 1st “Display Data Read” instruction. After that, the display
data is read out from a specified address by the 2nd instruction. Note that the “Display Data Read” instruction cannot be
used in the serial interface mode.
Display Data Write Operation
n
n+1
n+2
n+3
n+4
D0 to D15
WRb
Bus Holder
WRb
n
n+1
n+2
n+3
n+4
Display Data Read Operation
WRb
D0 to D7 (D0 to D15)
n
n
n+1
n+2
Address Set
n
Dummy
Read
Data Read
n Address
Data Read
Data Read
n+1 Address
n+2 Address
RDb
Fig 3 Internal-signal Timing of Display Data Read/Write Operations
NOTE) In 16-bit bus length mode, instruction is transmitted to/from instruction register in 16 bits, as well as display data.
Ver.2004-05-12
- 12 -
NJU6825
(1-8) Accessing Instruction Register
Each instruction register has a specific address in between (0H) and (FH), and instruction data is read out from the
register by the “Register Address” and ”Register Read” instructions. For more information, refer to “(14-23) Register
Address” and “(14-24) Register Read”.
WRb
M
m
N
n
D0 to D7
Register Address
Register Read
Register Address
Register Read
RDb
Fig 4 Access Timing of Instruction Register
(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode)
Either 8- or 16-bit bus length is selected by the D0 (WLS) bit of the “Bus Length” instruction. In the 16-bit bus
length mode, instruction as well as display data is transmitted to/from the instruction registers in 16 bits (D15 to D0).
However, only lower 8 bits (D7 to D0) are valid for instruction register access. And only 12 bits are actually stored in the
DDRAM, even though entire 16 bits (D15 to D0) are transmitted for DDRAM access. For more information, refer to
“(4-4) Bit Assignment of Display Data”.
Table 8 Selection of 8-/16-bit Bus Length Mode
WLS
L
Bus Length Mode
8-bit Bus Length
16-bit Bus Length
H
(2) INITIAL DISPLAY LINE REGISTER
The address data in the initial display line register specifies the row address, which corresponds to an initial COM
and is normally positioned on top of a screen in full display. The initial COM is the start position of common scanning,
which is specified by the “Initial COM” instruction.
The row address, which is established in the initial display line register, is preset into the line counter whenever the
FLM becomes “H”. At the rising edge of the CL signal, the line counter is counted-up, then 384-bit display data is
latched into the data latch circuit. At the falling edge of the CL signal, the latch data is released to the grayscale control
circuit to decide a grayscale level, then the segment drivers Ai, Bi and Ci (i=0 to 127) generate LCD waveforms.
(3) COLUMN AND ROW ADDRESS COUNTERS
The column and row address counters designate a column address and a row address respectively for DDRAM
access, but they are completely independent from the line counter. The line counter provides a line address which is
synchronized with display control timings such as the FLM and the CL.
Ver.2004-05-12
- 13 -
NJU6825
(4) DDRAM
(4-1) DDRAM Address Range
The DDRAM is capable of 162 bits for row address and 1,536 bits (12-bit
x 128-segment) for column address. The
range of the column address is varied depending on the settings as follows, and the row address is from (00H) to (A1H).
Setting outside these ranges is not allowed, otherwise it may cause malfunctions. For DDRAM access, two data
transmissions are needed for 1 RGB-pixel in the 8-bit bus length mode, and one transmission in the 16-bit bus length
mode.
8-bit Bus Length
Column Address
00H
00H 7 bits
01H
5 bits
--------------------------------------------------
FEH
7 bits
FFH
5 bits
:
:
:
:
Row Address
A1H 7 bits
5 bits
7 bits
5 bits
Column Address
00H
01H
--------------------------------------------------
FEH
FFH
ABS=”1”
00H 4 bits
8 bits
4 bits
8 bits
:
:
Row Address
:
:
A1H 4 bits
8 bits
4 bits
8 bits
Column Address
HSW=”1”
00H
01H
--------------------------------------------------
BEH
BFH
00H 8 bits
8 bits
8 bits
8 bits
:
:
Row Address
:
:
A1H 8 bits
8 bits
8 bits
8 bits
Column Address
C256=”1”
00H
01H
--------------------------------------------------
7EH
7FH
00H 8 bits
8 bits
8 bits
8 bits
:
:
Row Address
:
:
A1H 8 bits
8 bits
8 bits
8 bits
Fig 5 Range of Column Address in 8-bit Bus Length
16-bit Bus Length
Column Address
00H
12 bits
--------------------------------------------------
7FH
12 bits
00H
:
:
Row Address
:
:
A1H
12 bits
12 bits
Fig 6 Range of Column Address in 16-bit Bus Length
Ver.2004-05-12
- 14 -
NJU6825
(4-2) Window Area for DDRAM Access
In addition to the normal DDRAM access discussed previously, the window area access can be used. This area is set
by the “Increment Control” instruction and the designation of the start point and the end point.
By the “Increment Control”, auto-increment is set for column address and row address individually. Once this mode
is set up, the column address, row address or both are automatically counted up , whenever the DDRAM is accessed.
And, the start point is specified by the “Column Address” and “Row Address” instructions, and the end point by the
“Window End Column Address” and ”Window End Row Address” instructions. For more information, refer to “(14-9)
Increment Control”, “(14-25) Window End Column Address” and “(14-26)Window End Row Address”. The typical
sequence of the window area setting is listed below.
1. Set “1” at D3 (WIN), D1 (AYI) and D0 (AXI) of “Increment Control” instruction.
2. Set start point by “Column Address” and “Row Address” instructions.
3. Set end point by “Window End Column Address” and “Window End Row Address” instructions.
4. Window area is set up, and DDRAM can be accessed.
NOTE) The order of address setting is column address first, then row address.
Column Address
Start Point
(AX, AY)
Window Area
End Point
(EX, EY)
Whole DDRAM Area
Fig 7 Window Area
NOTE1) The following relation should be maintained to avoid malfunctions.
- AX (Window Start Column Address) < EX (Window End Column Address) < Maximum Column Address
- AY (Window Start Row Address) < EY (Window End Row Address) < Maximum Row Address
NOTE3) Auto-increment in the window area
Start
End
Start
End
Ad d r e ss
Ad d r e ss
Address
Address
Column Address
Row Address
NOTE2) A read-modify-write operation is enabled by setting “1” at the D2 (AIM) of the “Increment Control” instruction. Refer to
the description about “AIM” bit in “(14-9) Increment Control”.
(4-3) Segment Direction
The DDRAM access direction is controlled by the D0 (REF) bit of the “Display Control (2)” instruction. This
function is used to reverse the segment direction for reducing the restrictions on the IC position of an LCD module.
Ver.2004-05-12
- 15 -
NJU6825
(4-4) Bit Assignment of Display Data
(4-4-1) Bit Assignment Overview
These maps is used for grasping general outlines of the variations in the bit assignment of display data.
C256
REF
C256
REF
HSW
ABS
HSW
ABS
SWAP
SWAP
WLS
Mode
WLS
Mode
16bit
8bit
8 bit
Ver.2004-05-12
- 16 -
NJU6825
(4-4-2) Bit Assignment in Variable 16-grayscale Mode
16-bit Bus Length (MON=0, PWM=0, C256=0, WLS=1)
HSW
*
*
ABS
0
0
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
*
*
ABS
0
0
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
HSW
*
*
ABS
1
1
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
ABS
1
1
REF
0
1
SWAP
Column Address / Display Data / Segment Driver
*
1
X=00H
X=7FH
X=7FH
X=00H
←→
←→
*
0
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
Ver.2004-05-12
- 17 -
NJU6825
8-bit Bus Length
(MON=0, PWM=0, C256=0, WLS=0)
HSW
0
0
ABS
0
0
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
0
0
ABS
0
0
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
SEGC0
HSW
0
0
ABS
1
1
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
0
0
ABS
1
1
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
Ver.2004-05-12
- 18 -
NJU6825
HSW
1
ABS
*
REF
0
SWAP
0
Column Address / Display Data / Segment Driver
X=01H
X=00H
X=BDH
X=02H
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA1
Palette B
SEGB1
Palette C
SEGC1
…
…
Column Address / Display Data / Segment Driver
X=BEH
…
…
X=BFH
…
…
Palette A
SEGA126
Palette B
SEGB126
Palette C
SEGC126
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
HSW
1
ABS
*
REF
0
SWAP
1
Column Address / Display Data / Segment Driver
X=01H
X=00H
X=BDH
X=02H
X=BFH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC1
Palette B
SEGB1
Palette C
SEGA1
…
…
Column Address / Display Data / Segment Driver
X=BEH
…
…
…
…
Palette A
SEGC126
Palette B
SEGB126
Palette C
SEGA126
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
HSW
1
ABS
*
REF
1
SWAP
0
Column Address / Display Data / Segment Driver
X=BFH X=BDH
X=BEH
X=BEH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC1
Palette B
SEGB1
Palette C
SEGA1
…
…
Column Address / Display Data / Segment Driver
X=02H X=00H
…
…
X=01H
X=01H
…
…
Palette A
SEGC126
Palette B
SEGB126
Palette C
SEGA126
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
HSW
1
ABS
*
REF
1
SWAP
1
Column Address / Display Data / Segment Driver
X=BFH X=BDH
X=BEH
X=BEH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA1
Palette B
SEGB1
Palette C
SEGC1
…
…
Column Address / Display Data / Segment Driver
X=02H X=00H
…
…
X=01H
X=01H
…
…
Palette A
SEGA126
Palette B
SEGB126
Palette C
SEGC126
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
Ver.2004-05-12
- 19 -
NJU6825
(4-4-3) Bit Assignment in Variable 8-level Gradation Mode
8-bit Bus Length
(MON=0, PWM=0, C256=1, WLS=0)
HSW
*
*
ABS
*
*
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
*
*
ABS
*
*
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
Ver.2004-05-12
- 20 -
NJU6825
(4-4-4) Bit Assignment in Fixed 8-level Gradation Mode
16-bit Bus Length (MON=0, PWM=1, C256=0, WLS=1)
HSW
*
*
ABS
0
0
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
*
*
ABS
0
0
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
NOTE) The data indicated with a slash mark ( / ) is invalid.
HSW
*
*
ABS
1
1
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
*
*
ABS
1
1
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
NOTE) The data indicated with a slash mark ( / ) is invalid.
Ver.2004-05-12
- 21 -
NJU6825
8-bit Bus Length
(MON=0, PWM=1, C256=0, WLS=0)
HSW
0
0
ABS
0
0
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
0
0
ABS
0
0
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
NOTE) The data indicated with a slash mark ( / ) is invalid.
HSW
0
0
ABS
1
1
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
0
0
ABS
1
1
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
NOTE) The data indicated with a slash mark ( / ) is invalid.
Ver.2004-05-12
- 22 -
NJU6825
HSW
1
ABS
*
REF
0
SWAP
0
Column Address / Display Data / Segment Driver
X=01H
X=00H
X=BDH
X=02H
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA1
Palette B
SEGB1
Palette C
SEGC1
…
…
Column Address / Display Data / Segment Driver
X=BEH
…
…
X=BFH
…
…
Palette A
SEGA126
Palette B
SEGB126
Palette C
SEGC126
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
HSW
1
ABS
*
REF
0
SWAP
1
Column Address / Display Data / Segment Driver
X=01H
X=00H
X=BDH
X=02H
X=BFH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC1
Palette B
SEGB1
Palette C
SEGA1
…
…
Column Address / Display Data / Segment Driver
X=BEH
…
…
…
…
Palette A
SEGC126
Palette B
SEGB126
Palette C
SEGA126
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
HSW
1
ABS
*
REF
1
SWAP
0
Column Address / Display Data / Segment Driver
X=BFH X=BDH
X=BEH
X=BEH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC1
Palette B
SEGB1
Palette C
SEGA1
…
…
Column Address / Display Data / Segment Driver
X=02H X=00H
…
…
X=01H
X=01H
…
…
Palette A
SEGC126
Palette B
SEGB126
Palette C
SEGA126
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
HSW
1
ABS
*
REF
1
SWAP
1
Column Address / Display Data / Segment Driver
X=BFH X=BDH
X=BEH
X=BEH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA1
Palette B
SEGB1
Palette C
SEGC1
…
…
Column Address / Display Data / Segment Driver
X=02H X=00H
…
…
X=01H
X=01H
…
…
Palette A
SEGA126
Palette B
SEGB126
Palette C
SEGC126
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
Ver.2004-05-12
- 23 -
NJU6825
8-bit Bus Length
(MON=0, PWM=1, C256=1, WLS=0)
HSW
*
*
ABS
*
*
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
*
*
ABS
*
*
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
Ver.2004-05-12
- 24 -
NJU6825
(4-4-5) Bit Assignment in B&W Mode
16-bit Bus Length (MON=1, PWM=*, C256=0, WLS=1)
HSW
*
*
ABS
0
0
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
*
*
ABS
0
0
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
HSW
*
*
ABS
1
1
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
ABS
1
1
REF
0
1
SWAP
Column Address / Display Data / Segment Driver
*
1
X=00H
X=7FH
X=7FH
X=00H
←→
←→
*
0
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.
Ver.2004-05-12
- 25 -
NJU6825
8-bit Bus Length
(MON=1, PWM=*, C256=0, WLS=0)
HSW
0
0
ABS
0
0
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
0
0
ABS
0
0
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
SEGC0
HSW
ABS
1
1
REF
0
1
SWAP
Column Address / Display Data / Segment Driver
0
0
X=00H
X=FEH
X=01H
X=FEH
X=FFH
X=01H
←→
0
1
X=FFH
X=00H
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
0
0
ABS
1
1
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=FEH
X=01H
X=FFH
X=FEH
X=00H
X=FFH
X=01H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.
Ver.2004-05-12
- 26 -
NJU6825
HSW
1
ABS
*
REF
0
SWAP
0
Column Address / Display Data / Segment Driver
X=01H
X=00H
X=BDH
X=02H
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA1
Palette B
SEGB1
Palette C
SEGC1
…
…
Column Address / Display Data / Segment Driver
X=BEH
…
…
X=BFH
…
…
Palette A
SEGA126
Palette B
SEGB126
Palette C
SEGC126
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
HSW
1
ABS
*
REF
0
SWAP
1
Column Address / Display Data / Segment Driver
X=01H
X=00H
X=BDH
X=02H
X=BFH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC1
Palette B
SEGB1
Palette C
SEGA1
…
…
Column Address / Display Data / Segment Driver
X=BEH
…
…
…
…
Palette A
SEGC126
Palette B
SEGB126
Palette C
SEGA126
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
HSW
1
ABS
*
REF
1
SWAP
0
Column Address / Display Data / Segment Driver
X=BFH X=BDH
X=BEH
X=BEH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC1
Palette B
SEGB1
Palette C
SEGA1
…
…
Column Address / Display Data / Segment Driver
X=02H X=00H
…
…
X=01H
X=01H
…
…
Palette A
SEGC126
Palette B
SEGB126
Palette C
SEGA126
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
HSW
1
ABS
*
REF
1
SWAP
1
Column Address / Display Data / Segment Driver
X=BFH X=BDH
X=BEH
X=BEH
…
…
Display Data in DDRAM
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA1
Palette B
SEGB1
Palette C
SEGC1
…
…
Column Address / Display Data / Segment Driver
X=02H X=00H
…
…
X=01H
X=01H
…
…
Palette A
SEGA126
Palette B
SEGB126
Palette C
SEGC126
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.
Ver.2004-05-12
- 27 -
NJU6825
8-bit Bus Length
(MON=1, PWM=*, C256=1, WLS=0)
HSW
*
*
ABS
*
*
REF
0
1
SWAP
0
1
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGA0
Palette B
SEGB0
Palette C
SEGC0
Palette A
SEGA127
Palette B
SEGB127
Palette C
SEGC127
←→
←→
HSW
*
*
ABS
*
*
REF
0
1
SWAP
1
0
Column Address / Display Data / Segment Driver
X=00H
X=7FH
X=7FH
X=00H
←→
←→
Display Data in DDRAM
←→
Grayscale Palette
Segment Driver
Palette A
SEGC0
Palette B
SEGB0
Palette C
SEGA0
Palette A
SEGC127
Palette B
SEGB127
Palette C
SEGA127
←→
←→
NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.
Ver.2004-05-12
- 28 -
NJU6825
(4-5) Write Data and Read Data
16-bit Bus Length
ABS=0
Write Data
D15
↓
D14
D14
D13
D13
D12
D12
D11
*
D10
D10
D9
D9
D8
D8
D7
D7
D6
*
D5
*
D4
D4
D3
D3
D2
D2
D1
D1
D0
↓
Read Data
D15
*
ABS=1
Write Data
Read Data
D15
↓
D14
*
D13
*
D12
*
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
↓
*
D0
8-bit Bus Length
ABS=0, HSW=0, C256=0 (Column Address: 00H, 02H, …FCH, FEH)
Write Data
Read Data
D7
↓
D6
D5
D4
D3
D2
D1
D0
↓
D7
D6
D5
D4
*
D2
D1
D0
ABS=0, HSW=0, C256=0 (Column Address: 01H, 03H, …FDH, FFH)
Write Data
Read Data
D7
↓
D6
D5
D4
D3
D2
D1
D0
↓
D7
*
*
D4
D3
D2
D1
*
ABS=1, HSW=0, C256=0 (Column Address: 00H, 02H, …FCH, FEH)
Write Data
Read Data
D7
↓
D6
D5
D4
D3
D2
D1
D0
↓
*
*
*
*
D3
D2
D1
D0
ABS=1, HSW=0, C256=0 (Column Address: 01H, 03H, …FDH, FFH)
Write Data
Read Data
D7
↓
D6
D5
D4
D3
D2
D1
D0
↓
D7
D6
D5
D4
D3
D2
D1
D0
ABS=0, HSW=1, C256=0 (Column Address: 00H, 01H, …BEH, BFH)
Write Data
Read Data
D7
↓
D6
D5
D4
D3
D2
D1
D0
↓
D7
D6
D5
D4
D3
D2
D1
D0
ABS=0, HSW=0, C256=1 (Column Address: 00H, 01H, …7EH, 7FH)
Write Data
Read Data
D7
↓
D6
D5
D4
D3
D2
D1
D0
↓
D7
D6
D5
D4
D3
D2
D1
D0
NOTE) * : Invalid Data
Ver.2004-05-12
- 29 -
NJU6825
(5) GRAYSCALE CONTROL CIRCUIT
(5-1) Display Mode Selection
A display mode is selected by the combination of the D2 (MON) bit of the “Display Control (1)” instruction and the
D3 (PWM) and D2 (C256) bits of the “Display Mode Control” instruction, as shown below.
Table 11 Display Mode Selection
C256
Oscillation
(NOTE2)
MON
PWM
Display Mode
Bus Length
(NOTE1)
0
1
0
1
0
1
Variable 16-grayscale Mode
Variable 8-grayscale Mode
4096 Colors
256 Colors
8-/16-bit
(WLS=0/1)
(WLS=0)
(WLS=0/1)
(WLS=0)
0
1
*
fOSC1
fOSC2
fOSC3
8-bit
8-/16-bit
8-bit
0
1
Fixed 8-grayscale Mode
256 Colors
8-/16-bit
8-bit
(WLS=0/1)
(WLS=0)
B&W Mode
Black & White
NOTE1) In the variable grayscale mode, “C256” bit selects either 16-grayscale (4K colors) or 8-grayscale (256 colors). When
C256=”0” (16-grayscale), all 12 bits are assigned to 1 RGB-pixel. When C256=”1” (8-grayscale), only 8 bits are
assigned and the 8-bit bus length should be used. In the fixed 8-grayscale mode or the B&W mode, the “C256” bit is
usually “1”. For more information how the display data is assigned, refer to “(4-4) Bit Assignment of Display Data”.
NOTE2)Oscillation frequency is decided according to the display mode, and is fine-tuned by the “Frequency Control” Instruction.
Refer to “(10) OSCILLATOR” and “OSCILLATION FREQUENCY AND FRAME FREQUENCY”.
(5-1-1) Variable 16-grayscale Mode
In this mode, each of the palettes Aj, Bj and Cj (j=0-15) is capable of selecting 16 from 32 grayscales (0/31-31/31)
by setting palette data in the grayscale palette. Then, each of the segment drivers SEGAi, SEGBi and SEGCi (i=0 to 127)
generates 16 grayscales to achieve 4,096 colors. Refer to Table 12-1 and Table 12-2.
(5-1-2) Variable 8-grayscale Mode
Each of the palettes Aj, Bj and Cj (j=0-15) is capable of selecting 8 from 32 grayscales (0/31-31/31). 2 segment
drivers of 1 RGB-group (SEGAi, SEGBi and SEGCi (i=0 to 127)) generate 8 grayscales, and the other driver does 4
grayscales to achieve 256 colors. Refer to Table 13-1 through Table 13-4. The 8-bit bus length is usually used in this
mode.
(5-1-3) Fixed 8-grayscale Mode
The palette setting is not necessary, because the palettes Aj, Bj and Cj (j=0-15) are always fixed at 4 or 8 grayscales
between 0/7 and 7/7. 2 segment drivers of 1 RGB-group (SEGAi, SEGBi and SEGCi (i=0 to 127)) are fixed at 8
grayscales, and the other driver is 4 grayscales, then results in 256 colors. Refer to Table 14-1 and Table 14-2.
(5-1-4) B&W Mode
The palette setting is not necessary, where the only MSB bits of display data are valid. Refer to Table 15.
Ver.2004-05-12
- 30 -
NJU6825
(6) GRAYSCALE PALETTE
(6-1) Grayscale Selection in Variable 16-grayscale Mode
Table 12-1 Grayscale selection
Table 12-2 Grayscale Palette
( Palette Aj, Bj, and Cj )
( Palette Aj, Bj, and Cj )
Display Data
Palette Name
MSB----LSB
Palette Data
Palette Data
MSB---LSB
Grayscale
Default Setting
Grayscale
Default Setting
MSB---LSB
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Palette A0/B0/C0
Palette A1/B1/C1
Palette A2/B2/C2
Palette A3/B3/C3
Palette A4/B4/C4
Palette A5/B5/C5
Palette A6/B6/C6
Palette A7/B7/C7
Palette A8/B8/C8
Palette A9/B9/C9
Palette A10/B10/C10
Palette A11/B11/C11
Palette A12/B12/C12
Palette A13/B13/C13
Palette A14/B14/C14
Palette A15/B15/C15
0
Palette A0/B0/C0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Palette A8/B8/C8
Palette A1/B1/C1
Palette A2/B2/C2
Palette A3/B3/C3
Palette A4/B4/C4
Palette A5/B5/C5
Palette A6/B6/C6
Palette A7/B7/C7
Palette A9/B9/C9
Palette A10/B10/C10
Palette A11/B11/C11
Palette A12/B12/C12
Palette A13/B13/C13
Palette A14/B14/C14
Palette A15/B15/C15
NOTE1) “MON=0”, “PWM=0”, “C256=0”
NOTE2) Applied to palette Aj, Bj and Cj (j=0 to 15)
Ver.2004-05-12
- 31 -
NJU6825
(6-2) Grayscale Selection in Variable 8-grayscale Mode
Table 13-1 Grayscale selection
Table 13-2 Grayscale Palette
( Palette Aj and Bj )
( Palette Aj and Bj )
Display Data
Palette Name
MSB----LSB
Palette Data
Palette Data
MSB---LSB
Grayscale
Default Setting
Grayscale
Default Setting
MSB---LSB
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
0 0 0 *
0 0 1 *
0 1 0 *
0 1 1 *
1 0 0 *
1 0 1 *
1 1 0 *
1 1 1 *
Palette A1/B1/C1
Palette A3/B3/C3
Palette A5/B5/C5
Palette A7/B7/C7
Palette A9/B9/C9
Palette A11/B11/C11
Palette A13/B13/C13
Palette A15/B15/C15
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Palette A1/B1/C1
Palette A3/B3/C3
Palette A5/B5/C5
Palette A7/B7/C7
Palette A9/B9/C9
Palette A11/B11/C11
Palette A13/B13/C13
Palette A15/B15/C15
NOTE1) “MON=0”, “PWM=0”, “C256=1”.
NOTE2) Applied to palette Aj and Bj (j=0 to 15)
NOTE3) Palette 0, 2, 4, 6, 8, 10, 12 and 14 are disabled.
Table 13-3 Grayscale selection
Table 13-4 Grayscale Palette
( Palette Cj )
( Palette Cj )
Display Data
Palette Name
MSB----LSB
Palette Data
Palette Data
MSB---LSB
Grayscale
Default Setting
Grayscale
Default Setting
MSB---LSB
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
0 0 * *
0 1 * *
1 0 * *
1 1 * *
Palette A3/B3/C3
Palette A7/B7/C7
Palette A3/B3/C3
Palette A7/B7/C7
Palette A11/B11/C11
Palette A15/B15/C15
Palette A11/B11/C11
Palette A15/B15/C15
NOTE1) “MON=0”, “PWM=0”, “C256=1”
NOTE2) Applied to palette Cj (j=0 to 15)
NOTE3) Palette 0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13 and 14 are disabled.
Ver.2004-05-12
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NJU6825
(6-3) Grayscale Selection in Fixed 8-grayscale Mode
Table 14-1 Grayscale Selection
Table 14-2 Grayscale Palette
( Palette Aj and Bj )
( Palette Cj )
Display Data
Display Data
Grayscale
Grayscale
0/7
MSB- - - -LSB
MSB- - - -LSB
0 0 0 *
0 0 1 *
0 1 0 *
0 1 1 *
1 0 0 *
1 0 1 *
1 1 0 *
1 1 1 *
0/7
1/7
2/7
3/7
4/7
5/7
6/7
7/7
0 0 * *
0 1 * *
1 0 * *
1 1 * *
3/7
5/7
7/7
NOTE1) “MON=0”, “PWM=1”, “C256=0 or 1”
(6-4) Grayscale Selection in B&W Mode
Table 15 Grayscale Selection
Display Data
Grayscale
MSB- - - -LSB
0 * * *
1 * * *
0
1
NOTE1) “MON=1”, “PWM=0 or 1” and “C256=0 or 1”
Ver.2004-05-12
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NJU6825
(7) DISPLAY TIMING GENERATOR
The display timing generator generates timing clocks such as the CL (Line Clock), FR (Frame Rate) and FLM (First
Line Maker) by dividing an oscillation frequency. These clocks are used inside the LSI, and are activated by setting “1”
at the D0 (SON) bit of the “Duty-1 /Display Clock ON/OFF” instruction.
The CL is used for the line counter and the data latch circuit. At the rising edge of the CL signal, the line counter is
counted up, then 384-bit display data is latched into the data latch circuit. At the falling edge of the CL signal, the latch
data is released to the grayscale control circuit, then segment drivers Ai, Bi and Ci (i=0 to 127) produce LCD driving
waveforms. The internal data-transmission timing between the DDRAM and segment drivers is completely independent
of external data-transmission timing, so that MPU makes access to the LSI without concern for the LSI’s internal
operation.
The FR and FLM are generated by the CL. The FR toggles once every frame in the default status, and is
programmed to toggle once every N lines. And the FLM is used to specify an initial display line, which is preset
whenever the FLM becomes “H”.
(8) DATA LATCH CIRCUIT
The data latch circuit is used to temporarily store display data which is released to the grayscale control circuit. The
display data in this circuit is updated in synchronization with the CL. The “All Pixels ON/OFF”, “Display ON/OFF” and
“Reverse Display ON/OFF” instructions control the data in this circuit, but does not change the data in the DDRAM.
(9) COMMON DRIVERS AND SEGMENT DRIVERS
The LSI includes 162-common drivers and 384-segment drivers. The common drivers generate LCD driving
waveforms formed on the VLCD, V1, V4 and VSSH levels. The segment drivers generate waveforms formed on the VLCD
V2, V3 and VSSH levels.
,
COM0
163
1
2
3
4
5
163
1
2
3
4
5
163 1
COM1
CL
SEG0
SEG2
SEG1
FLM
FR
VLCD
V1
V2
V3
COM0
V4
VSSH
VLCD
V1
V2
V3
V4
VSSH
COM1
SEG0
VLCD
V1
V2
V3
V4
VSSH
VLCD
V1
V2
SEG1
V3
V4
VSSH
Fig 8 LCD Driving Waveforms (B&W Mode, Color Reverse OFF, 1/163 Duty)
Ver.2004-05-12
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NJU6825
(10) OSCILLATOR
The oscillator is equipped with a resistor and a capacitor, and generates internal clocks used for the display timing
generator and the voltage booster. The internal resistor is enabled by setting “0” at the D1 (CKS) bit of the “Bus Length”
instruction. For more accurate frequency, using an external resistor or external clock is recommended.
When using the internal resistor, the resistance is controlled to optimize frame frequency for different LCD panels,
by setting the D2-D0 (RF2-RF0) bits of the “Frequency Control” instruction. For more safety, make sure what is the best
frequency in the particular application.
(10-1) Using Internal Resistor (CKS=0)
In this case, the OSC1 should be fixed at “H” or “L” and the OSC2 is open. The oscillation frequency is varied
according to the display mode, as follows.
Table 16 Oscillation Frequency vs. Display Mode
Symbol
fOSC1
MON
PWM
Display Mode
Variable 8-/16-grayscale Mode
Fixed 8-grayscale Mode
B&W Mode
0
0
1
0
1
*
fOSC2
fOSC3
*: Don’t care
(10-2) Using External Resistor (CKS=1)
Be sure to connect the OSC1 and OSC2 with an external resistor. The frequency of the oscillator should be adjusted
to the same value generated by the internal resistor.
(10-3) Using External Clock (CKS=1)
Input external clock to the OSC1 and leave the OSC2 open. The external clock with 50% duty is recommended. The
frequency of the external clock should be the same value generated by the internal resistor.
(11) LCD POWER SUPPLY
The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage
converter consists of the reference voltage generator, the voltage regulator with EVR and the LCD bias voltage generator.
The configuration of the LCD power supply is arranged by setting the D3 (AMPON) and D1 (DCON) bits of the “Power
Control” instruction. For this configuration, the internal LCD power supply can be partially used in combination with an
external supply voltage, as shown in Table 17.
Table 17 Configuration of LCD Power Supply
DCON
AMPON
Voltage Booster
Voltage Converter
External Supply Voltage
NOTE
0
0
1
0
1
1
Inactive
Inactive
Active
Inactive
Active
Active
VOUT, VLCD, V1, V2, V3, V4
1, 3, 4
2, 3, 4
-
VOUT
−
NOTE1) No internal LCD power supply is used. The LCD bias voltages are externally supplied, and the C1+, C1-, C2+, C2-, C3+,
C3-, C4+, C4-, C5+, C5-, C6+, C6-, VREF, VREG and VEE are open.
NOTE2) Only the voltage converter is used. The VOUT is externally supplied, and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+,
C5-, C6+, C6-, and VEE are open. The reference voltage is supplied on the VREF
.
NOTE3) The following relation among each LCD bias voltages must be maintained.
VOUT ≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSSH
NOTE4) If the internal LCD power supply doesn’t have enough capability to drive the particular LCD panel, use the external
LCD power supply. Otherwise, it may affect display quality.
Ver.2004-05-12
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NJU6825
(11-1) Voltage Booster
The internal voltage booster generates up to 7xVEE voltage. The boost level is selected from 2x, 3x, 4x, 5x, 6xor7x
by setting the D2-D0 (VU2-VU0) bits of the “Boost Level” instruction. The boost voltage VOUT must not exceed 18.0V,
otherwise the voltage stress may cause a permanent damage to the LSI.
VOUT=17.5V
VOUT=9V
VEE=2.5V
VSSH=0V
VEE=3V
VSSH=0V
3-time Boost
7-time Boost
Fig 9 Boost Voltage
5-time Boost
6-time Boost
7-time Boost
C1+
C1-
C1+
C1-
C1+
C1-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
C2+
C2-
C2+
C2-
C2+
C2-
C3+
C3-
C3+
C3-
C3+
C3-
C4+
C4-
C4+
C4-
C4+
C4-
C5+
C5-
C5+
C5-
C5+
C5-
C6+
C6-
C6+
C6-
C6+
C6-
+
+
+
VOUT
VOUT
VOUT
4-time Boost
3-time Boost
2-time Boost
C1+
C1-
C1+
C1-
C1+
C1-
+
+
+
+
+
C2+
C2-
C2+
C2-
C2+
C2-
C3+
C3-
C3+
C3-
C3+
C3-
C4+
C4-
C4+
C4-
C4+
C4-
C5+
C5-
C5+
C5-
C5+
C5-
C6+
C6-
C6+
C6-
C6+
C6-
VOUT
VOUT
VOUT
+
+
Fig 10 External Capacitor Connection of Voltage Booster
Ver.2004-05-12
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NJU6825
(11-2) Voltage Converter
(11-2-1) Reference Voltage Generator
The reference voltage generator produces the reference voltage (VBA=0.9xVEE). When using the internal LCD
power supply, connect the VBA and the VREF, or supply 0.9xVEE or lower voltage on the VREF. When using an external
LCD power supply, the VBA should be open.
(11-2-2) Voltage Regulator
The voltage regulator consists of an operational amplifier with gain control and EVR. The VREF voltage is
multiplied to obtain the VREG voltage, and its multiple (boost level) is set by the D2-D0 (VU2-VU0) bits of the “Boost
Level” instruction. The formula is shown below.
VREG = VREF
x
N
(N: Boost Level)
(11-2-3) Electrical Variable Resistor (EVR)
The EVR is used to fine-tune the VLCD voltage to optimize display contrast. The EVR value is controlled in 128
steps by setting the D3-D0 (DV6-DV0) bits of the “EVR Control” instruction. The formula is shown below.
VLCD = 0.5
x
VREG + M (VREG - 0.5
x
VREG) / 127
(M: EVR Value)
(11-2-4) LCD Bias Voltage Generator
The LCD bias voltage generator consists of buffer amplifiers and bleeder resistors to generate the LCD bias
voltages such as the VLCD, V1, V2, V3 and V4, and its bias ratio is selected from1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11 or 1/12.
As shown in Fig 11, when using only the internal LCD power supply, the capacitors CA2 are connected to the VLCD
V1, V2, V3 and V4 respectively.
,
As shown in Fig 12, when using no internal LCD power supply, the LCD bias voltages are externally supplied on
the VLCD, V1, V2, V3 and V4, and the internal LCD power supply should be turned off by setting “0” at the “DCON” and
“AMPON” bits. And the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6-, VEE, VREF and VREG are open.
Fig 13 and 14 show typical peripheral circuits when partially using the LCD power supply without the reference
voltage generator.
Fig 15 shows the circuit when partially using the LCD power supply without the voltage booster.
Ver.2004-05-12
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NJU6825
(11-3) External Components for LCD Power Supply
Using Only Internal LCD Power Supply (7x boost)
Using Only External LCD Power Supply
VDD
VDD
VDD
VDD
VEE
CA1
VEE
CA1
VBA
VBA
VREF
VREF
VREG
CA3
VREG
CA3
C1-
C1-
CA1
C1+
C1+
C2-
C2-
CA1
C2+
C2+
C3-
C3-
CA1
C3+
C3+
C4-
C4-
CA1
C4+
C4+
C5-
C5-
CA1
C5+
C5+
C6-
C６-
CA1
C６+
C6+
VOUT
VOUT
CA1
CA1
VLCD
V1
VLCD
V1
CA2
CA2
CA2
CA2
CA2
VLCD
External V1
Power V2
Circuit V3
V4
V2
V2
V3
V3
V4
V4
CA2 CA2 CA2 CA2
Fig 11
Fig 12
Reference Values
CA1
CA2
CA3
1.0 to 4.7µF
1.0 to 2.2µF
0.1µF
NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular
application.
NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up
efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this
impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.
Ver.2004-05-12
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NJU6825
Using Internal LCD Power Supply
Without Reference Voltage generator (2)
Using Internal LCD Power Supply
Without Reference Voltage generator (1)
(7x boost)
(7x boost)
VDD
VDD
VDD
VEE
VDD
VEE
CA1
CA1
VBA
VBA
VREF
VREG
VREF
VREG
CA3
CA3
CA1
CA1
CA1
CA1
CA1
CA1
C1-
C1-
CA1
C1+
C2-
C1+
C2-
CA1
C2+
C3-
C2+
C3-
CA1
C3+
C4-
C3+
C4-
CA1
C4+
C5-
C4+
C5-
CA1
C5+
C6-
C5+
C6-
CA1
C6+
VOUT
C6+
VOUT
CA1
CA1
VLCD
V1
VLCD
CA2
CA2
CA2
CA2
CA2
CA2
V1
CA2
V2
CA2
CA2
CA2
V2
V3
V4
V3
V4
Fig 13
Fig 14
Reference Values
CA1
CA2
CA3
1.0 to 4.7µF
1.0 to 2.2µF
0.1µF
NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular
application.
NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up
efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this
impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.
Ver.2004-05-12
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NJU6825
Using Internal LCD Power Supply
Without Voltage Booster
VDD
VDD
VEE
CA1
VBA
VREF
VREG
CA3
CA3
C1-
C1+
C2-
C2+
C3-
C3+
C4-
C4+
C5-
C5+
C6-
C6+
VOUT
External
Power
Circuit
CA1
VLCD
V1
CA2
CA2
CA2
CA2
CA2
V2
V3
V4
Fig 15
Reference Values
CA1
CA2
CA3
1.0 to 4.7µF
1.0 to 2.2µF
0.1µF
NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular
application.
NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up
efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this
impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.
Ver.2004-05-12
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NJU6825
(11-4) Discharge Circuit
The LSI incorporates two discharge circuits which are independently controlled for the VLCD and V1-V4 and for the
V
OUT. The VLCD and V1-V4 are discharged by setting "1" at the D0 (DIS) bit of the "Discharge ON/OFF" instruction or
the reset by the RESb. Be sure to turned off the internal or external LCD power supply when this instruction is executed,
otherwise it may function as a current load and affect an operating current. Refer to “(14-22) Discharge ON/OFF”.
(11-5) Power ON/OFF
To protect the LSI from overcurrent, the following sequences must be maintained to turn on and off the power
supply. In addition to the following discussions, refer to “(18) TYPICAL INSTRUCTION SEQUENCES”.
(11-5-1) Power ON/OFF in Using Internal LCD Power Supply
Power ON
First “VDD and VEE ON”, next “Reset by RESb”, then “Internal LCD power supply ON”. Be sure to execute the
“Display ON” instruction later than the completion of this power ON sequence. Otherwise, unexpected pixels may be
turned on instantly.
Power OFF
First “Reset by RESb or “HALT” instruction”, next “VDD and VEE OFF”. If using different power sources for the
VDD and the VEE individually, the VEE must be turned off after the reset or the “HALT”. After that, the VDD can be turned
off, waiting until the LCD bias voltages (VLCD, V1, V2, V3 and V4) drop below the threshold level of LCD pixels.
(11-5-2) Power ON/OFF in Using External LCD Power Supply
Power ON
First “VDD and VEE ON”, next “Reset by RESb”, then “External LCD power supply ON”. When using only external
V
OUT, first “VDD ON”, next “Reset by RESb”, then “External VOUT ON”, as well.
Power OFF
First “Reset by RESb or “HALT” instruction” to isolate external LCD bias voltages, next “VDD OFF”. For more
safety, placing a resistor in series on the VLCD line (or the VOUT line in using only the external VOUT) is recommended.
That resistance is usually between 50Ω and 100Ω.
Ver.2004-05-12
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NJU6825
(12) RESET FUNCTION
The reset function initializes the LSI to the following default status by setting the RESb to “L”. Connecting the
RESb with MPU’s reset is recommended so that the LSI and MPU is initialized at a time.
Default Status
1. Display Data in DDRAM
2. Column Address
3. Row Address
4. Initial Display Line
5. Display ON/OFF
6. Reverse Display ON/OFF
7. Duty Cycle Ratio
8. N-line Inversion ON/OFF
9. COM Scan Direction
10. Increment Control
11. REF
12. Swap
13. EVR Value
14. Internal LCD Power Supply
15. Display Mode
16. LCD Bias Ratio
17. Palette 0
:Undefined
:(00)H
:(00)H
:(0)H (1st line)
:OFF
:OFF (Normal)
:1/163 Duty (DSE=0)
:OFF
:COM0 → COM161
:Auto-increment OFF (AIM, AXI, AYI)=(0, 0, 0)
:REF=0 (Normal)
:OFF (Normal)
:(0, 0, 0, 0, 0, 0, 0)
:OFF
:Grayscale Mode
:1/9 Bias
:(0, 0, 0, 0, 0)
18. Palette 1
:(0, 0, 0, 1, 1)
19. Palette 2
:(0, 0, 1, 0, 1)
20. Palette 3
:(0, 0, 1, 1, 1)
21. Palette 4
:(0, 1, 0, 0, 1)
22. Palette 5
:(0, 1, 0, 1, 1)
23. Palette 6
:(0, 1, 1, 0, 1)
24. Palette 7
:(0, 1, 1, 1, 1)
25. Palette 8
:(1, 0, 0, 0, 1)
26. Palette 9
:(1, 0, 0, 1, 1)
27. Palette 10
:(1, 0, 1, 0, 1)
28. Palette 11
:(1, 0, 1, 1, 1)
29. Palette 12
:(1, 1, 0, 0, 1)
30. Palette 13
:(1, 1, 0, 1, 1)
31. Palette 14
:(1, 1, 1, 0, 1)
32. Palette 15
:(1, 1, 1, 1, 1)
33. Display Mode Control
34. Bus Length
35. Discharge ON/OFF
:Variable 16-grayscale Mode (4,096 Colors)
:8-bit Bus Length
:OFF (DIS)=(0)
Ver.2004-05-12
- 42 -
NJU6825
(13) INSTRUCTION TABLES
(13-1) Instruction Table and Register Address
The LSI incorporates 6 instruction tables as shown in Fig 16, and each instruction table has a specific address in
between “0” and “5”. And each instruction register has a specific address in between (0H) and (FH), and instruction is
read out from the register by the “Register Address” and “Register Read” instructions.
Fig 17 shows part of the instruction sequence, where the instruction table should be specified prior to other
instructions. However, when some instructions of the same table are sequentially executed, the table selection may be
omitted. In addition, the “Display Data Write”, “Display Data Read” and “Register Read” instructions can be performed
in any table.
Table “0”
Table “1”
Table “2”
Table “3”
Table “4”
Table “5”
(RE2,RE1,RE0)=(0,0,0) (RE2,RE1,RE0)=(0,0,1) (RE2,RE1,RE0)=(0,1,0) (RE2,RE1,RE0)=(0,1,1) (RE2,RE1,RE0)=(1,0,0) (RE2,RE1,RE0)=(1,0,1)
Instruction (0H)
Instruction (0H)
Instruction (0H)
Instruction (0H)
Instruction (0H)
Instruction (0H)
Instruction (FH)
Instruction (FH)
Instruction (FH)
Instruction (FH)
Instruction (FH)
Instruction (FH)
NOTE) Address (FH) is assigned to “Instruction Table Select” in any table.
Fig 16 Instruction Table Overview
Optional Status
[RE2:RE0]=[0,0,0]
Instruction Table “0” Select
Instruction 1
Instructions in Table “0”
Instruction 2
Instruction 3
[RE2:RE0]=[1,0,0]
Instruction Table “4” Select
Instruction 4
Instructions in Table “4”
Instruction 5
[RE2:RE0]=[1,0,1]
Instruction in Table “5”
Instruction Table “5” Select
Instruction 6
Optional Status
Fig 17 Outline of Instruction Sequence
Ver.2004-05-12
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NJU6825
(13-2) Instruction Table 0 (RE2, RE1, RE0)=(0, 0, 0)
Code (80 Series MPU I/F)
Code
D4 D3
Instructions/
Functions
Writing Display Data
Register Address [NH]
CSb RS RDb WRb RE2 RE1 RE0
D7
D6
D5
D2
D1
D0
1
2
Display Data Write
Display Data Read
0
0
0
0
1
0
0
1
0/1
0/1
0/1
0/1
0/1
0/1
Write Data
Read Data
Reading Display Data
Column Address
Setting Column Address
for start point
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AX3 AX2 AX1 AX0
AX7 AX6 AX5 AX4
AY3 AY2 AY1 AY0
AY7 AY6 AY5 AY4
(Lower) [0H]
3
4
5
6
Column Address
Row Address
Row Address
Setting Column Address
for start point
(Upper) [1H]
(Lower) [2H]
(Upper) [3H]
Setting Row Address
for start point
Setting Row Address
for start point
Initial Display Line
(Lower) [4H]
Setting Row Address
for Initial COM
LA3
LA7
N3
LA2 LA1 LA0
LA6 LA5 LA4
Initial Display Line
(Upper) [5H]
Setting Row Address
for Initial COM
N-line Inversion
Setting the Number of
N-line Inversion
N2
N6
N1
N5
N0
N4
(Lower) [6H]
(Upper) [7H]
N-line Inversion
Setting the Number of
N-line Inversion
N7
SHIFT
: Common Scan Direction
Display Control (1)
Display Control (2)
Increment Control
Power Control
ALL ON/ MON
: Grayscale/B/W Mode
7
8
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
SHIFT MON
[8H]
[9H]
[AH]
[BH]
ON OFF ALLON : All Pixels ON/OFF
ON/OFF : Display ON/OFF
REV
: Reverse Display ON/OFF
NLIN
SWAP
REF
: N-line Inversion ON/OFF
: SWAP ON/OFF
REV NLIN SWAP REF
: Segment Direction
WIN
AIM
AYI
: Window Area ON/OFF
: Read-Modify-Write ON/OFF
: Row Increment
9
WIN AIM
AYI
AXI
AXI
: Column Increment
AMPON : Voltage Converter ON/OFF
AMP
HALT
ON
DC
ON
HALT
DCON
ACL
: Power Save ON/OFF
: Voltage Booster ON/OFF
: Reset
10
ACL
Duty Cycle Ratio
Boost Level
11
12
13
14
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
DS3 DS2 DS1 DS0 Setting LCD Duty Cycle Ratio
[CH]
[DH]
[EH]
[FH]
*
*
VU2 VU1 VU0 VU2-0
: Setting Boost Level
LCD Bias Ratio
Instruction Table Select
0
0
0
B2
B1
B0 Setting LCD Bias Ratio
0/1
0/1
0/1
TST0 RE2 RE1 RE0 Setting Instruction Table
NOTE1) * : Don’t care.
NOTE2) [NH] (N=0-F) : Register Address
NOTE3) Any nonexistent instruction code is prohibited.
NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.
NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower
byte.
Ver.2004-05-12
- 44 -
NJU6825
(13-3) Instruction Table 1 (RE2, RE1, RE0)=(0, 0, 1)
Code (80 series MPU I/F)
Code
Instructions/
Functions
Register Address [NH]
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
Palette A0/A8
Setting Palette Data :
PA03/ PA02/ PA01/ PA00/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
PA83 PA82
PA81 PA80
(Lower) [0H]
A0(PS=0) /A8(PS=1)
Palette A0/A8
Palette A1/A9
Palette A1/A9
Palette A2/A10
Palette A2/A10
Palette A3/A11
Palette A3/A11
Palette A4/A12
Palette A4/A12
Palette A5/A13
Palette A5/A13
Palette A6/A14
Palette A6/A14
Setting Palette Data :
A0(PS=0) /A8(PS=1)
PA04/
*
*
*
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
PA84
(Upper) [1H]
(Lower) [2H]
(Upper) [3H]
(Lower) [4H]
(Upper) [5H]
(Lower) [6H]
(Upper) [7H]
(Lower) [8H]
(Upper) [9H]
(Lower) [AH]
(Upper) [BH]
(Lower) [CH]
(Upper) [DH]
Setting Palette Data :
A1(PS=0) /A9(PS=1)
PA13/ PA12/ PA11/ PA10/
0
0
1
PA93 PA92
PA91 PA90
Setting Palette Data :
A1(PS=0) /A9(PS=1)
PA14/
*
*
*
0
0
1
PA94
Setting Palette Data :
A2(PS=0) /A10(PS=1)
PA23/ PA22/ PA21/ PA20/
PA103 PA102 PA101 PA100
0
0
1
Setting Palette Data :
A2(PS=0) /A10(PS=1)
PA24/
*
*
*
0
0
1
PA104
Setting Palette Data :
A3(PS=0) /A11(PS=1)
PA33/ PA32/P PA31/ PA30/
PA113 A112 PA111 PA110
0
0
1
15
Setting Palette Data :
A3(PS=0) /A11(PS=1)
PA34/
*
*
*
0
0
1
PA114
Setting Palette Data :
A4(PS=0) /A12(PS=1)
PA43/ PA42/P PA41/ PA40/
PA123 A122 PA121 PA120
0
0
1
Setting Palette Data :
A4(PS=0) /A12(PS=1)
PA44/
*
*
*
0
0
1
PA124
Setting Palette Data :
A5(PS=0) /A13(PS=1)
PA53/ PA52/P PA51/ PA50/
PA133 A132 PA131 PA130
0
0
1
Setting Palette Data :
A5(PS=0) /A13(PS=1)
PA54/
*
*
*
0
0
1
PA134
Setting Palette Data :
A6(PS=0) /A14(PS=1)
PA63/ PA62/P PA61/ PA60/
PA143 A142 PA141 PA140
0
0
1
Setting Palette Data :
A6(PS=0) /A14(PS=1)
PA64/
*
*
*
0
0
1
PA144
Instruction Table Select
TST0
RE2
RE1
RE0
14
0/1
0/1
0/1
Setting Instruction Table
[FH]
NOTE1) * : Don’t care.
NOTE2) [NH] (N=0-F) : Register Address
NOTE3) Any nonexistent instruction code is prohibited.
NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.
NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower
byte.
Ver.2004-05-12
- 45 -
NJU6825
(13-4) Instruction Table 2 (RE2, RE1, RE0)=(0, 1, 0)
Code (80 series MPU I/F)
Code
D3
Instructions/
Functions
Register Address [NH]
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D2
D1
D0
Palette A7/A15
Setting Palette Data :
A7(PS=0) /A15(PS=1)
PA73/ PA72/P PA71/ PA70/
PA153 A152 PA151 PA150
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
(Lower) [0H]
Palette A7/A15
Palette B0/B8
Palette B0/B8
Palette B1/B9
Palette B1/B9
Palette B2/B10
Palette B2/B10
Palette B3/B11
Palette B3/B11
Palette B4/B12
Palette B4/B12
Palette B5/B13
Palette B5/B13
Setting Palette Data :
A7(PS=0) /A15(PS=1)
PA74/
*
*
*
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
PA154
(Upper) [1H]
(Lower) [2H]
(Upper) [3H]
(Lower) [4H]
(Upper) [5H]
(Lower) [6H]
(Upper) [7H]
(Lower) [8H]
(Upper) [9H]
(Lower) [AH]
(Upper) [BH]
(Lower) [CH]
(Upper) [DH]
Setting Palette Data :
B0(PS=0) /B8(PS=1)
PB03/ PB02/ PB01/ PB00/
PB83 PB82 PB81 PB80
0
1
0
Setting Palette Data :
B0(PS=0) /B8(PS=1)
PB04/
*
*
*
0
1
0
PG84
Setting Palette Data :
B1(PS=0) /B9(PS=1)
PB13/ PB12/ PB11/ PB10/
PB93 PB92 PB91 PB90
0
1
0
Setting Palette Data :
B1(PS=0) /B9(PS=1)
PB14/
*
*
*
0
1
0
PB94
Setting Palette Data :
B2(PS=0) /B10(PS=1)
PB23/ PB22/ PB21/ PB20/
PB103 PB102 PB101 PB100
0
1
0
15
Setting Palette Data :
B2(PS=0) /B10(PS=1)
PB24/
*
*
*
0
1
0
PB104
Setting Palette Data :
B3(PS=0) /B11(PS=1)
PB33/ PB32/ PB31/ PB30/
PB113 PB112 PB111 PB110
0
1
0
Setting Palette Data :
B3(PS=0) /B11(PS=1)
PB34/
*
*
*
0
1
0
PB114
Setting Palette Data :
B4(PS=0) /B12(PS=1)
PB43/ PB42/ PB41/ PB40/
PB123 PB122 PB121 PB120
0
1
0
Setting Palette Data :
B4(PS=0) /B12(PS=1)
PB44/
*
*
*
0
1
0
PB124
Setting Palette Data :
B5(PS=0) /B13(PS=1)
PB53/ PB52/ PB51/ PB50/
PB133 PB132 PB131 PB130
0
1
0
Setting Palette Data :
B5(PS=0) /B13(PS=1)
PB54/
*
*
*
0
1
0
PB134
Instruction Table Select
TST0
RE2
RE1
RE0
14
0/1
0/1
0/1
Setting Instruction Tablet
[FH]
NOTE1) * : Don’t care.
NOTE2) [NH] (N=0-F) : Register Address
NOTE3) Any nonexistent instruction code is prohibited.
NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.
NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower
byte.
Ver.2004-05-12
- 46 -
NJU6825
(13-5) Instruction Table 3 (RE2, RE1, RE0)=(0, 1, 1)
Code (80 series MPU I/F)
Code
D3
Instructions/
Functions
Register Address [NH]
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D2
D1
D0
Palette B6/B14
Setting Palette Data :
B6(PS=0) /B14(PS=1)
PB63/ PB62/ PB61/ PB60/
PB143 PB142 PB141 PB140
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
(Lower) [0H]
Palette B6/B14
Palette B7/B15
Palette B7/B15
Palette C0/C8
Palette C0/C8
Palette C1/C9
Palette C1/C9
Palette C2/C10
Palette C2/C10
Palette C3/C11
Palette C3/C11
Palette C4/C12
Setting Palette Data :
B6(PS=0) /B14(PS=1)
PB64/
*
*
*
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
PB144
(Upper) [1H]
(Lower) [2H]
(Upper) [3H]
(Lower) [4H]
(Upper) [5H]
(Lower) [6H]
(Upper) [7H]
(Lower) [8H]
(Upper) [9H]
(Lower) [AH]
(Upper) [BH]
Setting Palette Data :
B7(PS=0) /B15(PS=1)
PB73/ PB72/ PB71/ PB70/
PB153 PB152 PB151 PB150
0
1
1
Setting Palette Data :
B7(PS=0) /B15(PS=1)
PB74/
*
*
*
0
1
1
PB154
Setting Palette Data :
C0(PS=0) /C8(PS=1)
PC03/ PC02/ PC01/ PC00/
PC83 PC82 PC81 PC80
0
1
1
Setting Palette Data :
C0(PS=0) /C8(PS=1)
PC04/
*
*
*
0
1
1
PC84
Setting Palette Data :
C1(PS=0) /C9(PS=1)
PC13/ PC12/ PC11/ PC10/
PC93 PC92 PC91 PC90
0
1
1
15
Setting Palette Data :
C1(PS=0) /C9(PS=1)
PC14/
*
*
*
0
1
1
PC94
Setting Palette Data :
C2(PS=0) /C10(PS=1)
PC23/ PC22/ PC21/ PC20/
PC103 PC102 PC101 PC100
0
1
1
Setting Palette Data :
C2(PS=0) /C10(PS=1)
PC24/
*
*
*
0
1
1
PC104
Setting Palette Data :
C3(PS=0) /C11(PS=1)
PC33P PC32/ PC31/ PC30/
C113 PC112 PC111 PC110
0
1
1
Setting Palette Data :
C3(PS=0) /C11(PS=1)
PC34/
*
*
*
0
1
1
PC114
Setting Palette Data :
C4(PS=0) /C12(PS=1)
PC43/ PC42/ PC41/ PC40/
PC123 PC122 PC121 PC120
0
1
1
(Lower) [CH]
Palette C4/C12
(Upper) [DH]
Setting Palette Data :
C4(PS=0) /C12(PS=1)
PC44/
*
*
*
0
1
1
PC124
Instruction Table Select
TST0
RE2
RE1
RE0
14
0/1
0/1
0/1
Setting Instruction Table
[FH]
NOTE1) * : Don’t care.
NOTE2) [NH] (N=0-F) : Register Address
NOTE3) Any nonexistent instruction code is prohibited.
NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.
NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower
byte.
Ver.2004-05-12
- 47 -
NJU6825
(13-6) Instruction Table 4 (RE2, RE1, RE0)=(1, 0, 0)
Code (80 series MPU I/F)
Code
D3
Instructions/
Functions
Register Address [NH]
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D2
D1
D0
Palette C5/C13
Setting Palette Data :
C5(PS=0) /C13(PS=1)
PC53/ PC52/ PC51/ PC50/
PC133 PC132 PC131 PC130
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Lower) [0H]
Palette C5/C13
Palette C6/C14
Palette C6/C14
Palette C7/C15
Palette C7/C15
Initial COM
Setting Palette Data :
C5(PS=0) /C13(PS=1)
PC54/
*
*
*
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
PC134
(Upper) [1H]
(Lower) [2H]
(Upper) [3H]
(Lower) [4H]
(Upper) [5H]
[6H]
Setting Palette Data :
C6(PS=0) /C14(PS=1)
PC63/P PC62/ PC61/ PC60/
C143 PC142 PC141 PC140
15
Setting Palette Data :
C6(PS=0) /C14(PS=1)
PC64/
*
*
*
PC144
Setting Palette Data :
C7(PS=0) /C15(PS=1)
PC73/ PC72/ PC71/ PC70/
PC153 PC152 PC151 PC150
Setting Palette Data :
C7(PS=0) /C15(PS=1)
PC74/
*
SC3
*
*
SC2
*
*
PC154
SC1
DSE
SC0
16
17
18
Setting start COM for scanning
Duty-1 /Display Clock ON/OFF
[7H]
SON : Display Clock ON/OFF
DSE : Duty-1 ON/OFF
SON
PWM
:
Variable/Fixed Grayscale Mode
Display Mode Control
[8H]
PWM C256 FDC1 FDC2
C256 : 256-color Mode ON/OFF.
FDC : Boost clock
HSW : High Speed Writing
ABS : Bit Assignment
CKS : Oscillator Set
Bus Length
[9H]
HSW
ABS CKS
WLS
19
20
0
1
1
0
1
0
0
1
0
0
1
WLS : 8-/16-bit Bus Length
EVR Control
DV3
DV2
DV6
RF2
*
DV1
DV5
RF1
*
DV0
DV4
RF0
DIS
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
1
0
0
Setting EVR Value (Lower Bit)
Setting EVR Value (Upper Bit)
Adjusting Oscillation Frequency
Discharge ON/OFF
(Lower) [AH]
EVR Control
*
*
*
(Upper) [BH]
Frequency Control
[DH]
21
22
23
1
0
0
Discharge ON/OFF
[EH]
1
0
0
Register Address
[CH]
Setting
Register Address
Read Data
1
0
0
Register Address
24 Register Read
0/1
0/1
0/1
0/1
0/1
0/1
Reading Instruction
Instruction Table Select
14
TST0
RE2
RE1
RE0
1
1
1
1
Setting Instruction Table Select
[FH]
NOTE1) * : Don’t care.
NOTE2) [NH] (N=0-F) : Register Address
NOTE3) Any nonexistent instruction code is prohibited.
NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.
NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower
byte.
Ver.2004-05-12
- 48 -
NJU6825
(13-7) Instruction Table 5 (RE2, RE1, RE0)=(1, 0, 1)
Code (80 series MPU I/F)
Code
D4 D3
Instructions/
Functions
Register Address [NH]
CSb RS RDb WRb RE2 RE1 RE0 D7
D6
0
D5
0
D2
D1
D0
Window End Column Address
Setting Column Address
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
EX3 EX2 EX1 EX0
EX7 EX6 EX5 EX4
EY3 EY2 EY1 EY0
EY7 EY6 EY5 EY4
LS3 LS2 LS1 LS0
LS7 LS6 LS5 LS4
LE3 LE2 LE1 LE0
LE7 LE6 LE5 LE4
(Lower) [0H]
for end point
25
26
27
Window End Column Address
(Upper) [1H]
Setting Column Address
for end point
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
Window End Row Address
(Lower) [2H]
Setting Row Address
for end point
1
0
1
Window End Row Address
(Upper) [3H]
Setting Row Address
for end point
1
0
1
Initial Line-reverse Address
(Lower) [4H]
Setting Start Line
1
0
1
for Line-reverse Display
Initial Line-reverse Address
(Upper) [5H]
Setting Start Line
1
0
1
for Line-reverse Display
Last Line-reverse Address
(Lower) [6H]
Setting End Line
1
0
1
for Line-reverse Display
28
29
Last Line-reverse Address
(Upper) [7H]
Setting End Line
1
0
1
for Line-reverse Display
Line Reverse ON/OFF
BT
: Blink Set
1
0
1
*
*
*
*
BT LREV
[8H]
LREV : Line-reverse ON/OFF
Upper/Lower
30 Palette Select
0
1
0
1
*
PS PS : Upper/Lower Palette Register
[9H]
[AH]
PWM Control
31
PWM PWM PWM PWM
0
0
1
0
1
Setting PWM Mode
S
A
B
C
Instruction Table Select
14
0/1
0/1
0/1
TST0 RE2 RE1 RE0 Setting Instruction Table
[FH]
NOTE1) * : Don’t care.
NOTE2) [NH] (N=0-F) : Register Address
NOTE3) Any nonexistent instruction code is prohibited.
NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.
NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower
byte.
Ver.2004-05-12
- 49 -
NJU6825
(14) INSTRUCTION DESCRIPTIONS
This chapter provides detailed descriptions about each instruction. These descriptions are written with the
assumption that 80-series MPU is used. When using 68-series MPU, the polarities of the E and R/W signals differ from
those of the RDb and WRb signals.
(14-1) Display Data Write
The “Display Data Write” instruction writes display data on a specified DDRAM address.
CSb
0
RS
0
RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
1
0
Display Data
(14-2) Display Data Read
The “Display Data Read” instruction reads out display data from a specified DDRAM address. One dummy read is
necessary right after DDRAM address setting.
CSb
0
RS
0
RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
Display Data
(14-3) Column Address
The “Column Address” instruction specifies the column address of the start point. The setting order is lower byte
first, then upper byte.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
1
0
0
0
0
AX3
AX2
AX1 AX0
(Default: AX3-AX0=0H / Register Address: 0H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
D2
D1
D0
1
0
0
0
0
AX7
AX6
AX5 AX4
(Default: AX7-AX4=0H / Register Address: 1H)
(14-4) Row Address
The “Row Address” instruction specifies the row address of the start point. Available setting range is from (00H) to
(A1H), and outside this range is not allowed. The setting order is lower byte first, then upper byte.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
0
0
0
AY3
AY2
AY1 AY0
(Default: AY3-AY0=0H / Register Address: 2H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
D2
D1
D0
1
0
0
0
0
AY7
AY6
AY5 AY4
(Default: AY7-AY4=0H / Register Address: 3H)
(14-5) Initial Display Line
This instruction sets the row address, which corresponds to an initial COM and is normally positioned on top of a
screen in full display. For more information, refer to “(14-16) Initial COM”. The setting order is lower byte first, then
upper byte.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
0
0
0
LA3
LA2
LA1
LA0
(Default: LA3-LA0=0H / Register Address: 4H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
D2
D1
D0
1
0
0
0
0
LA7
LA6
LA5
LA4
(Default: LA7-LA4=0H / Register Address: 5H)
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Table 18 Initial Display Line Address
LA7
0
0
LA6
0
0
LA5
0
0
LA4
0
0
LA3
0
0
LA2
0
0
LA1
0
0
LA0
0
1
Row Address
0
1
:
:
1
0
1
0
0
0
0
1
161
(14-6) N-line Inversion
The number of N line is selected in between “2” and “162”. When the N-line inversion is enabled by setting “1” at
the D2 (NLIN) bit of the “Display Control (2)” instruction, the FR toggles once every N lines. When the N-line inversion
is disabled by setting “0” at this bit, the FR toggles by the frame.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
1
0
0
0
0
N3
N2
N1
N0
(Default: N3-N0=0H / Register Address: 6H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
D2
D1
D0
1
0
0
0
0
N7
N6
N5
N4
(Default: N7-N4=0H / Register Address: 7H)
Table 19 N-line Inversion
N7
0
N6
0
N5
0
N4
0
N3
0
N2
0
N1
N0
0
N Line
0
0
Inhibited
0
0
0
0
0
0
1
2
:
:
:
:
:
:
1
0
1
0
0
0
0
1
162
NOTE1) N Line=(N Value)+1
N-line inversion OFF
1st line
3rd line
162nd line
1st line
2nd line
163rd line
CL
FLM
FR
N-line inversion ON
N-line Inversion
1st line
3rd line
N line
2nd line
2nd line
1st line
CL
FR
Fig 18 N-line Inversion Timing (1/163 Duty)
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(14-7) Display Control (1)
The “Display Control (1)” instruction controls display conditions.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
ALL
ON
1
0
0
0
0
SHIFT MON
ON /OFF
(Default: [SHIFT,MON,ALLON,ON/OFF]=0H / Register Address: 8H)
D0 (ON/OFF)
ON/OFF=0 : Display OFF (All COM/SEG fixed at VSSH level)
ON/OFF=1 : Display ON
D1 (ALLON)
This bit forcibly turns on all pixels regardless of display data. This bit has a priority over the “REV” bit of the
“Display Control (2)” instruction.
ALLON=0
ALLON=1
: Normal
: All pixels ON
D2 (MON)
MON=0
MON=1
: Grayscale Mode (Variable 16-grayscale, Variable 8-grayscale or Fixed 8-grayscale Mode)
: B&W Mode
D3 (SHIFT)
SHIFT=0
SHIFT=1
: COM0 → COM161
: COM0 ← COM161
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(14-8) Display Control (2)
The “Display Control (2)” instruction controls display conditions.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
D2
D1
D0
1
0
0
0
0
REV NLIN SWAP REF
(Default: [REV,NLIN,SWAP,REF]=0H / Register Address: 9H)
D0 (REF)
This bit controls the DDRAM access direction which reverses the segment direction for reducing the restrictions on
the IC position of an LCD module. For more information, refer to “(16) SWAP FUNCTION”.
D1 (SWAP)
This bit swaps palettes Aj and palettes Cj (j=0-15). This function reduces the restrictions on the IC position of an
LCD module. Refer to “(16) SWAP FUNCTION”.
SWAP=0
SWAP=1
: SWAP OFF
: SWAP ON
D2 (NLIN)
This bit enables the N-line inversion.
NLIN=0
NLIN=1
: N-line Inversion OFF
: N-line Inversion ON
(FR toggles by the frame.)
(FR toggles once every N lines.)
D3 (REV)
This bit enables the reverse display function that reverses the polarities of all display data without changing the
DDRAM.
REV=0
REV=1
: Reverse Display OFF
: Reverse Display ON
(Normal)
Table 20 Reverse Display ON/OFF
REV
Display
DDRAM Data → Display Data
0
1
0
1
0
1
1
0
0
Normal
1
Reverse
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(14-9) Increment Control
The “AIM”, “AYI” and “AXI” bits set an auto-increment operation to the column address and row address
individually. Once this mode is set up, the column address, row address or both are automatically counted up, whenever
the DDRAM is accessed. The “WIN” bits enables/disables the window area access.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
0
0
0
WIN
AIM
AYI
AXI
(Default: [WIN,AIM,AYI,AXI]=0H / Register Address: AH)
D2 (AIM)
Table 21 Read-modify-write ON/OFF
AIM
0
1
Increment Mode
Read-modify-write OFF
Read-modify-write ON
NOTE
1
2
NOTE1) Increment in writing and reading display data
NOTE2) Increment in writing display data only
D1, D0 (AYI, AXI)
Table 22 Column/Row Increment
AYI
0
AXI
0
Column/Row Increment
NOTE
Non Increment
1
2
3
4
0
1
Column Address Increment
Row Address Increment
Column & Row Addresses Increment
1
1
0
1
NOTE1) Non increment. The “AIM” bit is disabled.
NOTE2) Increment operation of column address. The “AIM” bit is enabled.
00H
NOTE3) Row address increment. The “AIM” bit is enabled.
00H MAX
NOTE4) Column & row addresses increment. The “AIM” bit is enabled.
00H MAX 00H
Column Address
MAX
MAX
Row Address
D3 (WIN)
The window access should be enabled (WIN=1) in combination with the auto-increment operation (AXI=1, AYI=1).
The typical sequence of the window area setting is discussed in “(4-2) Window Area for DDRAM Access”.
WIN=0
WIN=1
: Window Area Access OFF (Normal DDRAM Access)
: Window Area Access ON
Start
End
Start
End
Ad d r es s
Ad d r es s
Ad d r es s
Address
Column Address
Row Address
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(14-10) Power Control
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
D2
D1
DCON
D0
ACL
0
1
1
0
0
0
0
AMPON HALT
(Default: [AMPON,HALT,DCON,ACL]=0H / Register Address: BH)
D0 (ACL)
This bit initializes the internal LCD power supply.
ACL=0
ACL=1
: Initialization OFF (Normal)
: Initialization ON
NOTE) During the initialization, “1” is read out as the status of the “ACL” bit by the “Register Read” instruction. After the
initialization, it is “0”. As the CLK triggers the initialization, the “wait time” at least equivalent to 2 cycles of the CLK is
required for the next instruction.
D1 (DCON)
The “DCON” bit activates the voltage booster.
DCON=0
DCON=1
: Voltage Booster OFF
: Voltage Booster ON
D2 (HALT)
The “HALT” bit enables the power save mode. During the power save, operating current is down to the stand-by
level. The internal state of the LSI in the power save mode is listed below.
HALT=0
HALT=1
: Power Save OFF (Normal)
: Power Save ON
Internal State in Power Save Mode (HALT=”1”)
- Internal oscillator and internal LCD power supply are halted.
- All segment and common drivers are fixed at VSSH level.
- External clock to the OSC1 cannot be accepted.
- Display data in the DDRAM is being maintained.
- Data in the instruction registers are being maintained.
- VLCD, V1, V2, V3 and V4 are in high impedance.
NOTE) In the power save ON sequence, execute the “Display OFF” prior to the “Power Save ON”. In the power save OFF
sequence, execute the “Power save OFF” prior to the “Display ON”. If the “Power Save ON/OFF” instruction is
executed during the “Display ON”, unexpected pixels may be turned on instantly.
D3 (AMPON)
The “AMPON” bit activates the voltage converter which includes the reference voltage generator, the voltage
regulator and the LCD bias generator.
AMPON=0 : Voltage Converter OFF
AMPON=1 : Voltage Converter ON
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(14-11) Duty Cycle Ratio
The “Duty Cycle Ratio” instruction selects LCD duty cycle ratio, and is used to carry out the partial display in
combination with other instructions such as the “Boost Level”, the “LCD Bias Ratio” and the “EVR Control”.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
0
0
0
DS3 DS2 DS1 DS0
(Default: DS3-DS0=0H / Register Address: CH)
Table 23 Duty Cycle Ratio
Duty Cycle Ratio
# of Commons
DS3
DS2
DS1
DS0
DSE=0
DES=1
1/162
1/160
1/144
1/132
1/128
1/112
1/96
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1/163
1/161
1/145
1/133
1/129
1/113
1/97
162 commons
160 commons
144 commons
132 commons
128 commons
112 commons
96 commons
80 commons
72 commons
64 commons
56 commons
48 commons
40 commons
32 commons
24 commons
16 commons
1/81
1/80
1/73
1/72
1/65
1/64
1/57
1/56
1/49
1/48
1/41
1/40
1/33
1/32
1/25
1/24
1/17
1/16
NOTE) Duty cycle ratio is subtracted by 1 (Duty-1) from the original duty cycle ratio by setting “1” at the D1 (DSE) bit of the
“Duty-1 ON/OFF” instruction. Refer to “(14-17) Duty-1 /Display Clock ON/OFF”.
(14-12) Boost Level
The “Boost Level” selects the multiple of the voltage booster.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
1
0
0
0
0
VU2 VU1 VU0
(Default:VU2-VU0=0H / Register Address: DH)
D2, D1, D0 (VU2, VU1, VU0)
Table 24 Boost Level
VU2
0
VU1
0
VU0
0
Boost Level
1 time (No boost)
2 times
0
0
1
0
1
0
3 times
0
1
1
4 times
1
0
0
5 times
1
0
1
6 times
1
1
0
7 times
1
1
1
Inhibited
.
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(14-13) LCD Bias Ratio
The “LCD bias ratio” selects LCD bias ratio.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
D1
D0
1
0
0
0
0
B2
B1
B0
(Default: B2-B0=0H / Register Address: EH)
Table 25 LCD Bias Ratio
B2
0
B1
0
B0
0
LCD Bias Ratio
1/9
1/8
0
0
1
0
1
0
1/7
0
1
1
1/6
1
0
0
1/5
1
0
1
1/10
1/11
1/12
1
1
0
1
1
1
(14-14) Instruction Table Select
This instruction specifies an instruction table, and should be executed prior to other instructions.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
1
D6
1
D5
1
D4
1
D3
D2
D1
D0
1
0
TST0 RE2 RE1 RE0
(Default: TST0, RE2-RE0=0H / Register Address: FH)
Table 26 Instruction Table Select
RE2
0
RE1
0
RE0
0
Instructions
Instruction Table (0)
Instruction Table (1)
Instruction Table (2)
Instruction Table (3)
Instruction Table (4)
Instruction Table (5)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
NOTE) “TST0” bit must be “0”. This is used for maker tests only.
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(14-15) Palette A / B / C
Palette A0 (PS=0) / Palette A8 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PA03/ PA02/ PA01/ PA00/
PA83 PA82 PA81 PA80
1
0
0
0
1
(Register Address: 0H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA04/
1
0
0
0
1
PA84
(Register Address: 1H)
Palette A1 (PS=0) / Palette A9 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PA13/ PA12/ PA11/ PA10/
1
0
0
0
1
PA93 PA92 PA91 PA90
(Register Address: 2H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA14/
1
0
0
0
1
PA94
(Register Address: 3H)
Palette A2 (PS=0) / Palette A10 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PA23/ PA22/ PA21/ PA20/
1
0
0
0
1
PA103 PA102 PA101 PA100
(Register Address: 4H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA24/
1
0
0
0
1
PA104
(Register Address: 5H)
Palette A3 (PS=0) / Palette A11 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
PA33/ PA32/ PA31/ PA30/
1
0
0
0
1
PA113 PA112 PA111 PA110
(Register Address: 6H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA34/
1
0
0
0
1
PA114
(Register Address: 7H)
Palette A4 (PS=0) / Palette A12 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PA43/ PA42/ PA41/ PA40/
1
0
0
0
1
PA123 PA122 PA121 PA120
(Register Address: 8H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA44/
1
0
0
0
1
PA124
(Register Address: 9H)
NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.
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Palette A5 (PS=0) / Palette A13 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PA53/ PA52/ PA51/ PA50/
1
0
0
0
1
PA133 PA132 PA131 PA130
(Register Address: AH)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA54/
1
0
0
0
1
PA134
(Register Address: BH)
Palette A6 (PS=0) / Palette A14 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
PA63/ PA62/ PA61/ PA60/
1
0
0
0
1
PA143 PA142 PA141 PA140
(Register Address: CH)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA64/
1
0
0
0
1
PA144
(Register Address: DH)
Palette A7 (PS=0) / Palette A15 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PA73/ PA72/ PA71/ PA70/
1
0
0
1
0
PA153 PA152 PA151 PA150
(Register Address: 0H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA74/
1
0
0
1
0
PA154
(Register Address: 1H)
NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.
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Palette B0 (PS=0) / Palette B8 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PB03/ PB02/ PB01/ PB00/
1
0
0
1
0
PB83 PB82 PB81 PB80
(Register Address: 2H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB04/
1
0
0
1
0
PB84
(Register Address: 3H)
Palette B1 (PS=0) / Palette B9 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PB13/ PB12/ PB11/ PB10/
1
0
0
1
0
PB93 PB92 PB91 PB90
(Register Address: 4H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB14/
1
0
0
1
0
PB94
(Register Address: 5H)
Palette B2 (PS=0) / Palette B10 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
PB23/ PB22/ PB21/ PB20/
1
0
0
1
0
PB103 PB102 PB101 PB100
(Register Address: 6H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB24/
1
0
0
1
0
PB104
(Register Address: 7H)
Palette B3 (PS=0) / Palette B11 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PB33/ PB32/ PB31/ PB30/
1
0
0
1
0
PB113 PB112 PB111 PB110
(Register Address: 8H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB34/
1
0
0
1
0
PB114
(Register Address: 9H)
Palette B4 (PS=0) / Palette B12 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PB43/ PB42/ PB41/ PB40/
1
0
0
1
0
PB123 PB122 PB121 PB120
(Register Address: AH)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB44/
1
0
0
1
0
PB124
(Register Address: BH)
NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.
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Palette B5 (PS=0) / Palette B13 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
PB53/ PB52/ PB51/ PB50/
1
0
0
1
0
PB133 PB132 PB131 PB130
(Register Address: CH)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB54/
1
0
0
1
0
PB134
(Register Address: DH)
Palette B6 (PS=0) / Palette B14 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PB63/ PB62/ PB61/ PB60/
1
0
0
1
1
PB143 PB142 PB141 PB140
(Register Address: 0H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB64/
1
0
0
1
1
PB144
(Register Address: 1H)
Palette B7 (PS=0) / Palette B15 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PB73/ PB72/ PB71/ PB70/
1
0
0
1
1
PB153 PB152 PB151 PB150
(Register Address: 2H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB74/
1
0
0
1
1
PB154
(Register Address: 3H)
NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.
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Palette C0 (PS=0) / Palette C8 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC03/ PC02/ PC01/ PC00/
1
0
0
1
1
PC83 PC82 PC81 PC80
(Register Address: 4H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC04/
1
0
0
1
1
PC84
(Register Address: 5H)
Palette C1 (PS=0) / Palette C9 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
PC13/ PC12/ PC11/ PC10/
1
0
0
1
1
PC93 PC92 PC91 PC90
(Register Address: 6H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC14/
1
0
0
1
1
PC94
(Register Address: 7H)
Palette C2 (PS=0) / Palette C10 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PC23/ PC22/ PC21/ PC20/
1
0
0
1
1
PC103 PC102 PC101 PC100
(Register Address: 8H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC24/
1
0
0
1
1
PC104
(Register Address: 9H)
Palette C3 (PS=0) / Palette C11 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PC33/ PC32/ PC31/ PC30/
1
0
0
1
1
PC113 PC112 PC111 PC110
(Register Address: AH)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC34/
1
0
0
1
1
PC114
(Register Address: BH)
Palette C4 (PS=0) / Palette C12 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC43/ PC42/ PC41/ PC40/
1
0
0
1
1
PC123 PC122 PC121 PC120
(Register Address: CH)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC44/
1
0
0
1
1
PC124
(Register Address: DH)
NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.
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Palette C5 (PS=0) / Palette C13 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PC53/ PC52/ PC51/ PC50/
1
0
1
0
0
PC133 PC132 PC131 PC130
(Register Address: 0H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC54/
1
0
1
0
0
PC134
(Register Address: 1H)
Palette C6 (PS=0) / Palette C14 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PC63/ PC62/ PC61/ PC60/
1
0
1
0
0
PC143 PC142 PB141 PB140
(Register Address: 2H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC64/
1
0
1
0
0
PC144
(Register Address: 3H)
Palette C7 (PS=0) / Palette C15 (PS=1)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC73/ PC72/ PC71/ PC70/
1
0
1
0
0
PC153 PC152 PC151 PC150
(Register Address: 4H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC74/
1
0
1
0
0
PC154
(Register Address: 5H)
NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.
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(14-16) Initial COM
The “Initial COM” instruction specifies the common driver for a scan start common.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
0
SC3 SC2 SC1 SC0
(Default: SC3-SC0=0H / Register Address: 6H)
Table 27 Initial COM
SC3
0
SC2
0
SC1
0
SC0
0
Initial COM (SHIFT=0)
COM0
Initial COM (SHIFT=1)
COM161
COM160
COM152
COM146
COM144
COM136
COM128
COM120
COM112
COM104
COM96
0
0
0
1
COM1
0
0
1
0
COM9
0
0
1
1
COM14
0
1
0
0
COM17
0
1
0
1
COM25
0
1
1
0
COM33
0
1
1
1
COM41
1
0
0
0
COM49
1
0
0
1
COM57
1
0
1
0
COM65
1
0
1
1
COM73
COM88
1
1
0
0
COM122
COM130
COM138
COM146
COM39
1
1
0
1
COM31
1
1
1
0
COM23
1
1
1
1
COM15
(14-17) Duty-1 /Display Clock ON/OFF
This instruction controls ON (Duty-1) /OFF (Duty-0) and Display Clock ON/OFF.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
D0
1
0
1
0
0
DSE SON
(Default: SON,DSE=0H / Register Address: 7H)
D0 (SON)
SON=0
SON=1
: CL, FLM, FR, and CLK are fixed at “L” level.
: CL, FLM, FR, and CLK are enabled.
D1 (DSE)
The duty cycle ratio is subtracted by 1 (Duty-1) from the original duty cycle ratio by setting “1” at the “DSE” bit.
DSE=0
DSE=1
: OFF
: ON
(Duty-0)
(Duty-1)
NOTE) For the last common timing at “DSE=0”, all common drivers generate non-selective waveforms, and segment drivers
generate the same waveforms as for the previous common timing. For instance, in 1/163 duty cycle, the segment
waveforms for 163rd common timing are the same as for 162nd common timing (last line).
(14-18) Display Mode Control
The “Display Mode Control” instruction sets up display modes such as the variable or fixed grayscale mode and the
variable 8- or 16-grayscale mode. The D2 (MON) bit of the “Display Control (1)” is used in combination. Refer to “(5)
GRAY SCALE CONTROL CIRCUIT” and “(14-7) Display Control (1).”
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
1
0
1
0
0
PWM C256 FDC1 FDC2
(Default: PWM,C256=0H / Register Address: 8H)
D3 (PWM)
PWM=0
PWM=1
: Variable grayscale Mode (Variable 8-/16-grayscale Mode)
: Fixed 8-grayscale Mode
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D2 (C256)
C256=0
: Variable 16-grayscale Mode at “PWM=0” (4096 colors)
: Variable 8-grayscale Mode at “PWM=0” (256 colors)
C256=1
D1(FDC1), D0(FDC2)
These bits are used to select clock multiply for voltage booster.
FDC1
FDC2
Boost Clock
0
0
1
1
0
1
0
1
×1
×2
×4
×1/2
(14-19) Bus Length
This instruction selects 8- or 16-bit bus length, and sets oscillator configuration, ABS mode ON/OFF and high
speed writing ON/OFF as well.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
D2
D1
D0
1
0
1
0
0
HSW ABS CKS WLS
(Default: HSW,ABS,CKS,WLS=0H / Register Address: 9H)
D0 (WLS)
WLS=0: 8-bit Bus Length
WLS=1: 16-bit Bus Length
D1 (CKS)
CKS =0: Internal Oscillator using an internal resistor
CKS =1: External Clock, or Internal Oscillator using an external resistor
NOTE) Refer to “(10) OSCILLATOR”.
D2 (ABS)
ABS=0: ABS Mode OFF (Normal)
ABS=1: ABS Mode ON
D3 (HSW)
HSW=0: High Speed Writing OFF (Normal)
HSW=1: High Speed Writing ON
(14-20) EVR Control
The “EVR Control” instruction adjusts VLCD to optimize display contrast. This instruction is finally effective when
both upper and lower bytes are transmitted in order to prevent high VLCD. The setting order is upper byte first, then lower
byte. Refer to “(11-2-3) Electrical Variable Resistor (EVR)”.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
0
DV3
DV2
DV1
DV0
(Default: DV3-DV0=0H / Register Address: AH)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
1
0
1
0
0
DV6
DV5
DV4
(Default: DV6-DV4=0H / Register Address: BH)
Table 28 EVR Control
DV6
0
DV5
0
DV4
0
DV3
DV2
0
DV1
0
DV0
0
VLCD
0
0
:
Low
0
0
0
0
0
1
:
:
:
:
1
1
1
1
1
1
1
High
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Formula of VLCD
VLCD [V] = 0.5x VREG + M (VREG – 0.5x VREG) / 127
V
V
BA = VEE x 0.9
REG = VREF x N
VBA
VREF
VREG
N
: Output of the reference voltage generator
: Input of the voltage regulator
: Output of the voltage regulator
: Boost level
M
: EVR Value
(14-21) Frequency Control
The “Frequency Control” instruction adjusts the frame frequency.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
1
0
1
0
0
Rf2
Rf1
Rf0
(Default: DV3-DV0=0H / Register Address: DH)
Table 29 Frequency Control
Rf 2
0
Rf 1
0
Rf 0
0
Feedback Resistor Value
Reference Value
0.8 x Reference Value
0.9 x Reference Value
1.1 x Reference Value
1.2 x Reference Value
Inhibited
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Inhibited
1
1
1
Inhibited
(14-22) Discharge ON/OFF
Discharge circuit is used to discharge out of the stabilizing capacitors placed on the VLCD, V1, V2, V3,V4 and VOUT
Refer to “(11-4) Discharge Circuit”
.
.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
*
D1
*
D0
1
0
1
0
0
DIS
(Default: DIS2,DIS1=0H / Register Address: EH)
D0 (DIS)
DIS=0
: Discharge OFF
: Discharge ON
DIS=1
(Discharge from VLCD, V1, V2, V3 and V4)
NOTE) Resistance is 100KΩ typical.
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(14-23) Register Address
The “Register Address” instruction specifies a register address.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
1
0
0
RA3 RA2 RA1 RA0
(Default: RA3-RA0=BH / Register Address: CH)
(14-24) Register Read
The “Register Read” instruction reads out instruction data from the register which address is specified by the
“Register Address” instruction.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
*
D6
*
D5
*
D4
*
D3
D2
D1
D0
0
1
Internal register data
(14-25) Window End Column Address
The “Window End Column Address” instruction specifies the column address of the end point. Refer to “(4-2)
Window Area for DDRAM Access”. The setting order is lower byte first, then upper byte.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
1
0
1
0
1
EX3 EX2 EX1 EX0
(Default: EX3-EX0=0H / Register Address: 0H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
D2
D1
D0
1
0
1
0
1
EX7 EX6 EX5 EX4
(Default: EX7-EX4=0H / Register Address: 1H)
(14-26) Window End Row Address
The “Window End Row Address” instruction specifies the row address of the end point. Refer to “(4-2) Window
Area for DDRAM Access”. The setting order is lower byte first, then upper byte.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
1
EY3 EY2 EY1 EY0
(Default: EY3-EY0=0H / Register Address: 2H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
D2
D1
D0
1
0
1
0
1
EY7 EY6 EY5 EY4
(Default: EY7-EY4=0H / Register Address: 3H)
(14-27) Initial Line-reverse Address
The “Initial Line-reverse Address” instruction specifies the start line of the line-reverse display area. The setting
order is lower byte first, then upper byte.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
1
0
1
0
1
LS3
LS2
LS1
LS0
(Default: LS3-LS0=0H / Register Address: 4H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
D2
D1
D0
1
0
1
0
1
LS7
LS6
LS5
LS4
(Default: LS7-LS4=0H / Register Address: 5H)
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(14-28) Last Line-reverse Address
The “Last Line-reverse Address” instruction specifies the end line of the line-reverse display area. The setting order
is lower byte first, then upper byte.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
1
0
1
0
1
LE3
LE2
LE1
LE0
(Default: LE3-LE0=0H / Register Address: 6H)
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
D2
D1
D0
1
0
1
0
1
LE7
LE6
LE5
LE4
(Default: LE7-LE4=0H / Register Address: 7H)
(14-29) Line Reverse ON/OFF
The “Line Reverse ON/OFF” instruction enables the line-reverse display, and blink function as well. Note that the
line reverse display cannot be used for entire display area. In this case, use the reverse display function by the D3 (REV)
bit of the “Display Control (2)” instruction.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
*
D2
*
D1
D0
1
0
1
0
1
BT LREV
(Default: BT,LREV=0H / Register Address: 8H)
D0 (LREV)
LREV =0
LREV =1
: Line Reverse OFF (Normal)
: Line Reverse ON
D1 (BT)
BT =0
BT =1
: No Blink
: Blink once every 32 frames
NJRC
NJRC
STN COLOR
STN COLOR
←
←
Initial Line-reverse Address
Last Line-reverse Address
LCD DRIVER
LCD DRIVER
LOW POWER
LOW POWER
Blink / 32 Frames
HIGH PERFORMANCE
HIGH PERFORMANCE
Fig 19 On-screen Image in Using Line-reverse Display and Blink Function
Ver.2004-05-12
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NJU6825
(14-30) Upper/Lower Palette Select
The “Upper/Lower Palette Select” instruction selects either upper or lower palette register.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
1
0
1
0
1
PS
(Default: PS=0 / Register Address: 9H)
D0 (PS)
PS=0
PS=1
: Lower Palettes (PA00, PA01, PA02, PA03, …, PC74)
: Upper Palettes (PA80, PA81, PA82, PA83, …, PC154)
(14-31) PWM Control
The “PWM control” instruction selects PWM type, as shown in Fig 20.
CSb
0
RS
1
RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PWM PWM PWM PWM
1
0
1
0
1
S
A
B
C
(Default: PWMS,PWMA,PWMB,PWMC=0H / Register Address: AH)
D3 (PWMS)
PWMS=0
PWMS=1
: Type 1
: Type 2
D2 (PWMA), D1 (PWMB), D0 (PWMC)
PWMZ=0 (Z=A, B and C): Type 1-O
PWMZ=1 (Z=A, B and C): Type 1-E
PWM Type 1 (PWMS=0)
Odd Line
Even Line
CL
VLCD
V2
Type-0
Type-E
SEG
VLCD
V2
PWM Type 2 (PWMS=1)
CL
VLCD
SEG
V2
Fig 20 PWM Control
Ver.2004-05-12
- 69 -
NJU6825
(15) PARTIAL DISPLAY FUNCTION
The partial display function activates specified area on an LCD screen, or equivalently, common drivers are simply
scanning this specified area. This function allows LCD modules to work in a minimum duty cycle ratio to minimize
power consumption. The partial display function is carried out by the combination of the “Duty Cycle Ratio”, “LCD Bias
Ratio”, “Boost Level” and “EVR Control” instructions. For more information, refer to “(14-11) Duty Cycle Ratio”,
“(14-12) Boost Level”, “(14-13) LCD Bias Ratio” and “(14-20) EVR Control”. Typical setting sequence is shown in
“(18-4) Partial Display Sequence”.
NJRC
LCD DRIVER
Low Power and
Low Voltage
LCD DRIVER
Normal
Partial Display
Fig 21 On-screen Image in Using Partial Display Function
Ver.2004-05-12
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NJU6825
(16) SWAP FUNCTION
The swap function switches the palettes Aj and the palettes Cj (j=0-15), and is controlled by the D1 (SWAP) bit of
the “Display Control (2)” instruction. This function reduces the restrictions on the IC position of an LCD module. Fig 22
“Overview of Swap Function” illustrates general outlines of internal operations, and (16-1-1) through (16-1-4) show
each configuration on a mode-by-mode basis.
(SWAP, REF)=(0,0)
- Default state
(SWAP, REF)=(0,1)
- Swapping Palette A and Palette C
- Reversing Column Address
LCD Panel
LCD Panel
1RGB
1RGB
1RGB
1RGB
Segment
Driver
Segment
Driver
(00H)
(7FH)
(7FH)
(00H)
Grayscale
Control
Circuits
Grayscale
Control
Circuits
A
B
C
Selected Palette
A
B
C
A
B
C
Selected Palette
A
B
C
MSB
MSB
MSB
LSB
LSB
LSB
MSB
MSB
MSB
LSB
MSB
MSB
MSB
LSB
LSB
LSB
MSB
MSB
MSB
LSB
LSB
LSB
Data
Data
Data
Data
(7FH)
(00H)
(00H)
(7FH)
Display Data
in DDRAM
Display Data
in DDRAM
LSB
LSB
Data
Data
Data
Data
Display Data
from MPU
Display Data
from MPU
Data
Data
Data
Data
(00H)
(7FH)
(00H)
(7FH)
(SWAP, REF)=(1,0)
(SWAP, REF)=(1,1)
- Reversing Column Address
- Swapping Palette A and Palette C
LCD Panel
LCD Panel
1RGB
1RGB
1RGB
1RGB
Segment
Driver
Segment
Driver
(7FH)
(00H)
(00H)
(7FH)
Grayscale
Control
Circuits
Grayscale
Control
Circuits
A
B
C
Selected Palette
A
B
C
A
B
C
Selected Palette
A
B
C
MSB
MSB
MSB
LSB
LSB
LSB
MSB
MSB
MSB
LSB
LSB
LSB
MSB
MSB
MSB
LSB
LSB
LSB
MSB
MSB
MSB
LSB
LSB
LSB
Data
Data
Data
Data
(00H)
(7FH)
(7FH)
(00H)
Display Data
in DDRAM
Display Data
in DDRAM
Data
Data
Data
Data
Display Data
from MPU
Display Data
from MPU
Data
Data
Data
Data
(00H)
(7FH)
(00H)
(7FH)
Fig 22 Overview of SWAP Function
Ver.2004-05-12
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NJU6825
(16-1) Swap Function in Variable 16-grayscale Mode
16-bit Bus Length
(REF, SWAP)=(0,0) or (1,1)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
0/31 (Default)
⇑
⇑
7/31 (Default)
⇑
⇑
31/31 (Default)
⇑
Grayscale Level
Grayscale Palette
Palette A0
Palette B3
Palette C15
↑
0
↑
↑
↑
0
↑
0
↑
↑
↑
1
↑
1
↑
↑
↑
1
0
0
0
1
1
1
Display Data
in Grayscale Control Circuit
MSB
↑
LSB
↑
MSB
↑
LSB
↑
MSB
↑
LSB
↑
↑
↑
↑
↑
↑
↑
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D15
D11
D14
D10
D13
D9
D12
D8
D10
D7
D9
D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
ABS=1
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
⇑
7/31 (Default)
⇑
⇑
0/31 (Default)
⇑
31/31 (Default)
⇑
Grayscale Level
Grayscale Palette
Palette C15
Palette B3
Palette A0
↑
↑
↑
↑
1
↑
1
↑
↑
↑
0
↑
0
↑
↑
↑
1
1
1
1
0
0
0
0
Display Data
in Grayscale Control Circuit
LSB
MSB
LSB
MSB
LSB
MSB
|
|
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D15
D11
D14
D10
D13
D9
D12
D8
D10
D7
D9
D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
ABS=1
NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as “0”.
Ver.2004-05-12
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NJU6825
8-bit Bus Length
(REF, SWAP)=(0,0) or (1,1)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
0/31 (Default)
⇑
⇑
7/31 (Default)
⇑
⇑
31/31 (Default)
⇑
Grayscale Level
Palette A0
Palette B3
Palette C15
Grayscale Palette
↑
0
↑
↑
↑
0
↑
0
↑
↑
↑
1
↑
1
↑
↑
↑
1
0
0
0
1
1
1
Display Data
in Grayscale Control Circuit
MSB
↑
LSB
↑
MSB
↑
LSB
↑
MSB
↑
LSB
↑
↑
↑
↑
↑
↑
↑
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D7
D3
D7
D6
D2
D6
D5
D1
D5
D4
D0
D4
D2
D7
D3
D1
D6
D2
D0
D5
D1
D7
D4
D0
D4
D3
D7
D3
D2
D6
D2
D1
D5
D1
D0
D4
ABS=1
HSW=1
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
⇑
7/31 (Default)
⇑
⇑
0/31 (Default)
⇑
31/31 (Default)
⇑
Grayscale Level
Palette C15
Palette B3
Palette A0
Grayscale Palette
↑
↑
↑
↑
1
↑
1
↑
↑
↑
0
↑
0
↑
↑
↑
1
1
1
1
0
0
0
0
Display Data
in Grayscale Control Circuit
LSB
MSB
LSB
MSB
LSB
MSB
|
|
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D7
D3
D7
D6
D2
D6
D5
D1
D5
D4
D0
D4
D2
D7
D3
D1
D6
D2
D0
D5
D1
D7
D4
D0
D4
D3
D7
D3
D2
D6
D2
D1
D5
D1
D0
D4
ABS=1
HSW=1
NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as “0”.
Ver.2004-05-12
- 73 -
NJU6825
(16-2) Swap Function in Variable 8-grayscale Mode
8-bit Bus Length
(REF, SWAP)=(0,0) or (1,1)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
3/31 (Default)
⇑
⇑
7/31 (Default)
⇑
⇑
31/31 (Default)
⇑
Grayscale Level
Grayscale Palette
Palette A0
Palette B3
Palette C15
↑
0
↑
↑
↑
*
↑
0
↑
↑
↑
*
↑
1
↑
↑
↑
*
0
0
0
1
1
*
Display Data
in Grayscale Control Circuit
MSB
↑
LSB
↑
MSB
↑
LSB
↑
MSB
↑
LSB
↑
↑
0
↑
0
↑
0
↑
1
↑
1
↑
*
*
0
*
*
0
*
*
1
*
*
Display Data
from MPU to LSI
D7
D6
D5
D4
D3
D2
D1
D0
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
⇑
7/31 (Default)
⇑
⇑
3/31 (Default)
⇑
31/31 (Default)
⇑
Grayscale Level
Grayscale Palette
Palette C15
Palette B3
Palette A0
↑
↑
↑
↑
1
↑
*
↑
↑
↑
0
↑
*
↑
↑
↑
*
*
1
1
0
0
0
0
Display Data
in Grayscale Control Circuit
LSB
MSB
LSB
MSB
LSB
MSB
|
|
0
0
0
*
*
0
0
1
*
*
1
1
*
*
*
*
Display Data
from MPU to LSI
D7
D6
D5
D4
D3
D2
D1
D0
NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as “0”.
Ver.2004-05-12
- 74 -
NJU6825
(16-3) Swap Function in Fixed 8-grayscale Mode
16-bit Bus Length
(REF, SWAP)=(0,0) or (1,1)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
0/7
⇑
⇑
1/7
⇑
⇑
7/7
⇑
Grayscale Level
-
-
-
↑
0
↑
↑
↑
0
↑
0
↑
↑
↑
1
↑
1
↑
↑
↑
1
0
0
0
1
1
1
Display Data
in Grayscale Control Circuit
MSB
↑
LSB
↑
MSB
↑
LSB
↑
MSB
↑
LSB
↑
↑
↑
↑
↑
↑
↑
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D15
D11
D14
D10
D13
D9
D12
D8
D10
D7
D9
D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
ABS=1
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
7/7
⇑
⇑
1/7
⇑
⇑
0/7
⇑
Grayscale Level
-
-
-
↑
↑
↑
↑
1
↑
1
↑
↑
↑
0
↑
0
↑
↑
↑
1
1
1
1
0
0
0
0
Display Data
in Grayscale Control Circuit
LSB
MSB
LSB
MSB
LSB
MSB
|
|
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D15
D11
D14
D10
D13
D9
D12
D8
D10
D7
D9
D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
ABS=1
NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as “0”.
NOTE2) The data indicated with a slash mark ( / ) is invalid.
Ver.2004-05-12
- 75 -
NJU6825
8-bit Bus Length
(REF, SWAP)=(0,0) or (1,1)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
0/7
⇑
⇑
1/7
⇑
⇑
7/7
⇑
Grayscale Level
-
-
-
↑
0
↑
↑
↑
0
↑
0
↑
↑
↑
1
↑
1
↑
↑
↑
1
0
0
0
1
1
1
Display Data
in Grayscale Control Circuit
MSB
↑
LSB
↑
MSB
↑
LSB
↑
MSB
↑
LSB
↑
↑
↑
↑
↑
↑
↑
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D7
D3
D7
D7
D6
D2
D6
D6
D5
D1
D5
D5
D4
D0
D4
*
D2
D7
D3
D4
D1
D6
D2
D3
D0
D5
D1
D2
D7
D4
D0
*
D4
D3
D7
D1
D3
D2
D6
D0
D2
D1
D5
*
D1
D0
D4
*
ABS=1
HSW=1
C256=1
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
7/7
⇑
⇑
1/7
⇑
⇑
0/7
⇑
Grayscale Level
-
-
-
↑
↑
↑
↑
1
↑
1
↑
↑
↑
0
↑
0
↑
↑
↑
1
1
1
1
0
0
0
0
Display Data
in Grayscale Control Circuit
LSB
MSB
LSB
MSB
LSB
MSB
|
|
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D7
D3
D7
D7
D6
D2
D6
D6
D5
D1
D5
D5
D4
D0
D4
*
D2
D7
D3
D4
D1
D6
D2
D3
D0
D5
D1
D2
D7
D4
D0
*
D4
D3
D7
D1
D3
D2
D6
D0
D2
D1
D5
*
D1
D0
D4
*
ABS=1
HSW=1
C256=1
NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as “0”.
NOTE2) The data indicated with a slash mark ( / ) is invalid.
Ver.2004-05-12
- 76 -
NJU6825
(16-4) Swap Function in B&W Mode
16-bit Bus Length
(REF, SWAP)=(0,0) or (1,1)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
⇑
⇑
0/1 (OFF)
0/1 (OFF)
1/1 (ON)
Grayscale Level
⇑
⇑
⇑
-
-
-
↑
0
↑
↑
↑
0
↑
0
↑
↑
↑
1
↑
1
↑
↑
↑
1
0
0
0
1
1
1
Display Data
in Grayscale Control Circuit
MSB
↑
LSB
↑
MSB
↑
LSB
↑
MSB
↑
LSB
↑
↑
↑
↑
↑
↑
↑
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D15
D11
D14
D10
D13
D9
D12
D8
D10
D7
D9
D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
ABS=1
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
⇑
⇑
1/1 (ON)
0/1 (OFF)
0/1 (OFF)
Grayscale Level
⇑
⇑
⇑
-
-
-
↑
↑
↑
↑
1
↑
1
↑
↑
↑
0
↑
0
↑
↑
↑
1
1
1
1
0
0
0
0
Display Data
in Grayscale Control Circuit
LSB
MSB
LSB
MSB
LSB
MSB
|
|
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D15
D11
D14
D10
D13
D9
D12
D8
D10
D7
D9
D6
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
ABS=1
NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as “0”.
NOTE2) The data indicated with a slash mark ( / ) is invalid.
Ver.2004-05-12
- 77 -
NJU6825
8-bit Bus Length
SWAP=0
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
⇑
⇑
0/1 (OFF)
0/1 (OFF)
1/1 (ON)
Grayscale Level
-
-
-
↑
0
↑
↑
↑
0
↑
0
↑
↑
↑
1
↑
1
↑
↑
↑
1
0
0
0
1
1
1
Display Data
in Grayscale Control Circuit
MSB
↑
LSB
↑
MSB
↑
LSB
↑
MSB
↑
LSB
↑
↑
↑
↑
↑
↑
↑
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D7
D3
D7
D7
D6
D2
D6
D6
D5
D1
D5
D5
D4
D0
D4
*
D2
D7
D3
D4
D1
D6
D2
D3
D0
D5
D1
D2
D7
D4
D0
*
D4
D3
D7
D1
D3
D2
D6
D0
D2
D1
D5
*
D1
D0
D4
*
ABS=1
HSW=1
C256=1
SWAP=1
SEGAi
SEGBi
SEGCi
(i=0-127)
⇑
⇑
⇑
1/1 (ON)
0/1 (OFF)
0/1 (OFF)
Grayscale Level
⇑
⇑
⇑
-
-
-
↑
↑
↑
↑
1
↑
1
↑
↑
↑
0
↑
0
↑
↑
↑
1
1
1
1
0
0
0
0
Display Data
in Grayscale Control Circuit
LSB
MSB
LSB
MSB
LSB
MSB
|
|
0
0
0
0
0
0
1
1
1
1
1
1
Display Data
from MPU to LSI
D7
D3
D7
D7
D6
D2
D6
D6
D5
D1
D5
D5
D4
D0
D4
*
D2
D7
D3
D4
D1
D6
D2
D3
D0
D5
D1
D2
D7
D4
D0
*
D4
D3
D7
D1
D3
D2
D6
D0
D2
D1
D5
*
D1
D0
D4
*
ABS=1
HSW=1
C256=1
NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as “0”.
NOTE2) The data indicated with a slash mark ( / ) is invalid.
(17) RELATION BETWEEN ROW ADDRESS AND COMMON DRIVER
The relation between row address and common driver is changed by the D3 (SHIFT) bit of the “Display Control
(1)” and the “Duty Cycle Ratio”, “Initial Display Line” and “Initial COM” instructions.
When the “Initial Display Line” is set to (LA7:LA0=00H: Address “0”), the row address corresponding to an initial
COM is “0”. However, if the “Initial Display Line” is other than “0”, the row address is shifted from “0” by just that
address. For instance, when the initial display line address is (LA7:LA0=05H: Address “5”) and the initial COM is
(SC3:SC0=1H), the row address on the initial COM is “5” and the initial COM is “COM1”.
(17-1) through (17-5) illustrate the examples of the relation between row address and common driver.
Ver.2004-05-12
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NJU6825
(17-1) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/163”
SHIFT=”0”(Common forward scan), DS3, 2
,
,
1
0=”0000”, LA7….LA0=”00000000”(Initial display line 0) DSE=”0”
SC3
SC2
SC1
SC0
0000
0
0001
0010
153
0011
148
0100
145
0101
137
0110
129
0111
121
1000
113
1001
105
1010
97
1011
89
1100
40
1101
32
1110
24
1111
16
COM0
161
0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
161
0
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
:
161
0
161
0
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
:
161
0
161
0
161
0
161
0
161
0
161
0
161
0
COM120
COM121
COM122
:
161
0
COM128
COM129
COM130
:
161
0
COM136
COM137
COM138
COM139
COM140
COM141
COM142
COM143
COM144
COM145
COM146
COM147
COM148
COM149
COM150
COM151
COM152
COM153
COM154
COM155
COM156
COM157
COM158
COM159
COM160
COM161
161
0
161
0
161
161
160
161
152
161
147
161
144
161
136
161
128
161
120
161
112
161
104
161
96
161
88
161
39
161
31
161
23
161
15
161
(163rd COM period) *2
Fig 23 Relation between Row address and Common Driver (1)
NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address
NOTE2) Segment waveforms for 163rd COM timing are the same as for 162nd COM timing (Row address “A1H”).
Ver.2004-05-12
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NJU6825
(17-2) SHIFT=1, Initial Display Line “0”, Duty Cycle Ratio “1/163”
SHIFT=”1”(Common backward scan), DS3, 2
,
,
1
0=”0000”, LA7….LA0=”00000000”(Initial display line 0) DSE=”0”
SC3
SC2
SC1
SC0
0000
161
0001
160
0010
152
0011
146
0100
144
0101
136
0110
128
0111
120
1000
112
1001
104
1010
96
1011
88
1100
39
1101
31
1110
23
1111
15
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
:
0
161
0
161
COM31
COM32
:
COM39
COM40
:
0
161
0
161
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
COM107
COM108
COM109
COM110
COM111
COM112
COM113
COM114
COM115
COM116
COM117
COM118
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
COM128
COM129
COM130
COM131
COM132
COM133
COM134
COM135
COM136
COM137
COM138
COM139
COM140
COM141
COM142
COM143
COM144
COM145
COM146
COM147
COM148
COM149
COM150
COM151
COM152
COM153
COM154
COM155
COM156
COM157
COM158
COM159
COM160
COM161
0
161
0
161
0
161
0
161
0
161
0
161
0
161
0
161
0
161
0
161
0
0
161
161
153
161
147
161
145
161
137
161
129
161
121
161
113
161
105
161
97
161
89
161
40
161
32
161
24
161
16
161
(163rd COM period) *2
161
Fig 24 Relation between Row address and Common Driver (2)
NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address
NOTE2) Segment waveforms for 163rd COM timing are the same as for 162nd COM timing (Row address “A1H”).
- 80 -
Ver.2004-05-12
NJU6825
(17-3) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/16”
SHIFT=”0”(Common forward scan), DS3, 2
,
,
1
0=”1111”, LA7….LA0=”00000000”(Initial display line 0) DSE=”1”
SC3
SC2
SC1
SC0
0000
0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
COM0
COM1
COM2
:
0
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
:
0
0
15
15
0
15
0
15
15
0
15
0
15
0
15
0
15
0
15
0
15
COM88
:
15
COM121
COM122
:
0
COM130
COM131
COM132
COM133
COM134
COM135
COM136
COM137
COM138
:
0
15
0
COM145
COM146
:
COM153
:
COM160
COM161
15
0
15
15
Fig 25 Relation between Row address and Common Driver (3)
NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address
Ver.2004-05-12
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NJU6825
(17-4) SHIFT=0, Initial Display Line “5”, Duty Cycle Ratio “1/163”
SHIFT=”0”(Common forward scan), DS3, 2
,
,
1
0=”0000”, LA7….LA0=”00000101”(Initial display line 5) DSE=”0”
SC3
SC2
SC1
SC0
0000
5
0001
0010
158
0011
153
0100
150
0101
142
0110
134
0111
126
1000
118
1001
110
1010
102
1011
94
1100
45
1101
37
1110
29
1111
21
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
:
4
5
161
0
161
0
5
161
0
5
5
161
0
5
161
0
COM33
COM34
COM35
COM36
:
5
161
0
COM41
COM42
COM43
COM44
:
5
161
0
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
:
5
161
0
5
1161
0
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
:
5
161
0
5
COM116
COM117
:
161
0
5
COM122
COM123
COM124
COM125
COM126
COM127
COM128
COM129
COM130
COM131
COM132
COM133
COM134
COM135
COM136
COM137
COM138
COM139
COM140
COM141
COM142
COM143
COM144
COM145
COM146
:
161
0
5
161
0
5
161
0
5
COM156
COM157
COM158
COM159
COM160
COM161
161
0
161
0
4
4
3
4
157
4
152
4
149
4
141
4
133
4
125
4
117
4
109
4
101
4
93
4
44
4
36
4
28
4
20
4
(163rd COM period) *1
Fig 26 Relation between Row address and Common Driver (4)
NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address
Ver.2004-05-12
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NJU6825
(17-5) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/162”
SHIFT=”0”(Common forward scan), DS3, 2
,
,
1
0=”0000”, LA7….LA0=”00000000”(Initial display line 0) DSE=”1”
SC3
SC2
SC1
SC0
0000
0
0001
0010
153
0011
148
0100
145
0101
137
0110
129
0111
121
1000
113
1001
105
1010
97
1011
89
1100
40
1101
32
1110
24
1111
16
COM0
161
0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
161
0
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
:
161
0
161
0
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
:
161
0
161
0
161
0
161
0
161
0
161
0
161
0
COM120
COM121
COM122
:
161
0
COM128
COM129
COM130
:
161
0
COM136
COM137
COM138
COM139
COM140
COM141
COM142
COM143
COM144
COM145
COM146
COM147
COM148
COM149
COM150
COM151
COM152
COM153
COM154
COM155
COM156
COM157
COM158
COM159
COM160
COM161
161
0
161
0
161
160
152
147
144
136
128
120
112
104
96
88
39
31
23
15
Fig 27 Relation between Row address and Common Driver (5)
NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address
Ver.2004-05-12
- 83 -
NJU6825
(18) TYPICAL INSTRUCTION SEQUENCES
(18-1) Initialization Sequence in Using Internal LCD Power Supply
Power ON (VDD, VEE) with RESb "L"
WAIT (NOTE2)
(NOTE1)
RESET
WAIT (NOTE3)
-------------- Instruction Code --------------
D7 D6 D5 D4 D3 D2 D1 D0
--------- Setting (Example) ---------
Display Setting
INSTRUCTION TABLE SELECT
1
1
0
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
0
1
0
*
0
0
1
0
1
1
0
0
1
0
0
*
0
1
0
0
0
*
- Instruction Table Select (0,0,0)
- 1/65 Duty
Duty Cycle Ratio
N-line Inversion (Lower)
N-line Inversion (Upper)
INSTRUCTION TABLE SELECT
Display Mode Control
- N=7
0
1
- Instruction Table Select (1,0,0)
- Fixed 8-grayscale Mode
- 256-color Mode ON
Power Setting
EVR Control (Upper)
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
*
1
0
0
*
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
0
0
- M=95
EVR Control (Lower)
INSTRUCTION TABLE SELECT
Boost Level
- Instruction Table Select (0,0,0)
- 5-times Booster
LCD Bias Ratio
- 1/7 Bias
Power Control
WAIT (NOTE4)
Power Control
0
- Voltage Booster ON
1
0
1
1
1
0
1
0
- Voltage Converter ON
WAIT (NOTE5)
END
NOTE1) If different power sources are applied to the VDD and the VEE, turn on the VDD first.
NOTE2) Wait until the VDD and VEE are stabilized.
NOTE3) Wait 10 [us] or more.
NOTE4) Wait until the VOUT is stabilized.
NOTE5) Wait until the VLCD and V1-V4 are stabilized.
Ver.2004-05-12
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NJU6825
(18-2) Initialization Sequence in Using External LCD Power Supply
Power ON (VDD) with RESb "L"
WAIT (NOTE1)
RESET
WAIT (NOTE2)
External LCD Power Supply ON
WAIT (NOTE3)
-------------- Instruction Code -------------- --------- Setting (Example) ---------
D7 D6 D5 D4 D3 D2 D1 D0
Display Setting
INSTRUCTION TABLE SELECT
1
1
0
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
0
1
0
*
0
0
1
0
1
1
0
0
1
0
0
*
0
1
0
0
0
*
- Instruction Table Select (0,0,0)
Duty Cycle Ratio
N-line Inversion (Lower)
N-line Inversion (Upper)
INSTRUCTION TABLE SELECT
- 1/65 Duty
- N=7
0
1
- Instruction Table Select (1,0,0)
Display Mode Control
END
- Fixed 8-grayscale Mode
- 256-color Mode ON
NOTE1) Wait until the VDD is stabilized.
NOTE2) Wait 10 [us] or more.
NOTE3) Wait until the external LCD power supply (VOUT, VLCD, V1-V4) are stabilized.
Ver.2004-05-12
- 85 -
NJU6825
(18-3) Display Data Write Sequence
Optional Status
-------------- Instruction Code -------------- --------- Setting (Example) ---------
D7 D6 D5 D4 D3 D2 D1 D0
INSTRUCTION TABLE SELECT
Initial Display Line (Lower)
Initial Display Line (Upper)
Increment Control
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
0
*
0
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
- Instruction Table Select (0,0,0)
-Initial Display Line (00)H
- Window Area Access ON
- Read-modify-write ON
- Column & Row Increment
1
0
0
0
0
0
0
0
0
0
0
1
Column Address (Lower)
Column Address (Upper)
Row Address (Lower)
-
Window Start Column Address (00)H
- Window Start Row Address (00)H
- Instruction Table Select (1,0,1)
-Window End Column Address (04)H
Row Address (Upper)
INSTRUCTION TABLE SELECT
Window End Column Address (Lower)
Window End Column Address (Upper)
Window End Row Address (Lower)
Window End Row Address (Upper)
Display Data Write
- Window End Row Address (04)H
- Writing Display Data on the DDRAM
for Checker Flag in B&W Mode (Example)
00H
04H
← X →
:
00H
↑
Y
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Repeating All “0” and All “1” Alternately
↓
04H
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
Display Data Write
INSTRUCTION TABLE SELECT
- Instruction Table Select (0,0,0)
- Display ON
Display Control (1)
END
Ver.2004-05-12
- 86 -
NJU6825
(18-4) Partial Display Sequence
Optional Status
-------------- Instruction Code -------------- --------- Setting (Example) ---------
D7 D6 D5 D4 D3 D2 D1 D0
INSTRUCTION TABLE SELECT
Display Control (1)
1
1
1
1
1
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
- Instruction Table Select (0,0,0)
- Display OFF
Power Control
- Voltage Converter OFF
- Voltage Booster OFF
Power Control
WAIT (NOTE1)
Display Setting
Duty Cycle Ratio
1
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
*
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
- 1/33 Duty
Initial Display Line (Lower)
Initial Display Line (Upper)
INSTRUCTION TABLE SELECT
Initial COM
- Initial Display Line (00)H
0
0
- Instruction Table Select (1,0,0)
- Initial COM: COM0
Power Setting
EVR Control (Upper)
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
*
1
0
*
0
1
0
0
1
0
1
0
0
1
0
1
1
0
0
0
0
0
- M=60
EVR Control (Lower)
INSTRUCTION TABLE SELECT
Boost Level
- Instruction Table Select (0,0,0)
- 3-times Booster
LCD Bias Ratio
*
- 1/5 Bias
Power Control
WAIT (NOTE2)
Power Control
WAIT (NOTE3)
Display Control (1)
END
0
- Voltage Booster ON
1
1
0
0
1
0
1
0
1
0
0
0
1
0
0
1
- Voltage Converter ON
- Display ON
NOTE1) Wait until the voltage booster is completely turned off. Make sure what is the wait time in the particular application.
NOTE2) Wait until the VOUT is stabilized.
NOTE3) Wait until the VLCD and V1-V4 are stabilized.
Ver.2004-05-12
- 87 -
NJU6825
(18-5) Power OFF Sequence
Optional Status
-------------- Instruction Code -------------- --------- Setting (Example) ---------
D7 D6 D5 D4 D3 D2 D1 D0
INSTRUCTION TABLE SELECT
Display Control (1)
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
*
0
0
0
0
1
1
*
0
0
1
0
0
0
1
0
0
0
0
0
0
1
- Instruction Table Select (0,0,0)
- Display OFF
Power Control
- Voltage Converter OFF
- Voltage Booster OFF
- Power Save ON
Power Control
Power Control
INSTRUCTION TABLE SELECT
- Instruction Table Select (1,0,0)
- Discharge ON
Discharge ON/OFF
WAIT (NOTE)
Power OFF (VDD-VSS, VEE-VSSH
)
END
NOTE) Wait until the Discharge is completed.
Ver.2004-05-12
- 88 -
NJU6825
ꢀ ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
Supply Voltage (3)
Supply Voltage (4)
Supply Voltage (5)
Supply Voltage (6)
Input Voltage
SYMBOL
VDD
CONDITION
TERMINAL
VDD
RATING
-0.3 to +4.0
UNIT
V
VEE
VEE
-0.3 to +4.0
V
VSS=0V
VOUT
VOUT
-0.3 to +19.0
-0.3 to +19.0
-0.3 to +19.0
-0.3 to VLCD + 0.3
-0.3 to VDD + 0.3
-45 to +100
V
VREG
VREG
V
Ta = +25°C
VLCD
VLCD
V
V1, V2, V3, V4
VI
V1, V2, V3, V4
*1
V
V
Storage Temperature
Tstg
TCP
°C
NOTE1) D0 to D15, CSb, RS, RDb, WRb, OSC1, RESb, TEST1, and TEST2
NOTE2) To stabilize the LSI operation, place decoupling capacitors between VDD and VSS and between VEE and VSSH
.
ꢀ RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
SYMBOL
VDD1
TERMINAL
VDD
MIN
1.7
2.4
2.4
5
TYP
MAX
3.3
UNIT NOTE
V
V
1
2
3
4
VDD2
3.3
VEE
VEE
VLCD
VOUT
VREG
VREF
3.3
V
VLCD
18.0
18.0
OUT × 0.9
3.3
V
VOUT
VREG
VREF
V
Operating Voltage
V
V
2.1
-30
V
5
Operating Temperature
Topr
85
°C
NOTE1) Applied to the condition when the reference voltage generator is not used.
NOTE2) Applied to the condition when the reference voltage generator is used.
NOTE3) Applied to the condition when the voltage booster is used.
NOTE4) The following relation among the LCD bias voltages must be maintained.
VSSH<V4<V3<V2<V1<VLCD<VOUT
NOTE5) Relation: VREF<VEE must be maintained.
Ver.2004-05-12
- 89 -
NJU6825
ꢀ DC CHARACTERISTICS
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85°C
SYM
PARAMETER
BOL
CONDITION
MIN
TYP
MAX
UNIT NOTE
VIH
VIL
VOH1
VOL1
VOH2
VOL2
ILI
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input leakage current
0.8 VDD
0
VDD
V
V
*1
*1
*2
*2
*3
*3
*4
*5
0.2VDD
IOH = -0.4mA
VDD - 0.4
V
IOL = 0.4mA
0.4
V
IOH = -0.1mA
IOL = 0.1mA
VI = VSS or VDD
VI = VSS or VDD
VDD - 0.4
V
0.4
10
10
2
4
15
948
214
31
V
-10
-10
µA
µA
ILO
Output leakage current
VLCD = 10V
VLCD = 6V
VDD = 3V
1
2
RON1
Driver ON-resistance
*6
|∆VON| = 0.5V
kΩ
µA
ISTB
*7
CSb=VDD, Ta=25°C
Stand-by current
fOSC1
fOSC2
fOSC3
fr1
fr2
fr3
659
149
21
804
181
25.9
750
185
27.2
*8
*9
*10
VDD = 3V
Ta = 25°C
Internal oscillation
Frequency
kHz
Rf=10kΩ
Rf=51kΩ
Rf=390kΩ
External oscillation
Frequency
kHz
V
*11
*12
N-time booster (N=2 to 7)
Voltage converter
output voltage
(N x VEE
)
VOUT
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
VBA
x 0.95
RL = 500kΩ (VOUT - VSS
)
VDD = 2.5V, 7-time booster
Whole ON pattern
Supply current (1)
Supply current (2)
Supply current (3)
Supply current (4)
Supply current (5)
Supply current (6)
Supply current (7)
Supply current (8)
VBA Operating voltage
870
1060
760
1300
1590
1140
1400
780
VDD = 2.5V, 7-time booster
Checker pattern
VDD = 3V, 6-time booster
Whole ON pattern
VDD = 3V, 6-time booster
Checker pattern
930
*13
µA
VDD = 3V, 5-time booster
Whole ON pattern
520
VDD = 3V, 5-time booster
Checker pattern
650
980
VDD = 3V, 4-time booster
Whole ON pattern
360
540
VDD = 3V, 4-time booster
Checker pattern
450
680
(0.9 VEE
)
(0.9 VEE
)
VEE = 2.4 to 3.3V
0.9 VEE
V
V
*14
*15
x 0.98
x 1.02
VEE = 2.4 to 3.3V
(VREF x N)
x 0.97
(VREF x N)
x 1.03
VREG
(VREF x N)
VREG Operating voltage
VREF = 0.9 x VEE
N-time booster (N=2 to 7)
V2
V3
VD12
VD34
VD24
-100
-100
-30
-30
-30
0
0
0
0
0
+100
+100
+30
+30
+30
Output Voltage
mV
*16
Ver.2004-05-12
- 90 -
NJU6825
ꢀOSCILLATION FREQUENCY AND FRAME FREQUENCY
Display duty cycle ratio (1/D) <DSE=0>
1/163 to 1/97 1/81 to 1/57 1/49 to 1/33
PARAMETER SYMBOL
NOTE
Display mode
1/25 to 1/17
Variable 8-/16-level
Grayscale Mode
fOSC / (62xD) fOSC / (62xDx2) fOSC / (62xDx4) fOSC / (62xDx8)
Internal clock
External clock
fOSC
Fixed 8-level Grayscale Mode fOSC / (14xD) fOSC / (14xDx2) fOSC / (14xDx4) fOSC / (14xDx8)
B&W Mode
fOSC / (2xD)
fCK / (62xD)
fCK / (14xD)
fCK / (2xD)
fOSC / (2xDx2)
fCK / (62xDx2)
fCK / (14xDx2)
fCK / (2xDx2)
fOSC / (2xDx4) fOSC / (2xDx8)
fCK / (62xDx4) fCK / (62xDx8)
fCK / (14xDx4) fCK / (14xDx8)
FLM
Variable 8-/16-level
Grayscale Mode
fCK
Fixed 8-level Grayscale Mode
B&W Mode
fCK / (2xDx4)
fCK / (2xDx8)
Ver.2004-05-12
- 91 -
NJU6825
NOTE1) D0-D15, CSb, RS, RDb, WRb, P/S, SEL68 and RESb
NOTE2) D0-D15
NOTE3) CL, FLM, FR and CLK
NOTE4) CSb, RS, SEL68, RDb, WRb, P/S, RESb and OSC1
NOTE5) D0-D15 in high impedance
NOTE6) SEGA0-SEGA127, SEGB0-SEGB127, SEGC0-SEGC127 and COM0-COM161
This parameter defines the resistance between each COM/SEG and each LCD bias (VLCD, V1, V2, V3 and V4).
- 0.5V Difference / 1/9 LCD Bias
NOTE7) VDD
Oscillator is halted.
- CSb=1 (Disabled) / No-load on COM/SEG
NOTE8) CLK
This parameter defines the oscillation frequency by using the internal resistor, in the Variable grayscale mode.
- (Rf2, Rf1, Rf0)=(0,0,0)
NOTE9) CLK
This parameter defines the oscillation frequency by using the internal resistor, in the 8-level fixed grayscale mode.
- (Rf2, Rf1, Rf0)=(0,0,0)
NOTE10) CLK
This parameter defines the oscillation frequency by using the internal resistor, in the B&W mode.
- (Rf2, Rf1, Rf0)=(0,0,0)
NOTE11) OSC2
- VDD=3V / Ta=25°C
NOTE12) VOUT
This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used.
- VEE=2.4V to 3.3V / EVR= (1,1,1,1,1,1,1) / 1/5 to 1/12 LCD Bias / 1/163 Duty Cycle / No-load on COM/SEG /
RL=500kΩ between VOUT and VSSH / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” / AMPON=”1”
NOTE13) VSS
This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used.
- EVR= (1,1,1,1,1,1,1) / All Pixels ON or Checker Flag Display / No-load on COM/SEG / No-access from MPU /
VDD=VEE / VREF=0.9VEE / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” / AMPON=”1” / NLIN=”0” / 1/163 Duty cycle /
Ta=25°C
NOTE14) VBA
- VBA=VREF / Boost Level (N)=”1”,/ DCON=”0” / VOUT=13.5V
NOTE15) VREG
- VEE=2.4V to 3.3V / VREF=0.9VEE / VOUT=18V / 1/5 to 1/12 LCD bias ratio / 1/163 duty cycle / EVR=(1,1,1,1,1,1,1)
/ Checker flag display / No-load on COM/SEG / Boost Level (N)=”2” to “7” / CA1=CA2=1.0uF / CA3=0.1uF /
DCON=”0” / AMPON=”1” / NLIN=”0”
NOTE16) VLCD, V1, V2, V3 and V4
- VEE=3.0V / VREF=0.9VEE / VOUT=15V/ 1/5 to 1/12 LCD Bias / EVR= (1,1,1,1,1,1,1) / Display OFF / No-load on
COM/SEG / Boost Level (N)=”5” / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”0” / AMPON=”1”
VLCD
V1
VD12: (1)-(2)
VD34: (3)-(4)
VD24: (2)-(4)
(1)
(2)
V2
V3
(3)
(4)
V4
VSSH
Ver.2004-05-12
- 92 -
NJU6825
ꢀAC CHARACTERISTICS
(1) Write Operation (Parallel Interface / 80-series MPU)
tAS8
tAH8
CSb
RS
WRb
tWRLW8
tWRHW8
tDS8
tDH8
D0 to D15
tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
CONDITION
CONDITION
CONDITION
PARAMETER
SYMBOL
MIN.
MAX.
MAX.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
140
60
60
ns
ns
ns
WRb
Data setup time
Data hold time
tDS8
tDH8
30
10
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
MIN.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
160
70
70
ns
ns
ns
WRb
Data setup time
Data hold time
tDS8
tDH8
40
10
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
MIN.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLW8
tWRHW8
240
110
110
ns
ns
ns
WRb
Data setup time
Data hold time
tDS8
tDH8
70
15
ns
ns
D0 to D15
NOTE) Each timing is specified based on 20% and 80% of VDD
.
Ver.2004-05-12
- 93 -
NJU6825
(2) Read Operation (Parallel Interface / 80-series MPU)
tAH8
tAS8
CSb
RS
tWRLR8
RDb
tWRHR8
tRDH8
D0 to D15
tRDD8
tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
CONDITION
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
180
80
80
ns
ns
ns
RDb
Read Data delay time
Read Data hold time
tRDD8
tRDH8
60
ns
ns
CL=15pF
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
CONDITION
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
180
80
80
ns
ns
ns
RDb
Read Data delay time
Read Data hold time
tRDD8
tRDH8
60
ns
ns
CL=15pF
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
CONDITION
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH8
tAS8
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
250
120
120
ns
ns
ns
RDb
Read Data delay time
Read Data hold time
tRDD8
tRDH8
110
ns
ns
CL=15pF
D0 to D15
0
NOTE) Each timing is specified based on 20% and 80% of VDD
.
Ver.2004-05-12
- 94 -
NJU6825
(3) Write Operation (Parallel Interface / 68-series MPU)
tAS6
tAH6
CSb
RS
R/W
tELW6
t
E
tDS6
tDH6
D0 to D15
tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
CONDITION
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
140
60
60
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
40
10
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
CONDITION
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
160
70
70
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
50
10
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
CONDITION
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELW6
tEHW6
240
110
110
ns
ns
ns
E
Data setup time
Data hold time
tDS6
tDH6
70
15
ns
ns
D0 to D15
NOTE) Each timing is specified based on 20% and 80% of VDD
.
Ver.2004-05-12
- 95 -
NJU6825
(4) Read Operation (Parallel Interface / 68-series MPU)
tAS6
tAH6
CSb
RS
R/W
(WRb)
tELR6
tEHR6
E
(RDb)
tRDH6
D0 to D15
tRDD6
tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH6
tAS6
0
0
ns
ns
CSb
RS
Address setup time
System cycle time
tCYC6
tELR6
tEHR6
180
80
ns
ns
ns
E
Enable ”L” level pulse width
Enable ”H” level pulse width
80
Read Data delay time
Read Data hold time
tRDD6
tRDH6
ns
ns
70
CL=15pF
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
System cycle time
tCYC6
tELR6
tEHR6
180
80
ns
ns
ns
E
Enable ”L” level pulse width
Enable ”H” level pulse width
80
Read Data delay time
Read Data hold time
tRDD6
tRDH6
ns
ns
70
CL=15pF
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
Address setup time
tAH6
tAS6
0
0
ns
ns
CSb
RS
250
120
120
System cycle time
tCYC6
tELR6
tEHR6
ns
ns
ns
E
Enable ”L” level pulse width
Enable ”H” level pulse width
110
Read Data delay time
Read Data hold time
tRDD6
tRDH6
ns
ns
CL=15pF
D0 to D15
0
NOTE) Each timing is specified based on 20% and 80% of VDD
.
Ver.2004-05-12
- 96 -
NJU6825
(5) Write Operation (Serial Interface)
tCSH
tCSS
CSb
RS
tASS
tAHS
tSLW
tSHW
SCL
tCYCS
tDSS
tDHS
SDA
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
20
ns
CSb
tCSH
20
ns
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
20
ns
CSb
tCSH
20
ns
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
80
35
35
35
35
35
35
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
35
ns
CSb
tCSH
35
ns
NOTE) Each timing is specified based on 20% and 80% of VDD
.
Ver.2004-05-12
- 97 -
NJU6825
(6) Display Control Timing
CLK
tDCL
CL
tDFLM
tDFLM
FLM
tFR
FR
Output timing
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
FLM delay time
FR delay time
CL delay time
tDFLM
0
0
0
500
500
200
ns
ns
ns
FLM
FR
CL
CL=15pF
tFR
tDCL
Output timing
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
FLM delay time
FR delay time
CL delay time
tDFLM
0
0
0
1000
1000
200
ns
ns
ns
FLM
FR
CL
CL=15pF
tFR
tDCL
NOTE) Each timing is specified based on 20% and 80% of VDD
.
Ver.2004-05-12
- 98 -
NJU6825
(7) Input Clock Timing
OSC1
tCKLW
tCKHW
(VDD=1.7 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
OSC1 “H” level pulse width (1)
OSC1 “L” level pulse width (1)
OSC1 “H” level pulse width (2)
OSC1 “L” level pulse width (2)
OSC1 “H” level pulse width (3)
OSC1 “L” level pulse width (3)
tCKHW1
tCKLW1
tCKHW2
tCKLW2
tCKHW3
tCKLW3
0.555
0.555
2.46
2.46
16.9
16.9
0.800
0.800
3.54
3.54
24.4
24.4
OSC1
µs
µs
µs
µs
µs
µs
(NOTE2)
OSC1
(NOTE3)
OSC1
(NOTE4)
NOTE1) Each timing is specified based on 20% and 80% of VDD
.
NOTE2) Applied to Variable 8-/16-level grayscale mode (MON=”0”,PWM=”0”)
NOTE3) Applied to fixed 8-level grayscale mode (MON=”0”,PWM=”1”)
NOTE4) Applied to B&W mode (MON=”1”)
(8) Reset Input Timing
tRW
RESb
tR
Internal circuit
During reset
End of reset
status
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
CONDITION
MIN.
MAX.
UNIT
Terminal
Reset time
tR
1.0
µs
µs
RESb “L” level pulse width
tRW
10.0
RESb
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Terminal
Reset time
tR
1.5
µs
µs
RESb “L” level pulse width
tRW
10.0
RESb
NOTE) Each timing is specified based on 20% and 80% of VDD
.
(9) Delay Time of Gate
PARAMETER
Delay time of gate
SYMBOL
Ta=+25°C, VSS=0V, VDD=3.0V
MIN
TYP
10
MAX
UNIT
ns
Ver.2004-05-12
- 99 -
NJU6825
ꢀ INPUT/OUTPUT BLOCK DIAGRAMS
Output Block Diagram
Terminals : FLM, CL, FR, CLK
VDD
Input Block Diagram
Terminals CSb, RS, RDb, WRb, SEL68, P/S, RESb
VDD
Output control signal
Output signal
Input signal
O
I
VSS(0V)
VSS(0V
Input/Output Block Diagram
Terminals : D0 - D15
VDD
Input signal
I/O
VSS(0V)
VSS(0V)
Input control signal
VDD
Output control signal
Output signal
VSS(0V)
COM/SEG Driver Block Diagram
Terminals : SEGA0/B0/C0 – SEGA127/B127/C127, COM0 – COM161
VLCD
VLCD
VLCD
V1/V2
Output control
signal 1
Output control signal 2
Output control signal 4
O
Output control
signal 3
VSSH(0V)
VSSH(0V)
VSSH(0V)
V3/V4
Ver.2004-05-12
- 100 -
NJU6825
ꢀ MPU CONNECTIONS
Parallel Interface / 80-series MPU
1.7V - 3.3V
(NJU6825)
VCC
VDD
A0
RS
A1-A7
Decoder
8
7
(80-MPU)
CSb
D0 -D7
IORQb
D0 -D7
RDb
RDb
WRb
WRb
RESb
RESb
GND
VSS
RESET
Parallel Interface / 68-series MPU
1.7V - 3.3V
(NJU6825)
VCC
VDD
A0
RS
A1-A15
15
Decoder
8
CSb
(68-MPU)
VMA
D0 -D7
D0 -D7
E
RDb(E)
R/W
WRb (R/W)
RESb
RESb
VSS
GND
RESET
Serial Interface
1.7V - 3.3V
(NJU6825)
VCC
VDD
RS
A0
A1-A7
Decoder
RESET
7
CSb
(MPU)
PORT1
PORT2
RESb
SDA
SCL
RESb
VSS
GND
Ver.2004-05-12
- 101 -
NJU6825
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2004-05-12
- 102 -
相关型号：
NJU7001M-(TE2)
OP-AMP, 10000uV OFFSET-MAX, 0.1MHz BAND WIDTH, PDSO8, 0.250 INCH, PLASTIC, DMP-8
NJRC
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