NJU7505AM-TE2 [NJRC]
Active Filter,;
| 型号： | NJU7505AM-TE2 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Active Filter, |
| 文件： | 总8页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU7505A
BAND PASS FILTER
FOR AUDIO SPECTRUM ANALYZER DISPLAY
ꢀPACKAGE OUTLINE
ꢀGENERAL DESCRIPTION
The NJU7505A is a band pass filter for audio spectrum
analyzer display.
It consists of high and low band pass filters, CR oscillation
circuit, control circuit and DC transfer circuit.
Each band pass filter using the switched capacitor filter
technology operates at the shared time by 5 bands which
filter constant is switched by the internal clock.
Therefore, the audio signal shared of 5 bands is output
from a serial output terminal.
NJU7505AD
NJU7505AM
The 10 bands version using the double by the cascade
connection is prepared.
ꢀPIN CONFIGURATION
ꢀFEATURES
ꢁBPF for the audio spectrum analyzer display of the 5 bands
ꢁ10 bands extension is available by the cascade connection
ꢁBPF using the switched capacitor filter technology
ꢁCR oscillation circuit on chip
(External clock input is available)
ꢁPower-on initialization circuit on chip
(External reset input is available)
OSC1
OSC2
1
VDD
5
6
AIN
2
3
4
AOUT
VSS
7
8
RSTb/CLKO
RD
ꢁC-MOS Technology
ꢁPackage Outline
DIP8, DMP8
ꢀBLOCK DIAGRAM
Audio Signal
Control Signal
Clock Signal
RSTb/CLKO
RD
OSC1
Power-on
Initialize
Control Circuit
OSC
OSC2
RH
fOSC fOSC/16 fOSC/4 iH
iL RL
ΦH
ΦL
BPF
High Band
High Band
Peak Detector
Level Shifter
&
Output BUF
AOUT
AIN
Input BUF
LPF
BPF
Low Band
Low Band
Peak Detector
VDD
VDD
AGND
VSS
-
+
VSS
Ver.2008-07-30
- 1 -
NJU7505A
ꢀTERMINAL DESCRIPTION
NO.
1
SYMBOL
OSC1
FUNCTION
External Resistor connecting terminal.
2
OSC2
External Resistor connecting terminal or External clock input terminal.
Both as Reset input terminal
and the clock of (2/3)*fOSC output terminal.
RSTb/CLKO
3
4
5
6
7
8
RD
VSS
AOUT
AIN
Trigger signal for reading-out the AOUT of each band output terminal.
GND
0V
Peak voltage of each band output terminal.
Audio signal input terminal.
Positive power supply +5.0 V
VDD
ꢀPEAK FREQUENCY
The peak frequency in each band of NJU7505A are a suitable band interval which is the 5 bands at using
the single and is the 10 bands at using the double by the cascade connection.
Peak Frequency ( Hz )
Band
Using the single
Using the double
f1a
f1b
f2a
f2b
f3a
f3b
f4a
f4b
f5a
f5b
12k
12k
8k
3.5k
2.3k
1k
670
250
165
63
-
3.5k
-
1k
-
250
-
63
-
42*
Note 1) It may not be output along the expectation at the peak frequency of * marking, since the sampling
time is not enough.
Note 2) The bands of f1a, f2a, ... f5a correspond to the master side and the bands of f1b, f2b, ... f5b
correspond to the slave side at the cascade connection of the double.
The example of using the single
The example of using the double
OSC1
AOUT
OSC1
AOUT
OSC1
AOUT
f1a~f5a
f1a~f5a
f1b~f5b
NJU7505A
NJU7505A
NJU7505A
Master
Slave
fOSC
fOSC
2/3 x fOSC
OSC2
OSC2
RSTb/
CLKO
OSC2
VSS
VSS
Ver.2008-07-30
- 2 -
NJU7505A
ꢀFUNCTIONAL DESCRIPTION
• Interface to external controller
The example of the interface between the NJU7505A and the external controller is shown below;
(1) Example of the interface to the external controller ( Using the single )
After the RSTb signal from the external controller is input and then the internal circuit is initialized, each
band data is output as shown below timing chart;
Since the RD signal is output before each band is switched, the external controller is to count the number of
the RD signal and is to recognize the status of the band and is to read the output data from the AOUT terminal
through the external A/D converter.
The output type of the external controller connected to the RSTb/CLKO terminal as the RSTb input should
be the N-channel and open-drain type or the diode should be connected between the RSTb/CLKO terminal
and the output terminal of the external controller, so that the voltage of the RSTb/CLKO terminal is not gotten
over the VSS level.
AIN
OSC1
NJU7505A
AOUT
OSC2
A / D
Converter
fOSC
RD
RSTb/
CLKO
VSS
µ CON
3 x 214 / fosc
AOUT
RD
f1
f2
f3
f5
f5
f1
f1
f2
f4
f4
f3
f3
f1
f1
f2
f3
f1
f2
f3
f2
f1
f2
RSTb
248 / fOSC
AOUT
RD
Since the RD signal is output before 248/fOSC
of each band switched, the output data should
be read out within the limited time as shown
right;
8 / fOSC
Available Period
of Read-out
AOUT
fn
f1
If the RSTb signal which pulse width is
more than 4/fOSC is input, the internal circuit is
initialized and the data of f1 band is output from
the AOUT terminal after 52/fOSC of the rise edge
of the RSTb signal.
4 / fOSC[MIN]
52 / fOSC
RSTb
Ver.2008-07-30
- 3 -
NJU7505A
(2) Example of the interface to the external controller (Using the double)
The 10 bands application is available using the cascade connection of the double NJU7505A as shown
blow.
After the RSTb signals from the external controller are input to each of the master and the slave of the
NJU7505A and then each internal circuit is initialized, each band data is output as shown below timing chart;
Since the RD signals are output from the master and the slave before each band is switched, the external
controller is to count the number of the RD signals and is to recognize the status of the band and is to read
the output data from each AOUT terminals through the external A/D converter.
The master clock for the slave is provided with the output signal from the RSTb/CLKO terminal of the
master. The master clock for the slave is stopped when the RSTb signal is input from the external controller
to the master, so that the RSTb/CLKO terminal of the master is used both as the RSTb input of the master
and the master clock for the slave.
The output type of the external controller connected to each RSTb/CLKO terminal as the RSTb input should
be the N-channel and open-drain type or the diode's should be connected between each RSTb/CLKO
terminal and the output terminals of the external controller, so that the voltage of each RSTb/CLKO terminal
is not gotten over the VSS level.
AIN
AIN
OSC1
OSC2
OSC2
NJU7505A
Slave
NJU7505A
Master
AOUT
AOUT
A / D
Converter
RD
RD
RSTb/
CLKO
RSTb/
CLKO
VSS
µ CON
3 x 214 / fosc
f3 f5
f5
Master
AOUT
f1
f2
f1
f1
f2
f2
f4
f4
f3
f3
f1
f2
f3
f1
f2
f1
f2
f3
f1
f2
f3
f3
f1
RD
RSTb
3 x 214 / fosc x 3/2
f3
Slave
AOUT
f1
f2
f5
f5
f1
f2
f4
f4
f3
f1
f2
f1
f2
f3
f1
f2
f1
RD
RSTb
248 / fOSC
(248 / fOSC x 3/2)
Since each RD signal of the master and the slave is
output before 248/fOSC (248/fOSC*3/2) of each band
switched, the output data should be read out within
the limited time as shown right;
AOUT
RD
8 / fOSC
(8 / fOSC x 3/2)
Available Period
of Read-out
* The "( )" is corresponded to the slave.
If the RSTb signal which pulse width is more than
4/fOSC is input to the master, the internal circuit is
initialized and the data of f1 band is output from the
AOUT terminal of the master after 52/fOSC of the rise
edge of the RSTb signal.
The RSTb signal for the slave should be set to "L"
level while the RSTb signal for the master is "L" level
and should keep "L" level more than 6/fOSC. So the
slave operates as same as the master after 78/fOSC of
the rise edge of the RSTb signal for the slave.
AOUT
fn
f1
4 / fOSC[MIN]
52 / fOSC
RSTb
RSTb
6 / fOSC
78 / fOSC
[MIN]
AOUT
fn'
f1’
Ver.2008-07-30
- 4 -
NJU7505A
ꢀABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
NOTE
PARAMETER
Supply Voltage
SYMBOL
RATINGS
UNIT
V
VDD
VIN
VIO
-0.3 to +7
-0.3 to VDD+0.3
-0.3 to 0
7
5, 8
Input Voltage
V
Output Voltage
Power Dissipation
Operating
Temperature
Storage Temperature
VOUT
PD
-0.3 to VDD+0.3
500(DIP), 300(DMP)
V
mW
Topr
Tstg
-30 to 85
°C
°C
-55 to 125
Note 3) If the IC are used on condition above the absolute maximum ratings, the IC may be destroyed. Using
the IC within electric characteristic conditions will cause malfunction and poor reliability.
Note 4) All voltage values are specified as VSS = 0V.
Note 5) When the voltage of the RSTb/CLKO terminal is gotten over the VSS level, the diode should be
connected between the RSTb/CLKO terminal and the external.
Note 6) Decoupling capacitor should be connected between the VDD terminal and the VSS due to the
stabilization of the operation.
Note 7) Applied to the AIN or the OSC2 terminals.
Note 8) Applied to the RSTb/CLKO terminal.
ꢀDC CHARACTERISTICS
(VDD=5V, VSS= 0V, Ta=25°C)
PARAMETER
Operating Voltage
Operating Current
SYMBOL
VDD
CONDITITONS
MIN
4.5
-
-0.1
0.033
-0.2
0
3.5
0
4.5
0
TYP
5.0
6.0
-0.05 -0.033
0.05
-0.1
-
-
-
MAX UNIT NOTE
6.0
V
IDD
IIL1
IIH1
IIL2
VILC
VIHC
VOL1
VOH1
VOL2
VOH2
VOS
VDD Terminal
AIN Terminal
12.0
mA
VIL1=0V
VIH1=5V
Input Leak Current 1
mA
mA
V
0.1
-0.05
1.5
5.0
0.5
5.0
0.5
4.75
300
-
Input Leak Current 2
External Clock
Input Voltage
RSTb/CLKO Terminal VIH2=0V
OSC2 Terminal
IOL1=100µA
RD Terminal
Output Voltage 1
V
V
IOH1=-100µA
-
RSTb/CLKO
Terminal
IOL1=100µA
IOH1=-5µA
AIN:OPEN
-
4.5
-
26.0
-
Output Voltage 2
4.25
-
-
Output Offset Voltage
BPF Output Voltage
AOUT Terminal
mV
dB
V
9,10,11
9,10
A
OUT Terminal Sine Wave Input
fIN=f1 to f5 VIN=200mVp
VOUT
3.5
-
Note 9) This specification is tested on condition of fCLK=400kHz (The external clock is input to the OSC2
terminal through the capacitor for AC coupling.
Note 10) Each input frequency of f1 to f5 is referred to the table of the " PEAK FREQUENCY ".
Note 11) This specification is calculated from " VOUT / VIN ".
Ver.2008-07-30
- 5 -
NJU7505A
ꢀAC CHARACTERISTICS
( VDD=4.5 ~ 6.0V, VSS=0V, Ta=25°C)
PARAMETER
SYMBOL
fOSC
CONDITIONS
RSTb/CLKO Terminal
VDD=5V
MIN
360
TYP
MAX
UNIT NOTE
Oscillation Clock Freq
400
440
kHz
12
RSTb/CLKO Terminal
VILC=0V
External Clock Frequency
RD Pulse Width
fCLK
400
800
kHz
13
VIHC=VDD
8/fOSC
8/fCLK
12/fOSC
12/fCLK
Master
Slave
tPWRD
RD Terminal
µs
14
4/fOSC
4/fCLK
6/fOSC
6/fCLK
Master
Slave
RSTb/CLKO
Terminal
RSTb Pulse Width
tPWRS
µs
µs
15
15
RSTb Rise/Fall Time
tr, tf
RSTb/CLKO Terminal
100
Note 12) The example for the CR Oscillation
OSC1
RT: 13kΩ(±2%)
CT: 220pF(±5%)
RT
OSC2
CT
*The oscillation clock frequency is calculated from the
output frequency of the RSTb/CLKO terminal by 3/2.
VSS
Note 13) The example for the external clock input
The input signal for the OSC2 terminal should be the
Open
OSC1
condition of the pulse of DUTY50%±10%.
* The oscillation clock frequency is calculated
from the output frequency of the RSTb/CLKO terminal by 3/2.
OSC2
Oscillator
Note 14) The output wave form of the RD terminal.
0.8VDD
0.8VDD
tPWRD
Note 15) The input wave form of the RSTb terminal.
tf
tPWRS
tr
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Ver.2008-07-30
- 6 -
NJU7505A
ꢀAPPLICATION CIRCUIT (1)
AUDIO IN
AUDIO IN
Rch
Lch
–
+
–
+
AUDIO OUT
AUDIO OUT
NJU7305
or
RESONANCE
CIRCUIT
RESONANCE
CIRCUIT
NJU7306
*1
ATT
AIN
*2
OSC1
OSC1
13kΩ
NJU7505A
220pF
RSTb/
CLKO
RD
AOUT
*3
A/D
µ CON
DISPLAY DRIVER
DISPLAY
*1 ) The capacitor for AC coupling connected to the AIN terminal should be needed.
*2 ) Connecting the attenuator, the dynamic range of the display can be changed.
*3 ) When the voltage of the output terminal of the µCON gets over the VSS level, the diode should be connected
between the RSTb/CLKO terminal and the output of the µCON.
Ver.2008-07-30
- 7 -
NJU7505A
ꢀAPPLICATION CIRCUIT (2)
AUDIO IN
AUDIO IN
Rch
Lch
–
+
–
+
AUDIO OUT
AUDIO OUT
NJU7305
or
NJU7306
RESONANCE
CIRCUIT
RESONANCE
CIRCUIT
*1
ATT
*2
ATT
*2
AIN
AIN
OSC1
13kΩ
OSC2
OSC2
RD
NJU7505A
NJU7505A
220pF
RD
RSTb/
CLKO
RSTb/
CLKO
AOUT
AOUT
*3
*3
A/D
A/D
µ CON
DISPLAY DRIVER
DISPLAY
*1 ) The capacitor for AC coupling connected to the AIN terminal should be needed.
*2 ) Connecting the attenuator, the dynamic range of the display can be changed.
*3 ) When the voltage of the output terminal of the µCON gets over the VSS level, the
diode should be connected between the RSTb/CLKO terminal and the output of
the µCON.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2008-07-30
- 8 -
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