NJU7706F39A1 [NJRC]
Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO5, SOT-23, 5 PIN;
| 型号： | NJU7706F39A1 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDSO5, SOT-23, 5 PIN ISM频段 光电二极管 |
| 文件： | 总10页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU7706/07
VOLTAGE DETECTOR
ꢀ GENERAL DESCRIPTION
ꢀ PACKAGE OUTLINE
The NJU7706/07 is a high precision voltage detector with a
built-in delay time generator of fixed time.
The NJU7706/07 is useful for preventing malfunction of
microprocessor or DSP through monitoring power supply voltage.
The delay function achieves set wait time when supply voltage
is unstable. Moreover, the delay function can make a sequence
that other devices in application work and stabilize before
microcomputer or DSP works.
NJU7706/07F
The detection voltage is internally fixed with an accuracy of 1.0%,
and three fixed delay times 50ms, 100ms and 200ms are
available. Manual reset function can output reset signal
irrespective of detection voltage.
NJU7706 is Nch. Open Drain and NJU7707 is a C-MOS output
type.
Small packaging makes NJU7706 and NJU7707 suitable for
space conscious applications.
ꢀ FEATURES
ꢁ High Precision Detection Voltage ±1.0%
ꢁ Low Quiescent Current
1.3µA typ.
ꢁ Detection Voltage Range
ꢁ Delay Time(Built-in Fixed Type)
1.5 6.0V(0.1V step)
50ms /100ms /200ms(Built-in Fixed Type)
ꢁ ON/OFF switch of delay time(DSW pin)
ꢁ Manual Reset
Active “L” : NJU770*F**A
Active "H" : NJU770*F**B
NJU7706: Nch. Open Drain type
NJU7707: C-MOS Output type
SOT-23-5
ꢁ Output Configuration
ꢁ Package Outline
ꢀ PIN CONFIGURATION
PIN FUNCTION
5
4
1.DSW
2.VSS
3.MR
4.VOUT
5.VDD
1
2
3
NJU7706/07F
Ver.2007-08-03
- 1 -
NJU7706/07
ꢀ EQUIVALENT CIRCUIT
VDD
VDD
VOUT
VOUT
DelayCircuit
DelayCircuit
Vref
Vref
VSS
VSS
DSW
MR
DSW
MR
NJU7706**A*
NJU7706**B*
VDD
VDD
VOUT
DelayCircuit
VOUT
DelayCircuit
Vref
Vref
VSS
VSS
DSW
MR
DSW
MR
NJU7707**A*
NJU7707**B*
Ver.2007-08-03
- 2 -
NJU7706/07
ꢀ DETECTION VOLTAGE RANK LIST
Device Name
NJU770*F25A1
NJU770*F26A1
NJU770*F27A1
NJU770*F28A1
NJU770*F29A1
NJU770*F03A1
NJU770*F39A1
NJU770*F42A1
NJU770*F27B1
NJU770*F15A2
NJU770*F18A2
NJU770*F19A2
NJU770*F21A2
NJU770*F22A2
NJU770*F25A2
NJU770*F27A2
NJU770*F28A2
NJU770*F29A2
NJU770*F03A2
NJU770*F31A2
NJU770*F39A2
NJU770*F04A2
NJU770*F42A2
NJU770*F43A2
NJU770*F45A2
NJU770*F46A2
NJU770*F06A2
NJU770*F25B2
NJU770*F27B2
NJU770*F42B2
NJU770*F27A3
NJU770*F39A3
NJU770*F42A3
NJU770*F27B3
VDET
2.5V
2.6V
2.7V
2.8V
2.9V
3.0V
3.9V
4.2V
2.7V
1.5V
1.8V
1.9V
2.1V
2.2V
2.5V
2.7V
2.8V
2.9V
3.0V
3.1V
3.9V
4.0V
4.2V
4.3V
4.5V
4.6V
6.0V
2.5V
2.7V
4.2V
2.7V
3.9V
4.2V
2.7V
MR Logic
Active “L”
Active “H”
Delay Time
50ms
Active “L”
100ms
Active “H”
Active “L”
Active “H”
200ms
Ver.2007-08-03
- 3 -
NJU7706/07
ꢀ NJU7706
ꢀABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
UNIT
PARAMETER
Input Voltage
Output Voltage
Input Voltage of DSW pin
Input Voltage of MR pin
Output Current
SYMBOL
RATINGS
+10
VDD
VOUT
VDSW
VMR
V
V
VSS-0.3 +10
VSS-0.3 VDD+0.3
VSS-0.3 VDD+0.3
50
V
V
IOUT
mA
350(*1)
200(*2)
-40 +85
-40 +125
Power Dissipation
PD
SOT-23-5
mW
Operating Temperature
Storage Temperature
Topr
Tstg
°C
°C
(*1) : Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers)
(*2) : Device itself
ꢀ ELECTRICALCHARACTERISTICS
(Ta=25°C)
PARAMETER
Detection Voltage
Hysteresis Voltage
SYMBOL
VDET
TEST CONDITION
MIN.
-1.0%
70
−
−
0.75
4.5
−
TYP. MAX. UNIT
+1.0%
130
1.7
V
mV
−
VHYS
90
1.0
1.3
2.0
7.0
−
VDET=1.5V 1.9V Version
VDET=2.0V 6.0V Version
VDD=1.2V
Quiescent Current
Output Current
ISS
VDD=VDET+1V
µA
2.2
−
−
0.1
IOUT
Nch,VDS=0.5V
VDD=VOUT=9V
mA
VDD=2.4V (≥2.7V Version)
Output Leak Current
Detection Voltage
Temperature
ILEAK
µA
∆ VDET /∆Ta Ta=0 +85°C
−
±100
−
ppm/°C
Coefficient
NJU7706F***1
NJU7706F***2
NJU7706F***3
42.5
85
170
25
1.5
0
1.5
0
50
100
200
100
−
−
−
−
−
57.5
115
230
300
VDD
0.3
VDD
0.3
VDD
ms
ms
ms
µs
V
V
V
V
V
VDD=VDET+1V,
td1
Delay Time 1
DSW=”L Level”
Delay Time 2
Input Voltage of
DSW pin
td2
VDD=VDET+1V, DSW=”H Level”
VDSW_H
VDSW_L
VMR_H
VMR_L
VMR_H
VMR_L
Input Voltage of
MR pin (Active “L”)
VDD-0.3
0
Input Voltage of
MR pin (Active “H”)
VDD-1.5
V
−
Impedance of
MR pin
Operating Voltage
(*3)
RMR
VDD
1.0
0.8
2.0
3.0
9
MΩ
V
RL=100kΩ
−
(*3): The minimum operating voltage(VOPL) indicates the same value of the input voltage(VDD) on condition that VOUT
becomes 10% or less of the input voltage(VDD).
Ver.2007-08-03
- 4 -
NJU7706/07
ꢀ TEST CIRCUIT
ꢁ Circuit Operating Current TEST CIRCUIT
ꢁ Detection voltage / Minimum operating voltage
TEST CIRCUIT
A
Iss
RL
VDD
VDD
VOUT
VOUT
MR
NJU7706
NJU7706
VDD
VOUT
V
VDD
VDET
VOPL
/
V
MR
DSW
DSW
VSS
VSS
ꢁ MR pin Input voltage TEST CIRCUIT
ꢁ Leak current / Output current TEST CIRCUIT
RL
ILEAK / IOUT
VDD
VDD
A
VOUT
MR
VOUT
NJU7706
NJU7706
VDD
VDD
VOUT
V
MR
DSW
VOUT/ VDS
DSW
VSS
VSS
VMR
V
VMR
ꢁ Delay time1TESTCIRCUIT
ꢁ Delay time2 TEST CIRCUIT
Oscilloscope
Oscilloscope
ch1 ch2
ch1 ch2
RL
RL
VDD
VDD
VOUT
VOUT
NJU7706
NJU7706
VDD
VDD
MR
MR
DSW
VSS
DSW
VSS
Ver.2007-08-03
- 5 -
NJU7706/07
ꢀ TYPICALAPPLICATION
1 Power Supply Monitor Circuit (VDD line COMMON)
VDD
RL
VDD
Reset Signal
VOUT
MR
INPUT
NJU7706
Micro-Processor
etc.
DSW
VSS
2 Power Supply Monitor Circuit (VDD line SEPARATE)
VDD1
VDD2
RL
VDD
Reset Signal
INPUT
VOUT
MR
NJU7706
Micro-Processor
etc.
DSW
VSS
Ver.2007-08-03
- 6 -
NJU7706/07
ꢀ NJU7707
ꢀABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER
Input Voltage
Output Voltage
Input Voltage of DSW pin
Input Voltage of MR pin
Output Current
SYMBOL
RATINGS
+10
VSS-0.3 VDD+0.3
VSS-0.3 VDD+0.3
VSS-0.3 VDD+0.3
50
UNIT
V
V
V
V
VDD
VOUT
VDSW
VMR
IOUT
mA
350(*4)
200(*5)
Power Dissipation
PD
SOT-23-5
mW
Operating Temperature
Storage Temperature
Topr
Tstg
-40 +85
-40 +125
°C
°C
(*4) : Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers)
(*5) : Device itself
ꢀ ELECTRICALCHARACTERISTICS
(Ta=25°C)
PARAMETER
Detection Voltage
Hysteresis Voltage
SYMBOL
VDET
TEST CONDITION
MIN.
-1.0%
70
−
−
0.75
4.5
2.0
TYP. MAX. UNIT
+1.0%
130
1.7
2.2
−
V
mV
−
90
VHYS
1.0
1.3
2.0
7.0
3.5
VDET=1.5V 1.9V Version
Quiescent Current
ISS
VDD=VDET+1V
Nch, VDS=0.5V
µA
VDET=2.0V 6.0V Version
VDD=1.2V
VDD=2.4V (≥2.7V Version)
VDD=4.8V (≤3.9V Version)
VDD=6.0V
−
−
Output Current
IOUT
mA
Pch, VDS=0.5V
2.5
3.0
4.0
5.0
−
−
(4.0V 5.6V Version)
VDD=8.4V (≥5.7V Version)
Detection Voltage
Temperature
Coefficient
∆ VDET /∆Ta Ta=0 +85°C
−
±100
−
ppm/°C
NJU7707F***1
NJU7707F***2
NJU7707F***3
42.5
85
170
25
1.5
0
1.5
0
50
100
200
50
−
−
−
−
−
57.5
115
230
300
VDD
0.3
VDD
0.3
VDD
ms
ms
ms
µs
V
V
V
V
V
VDD=VDET+1V,
td1
Delay Time 1
DSW=”L Level”
Delay Time 2
Input Voltage of
DSW pin
td2
VDD=VDET+1V, DSW=”H Level”
VDSW_H
VDSW_L
VMR_H
VMR_L
VMR_H
VMR_L
Input Voltage of
MR pin (Active “L”)
VDD-0.3
0
Input Voltage of
MR pin (Active “H”)
VDD-1.5
V
−
Impedance of
MR pin
Operating Voltage
(*6)
RMR
VDD
1.0
0.8
2.0
3.0
9
MΩ
V
RL=100kΩ
−
(*6): The minimum operating voltage(VOPL) indicates the same value of the input voltage(VDD) on condition that VOUT
becomes 10% or less of the input voltage(VDD).
Ver.2007-08-03
- 7 -
NJU7706/07
ꢀ TEST CIRCUIT
ꢁ Circuit Operating Current TEST CIRCUIT
ꢁ Detection voltage TEST CIRCUIT
A
Iss
VDD
VDD
VOUT
VOUT
MR
NJU7707
NJU7707
VDD
VOUT
V
VDD
VDET
V
MR
DSW
DSW
VSS
VSS
ꢁ Nch Output current TEST CIRCUIT
ꢁ Pch Output current TEST CIRCUIT
VDS
IOUT
IOUT
VDD
VDD
A
A
VOUT
MR
VOUT
NJU7707
NJU7707
VDD
VDD
DSW
MR
DSW
VDS
VSS
VSS
ꢁ MR pin Input voltage TEST CIRCUIT
ꢁ Minimum operating voltage TEST CIRCUIT
RL
VDD
VDD
VOUT
VOUT
NJU7707
V
NJU7707
VDD
VDD
VOUT
VOUT
VOPL
V
V
MR
MR
DSW
DSW
VSS
VSS
VMR
V
VMR
Ver.2007-08-03
- 8 -
NJU7706/07
ꢁ Delay time1TESTCIRCUIT
ꢁ Delay time2 TEST CIRCUIT
Oscilloscope
Oscilloscope
ch1 ch2
ch1 ch2
VDD
VDD
VOUT
MR
VOUT
MR
NJU7707
NJU7707
VDD
VDD
DSW
VSS
DSW
VSS
ꢀ TYPICALAPPLICATION
1 Power Supply Monitor Circuit (VDD line COMMON)
VDD
VDD
Reset Signal
VOUT
MR
INPUT
NJU7707
Micro-Processor
etc.
DSW
VSS
Ver.2007-08-03
- 9 -
NJU7706/07
ꢀ Functional Description
(1) Basic operation
Supply voltage
(VDD)
(1) When supply voltage(VDD) drops below
detection voltage(VDET), Output voltage(VOUT
Hysteresis voltage
(VHYS
)
)
Release voltage
changes "H" to "L" to alert reset state.
(2) The reset state is kept while VDD is lower than
release voltage. The release voltage is a sum
of VDET and Hysterisis voltage (VHYS). Please
refer to the (*7) below.
(VDET + VHYS
)
Detection voltage
(VDET
)
Minimum operation
voltage (VOPL
)
VSS
(3) When VDD becomes higher than the release
voltage and reset release delay time fixed by
internal is past, then VOUT changes from "L" to
"H" to resume normal state.
Output voltage
(VOUT
)
(*7) VHYS is to avoid unstable VOUT state caused
by rapid voltage change at nearby VDET
.
VSS
Delaytime
(*8): C-MOS output product (NJU7707) : When VDD less than VOPL, VOUT is free of the shaded region.
(2) Description of Manual Reset
Reset signal can output independently with MR.
Logic of MR
Active "L"
Active "H"
Operation
VMR= "L" => Reset "ON"
VMR= "H" => Reset "ON"
If Manual Reset is not required, please connect MR terminal as following.
Logic of MR
Active "L"
Active "H"
Connection
Connect MR terminal to VDD or open
Connect MR terminal to GNDor open
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2007-08-03
- 10 -
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