NJW1340V [NJRC]
Audio/Video Switch, 1 Func, 3 Channel, BICMOS, PDSO32, SSOP-32;
| 型号： | NJW1340V |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Audio/Video Switch, 1 Func, 3 Channel, BICMOS, PDSO32, SSOP-32 信息通信管理 光电二极管 |
| 文件： | 总12页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW1340
VIDEO SWITCH FOR DVD RECORDER
Q GENERAL DESCRIPTION
Q PACKAGE OUTLINE
The NJW1340 is a video switch for DVD recorders corresponding to
the composite signal and Y/C signal.
It contains synchronous separation circuit and synchronous signal
detection circuit, which are operating constantly. Therefore, It can detect
a signal at the state of power save mode.
NJW1340V
Q FEATURES
O Operating Voltage
4.5 to 5.5V
O I2C BUS Interface
O 5-input 1-output video switch
O 3-input 1-output 2-circuit video switch
O 6th order Low Pass Filter
O Internal synchronous separation circuit
O Internal synchronous signal detection circuit
O Power Save Circuit
O Bi-CMOS Technology
O Package Outline
SSOP32
Q BLOCK DIAGRAM
ADDRESS SDA
SCL
26
28
27
I2C BUS
1
2
C IN 1
BIAS
VCC 1
C IN 2
3
31
OUT 2
LPF
LPF
BIAS
4
Power Save
5
C IN 3
GND
BIAS
6
30
29
GND
7
Y IN 1
GND
CLAMP
CLAMP
CLAMP
CLAMP
CLAMP
CLAMP
CLAMP
CLAMP
8
9
Y IN 2
GND
OUT 1
10
11
12
13
14
15
Y IN 3
GND
CVBS IN 1
GND
CVBS IN 2
DET SW
16
17
18
19
20
21
CVBS IN 3
GND
CVBS IN 4
VCC 2
CVBS IN 5
Sync
Sepa
Sync
Detect
32
DET OUT
25
24
23
22
CLAMP
CLAMP
Ver.6
- 1 -
NJW1340
Q ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
PARAMETER
Supply Voltage
SYMBOL
V+
RATINGS
7.0
UNIT
V
Power Dissipation
Operating Temperature Range
Storage Temperature Range
PD
Topr
Tstg
800(note1)
-40 to +85
-40 to +125
mW
°C
°C
(Note1) At on a board of EIA/JEDEC specification. (76.2 × 114.3 × 1.6mm Two layers, FR-4)
Q RECOMMENDED OPEARATING CONDITION(Ta=25°C)
PARAMETER
SYMBOL
Vopr
TEST CONDITION
MIN.
4.5
TYP. MAX. UNIT
5.0 5.5
Operating Voltage
V
Q ELECTRICAL CHARACTERISTICS (V+=5.0V, RL=10KΩ, Ta=25°C)
PARAMETER
SYMBOL
Icc
TEST CONDITION
MIN.
-
TYP. MAX. UNIT
Operating Current
Operating Current
at Power Save
Maximum
13.0
17.0
No signal
mA
Isave
Vom1
Power Save
-
5.0
6.5
mA
CLAMP Channel
Vin=100kHz, 1.0Vp-p Sin signal, THD=1%
1.6
2.6
-
Vp-p
Output Voltage 1
Maximum
BIAS Channel
Vin=100kHz, 1.0Vp-p Sin signal, THD=1%
Vin=1MHz, 1.0Vp-p Sin signal
Vom2
Gv
1.6
-0.5
-0.5
2.9
0.0
0.0
-
Vp-p
dB
Output Voltage 2
Voltage Gain
Frequency
Characteristic 1
Frequency
Characteristic 2
Cross talk 1
Cross talk 2
Differential Gain
Differential Phase
S/N
Sync Detection Level
Capture Voltage H
Capture Voltage L
Lock Voltage H
Lock Voltage L
DET OUT
0.5
0.5
Gf1
Vin=6MHz / 100kHz, 1.0Vp-p Sin signal
Vin=27MHz / 100kHz, 1.0Vp-p Sin signal
dB
Gf2
-
-40
-24
dB
CTI
CTB
DG
Vin=4.43MHz,1.0Vp-p Sin signal
Vin=4.43MHz,1.0Vp-p Sin signal
Vin=1.0Vp-p 10step Video signal
Vin=1.0Vp-p 10step Video signal
Vin=1.0Vp-p,100% White Video Signal
Vin=10step Video signal
(Note2)
-
-
-
-
-
-70
-70
0.5
0.5
65
-
-
-
-
-
dB
dB
%
deg
dB
mVp-p
V
DP
SNv
VSYNC
VCAPH
VCAPL
-
80
-
2.07
1.57
2.53
1.25
2.22
1.72
2.68
1.40
2.37
1.87
2.83
1.55
(Note2)
V
V
V
VLOCKH (Note2)
VLOCKL
(Note2)
DetH
4.9
-
5.0
0.1
-
-
V
V
V
V
Output Voltage H
DET OUT
DetL
VthH
VthL
0.3
V+
Output Voltage L
Switch Change
Voltage H
Switch Change
Voltage L
2.0
0
-
0.6
ADR Voltage H
ADR Voltage L
Power Save SW
Inflow Current H
Power Save SW
Inflow Current L
DET SW
Inflow Current H
DET SW
Inflow Current L
VADRH
VADRL
3.5
0
-
-
5.0
1.0
V
V
ISWPH
ISWPL
IDETH
IDETL
V=5V
150
4.0
80
220
7.0
110
2.0
300
11.0
150
6.0
µA
µA
µA
µA
V=0.3V
V=5V
V=0.3V
0.2
- 2 -
NJW1340
Q MODE SWITCH FUNCTON
Power Save
Mode
5V
(Note2)
H
L
OPEN
Video switch block Power Save OFF (Active)
Video switch block Power Save ON (Mute)
Video switch block Power Save ON (Mute)
VLOCKH
VCAPH
VCAPL
DET SW
Mode
Y IN 1Select
CVBS IN 1 Select
CVBS IN 1 Select
VLOCKL
H
L
OPEN
0V
Lock Range
Capture Range
- 3 -
NJW1340
TIMING ON THE I2C BUS (SDA,SCL)
SDA
tBUF
tr
tf
tr
tf
tHD:STA
tSP
tSU:DAT
SCL
tHD:STA
tSU:STA
tSU:STO
tLOW
tHIGH
tHD:DAT
S
S
Sr
P
CHARACTERISTICS OF I/O STAGES FOR I2C BUS (SDA,SCL)
I2C BUS Load Conditions
STANDARD MODE: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
Standard mode
PARAMETER
SYMBOL
UNIT
MIN.
0.0
3.0
0
TYP. MAX.
Low Level Input Voltage
VIL
VIH
VOL
-
-
-
1.5
5.0
0.4
V
V
V
High Level Input Voltage
Low level output voltage (3mA at SDA pin)
Input current each I/O pin with an input voltage
between 0.1VDD and 0.9VDDmax
Ii
-10
-
10
µA
- 4 -
NJW1340
CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I2C-BUS DEVICES
Standard mode
PARAMETER
SYMBOL
UNIT
MIN.
TYP. MAX.
SCL clock frequency
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
-
4.0
4.7
4.0
4.7
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
V
Hold time (repeated) START condition.
Low period of the SCL clock
-
-
High period of the SCL clock
-
Set-up time for a repeated START condition
Data hold time NOTE)
-
-
Data set-up time
250
-
-
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the Low level
1000
tf
-
300
tSU:STO
tBUF
4.0
4.7
-
-
-
Cb
400
VnL
0.5
1
-
-
Noise margin at the High level
VnH
V
Cb ; total capacitance of one bus line in pF.
NOTE). Data hold time : tHD:DAT
Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge.
The SDA block in the NJW1340 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not
providing a hold time of at least 300nsec for the SDA in the master device.
The time-consists of the data-delay-circuit of the SDA terminal are as follows.
(a) Low level Æ High level: TLH ≈ RP*CD
(b) High level Æ Low level: THL ≈ RD*CD
In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward voltage
(Vf) as much as possible.
VDD
RP
RP
SCL
SDA
SBD
MASTER
NJW1340
RD
CD
- 5 -
NJW1340
I2C BUS FORMAT
MSB
LSB
MSB
LSB
MSB
LSB
Slave Address
S
A
Data
8bit
A
Data
8bit
A
P
1bit
8bit
1bit
1bit
1bit 1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
♦SLAVE ADDRESS
R/W: Set the Write Mode or Read Mode.
ADR : Set the Slave Address by “ADR” terminal.
Slave Address
Hex
MSB
LSB
-
-
1
0
0
0
0
0
ADR
R/W
X R/W = 0 : Write Mode, ADR = 0/1
-
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
0
94(h)
96(h)
-
X R/W = 1 : Read Mode, ADR = 0/1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
1
1
95(h)
97(h)
♦CONTROL REGISTER TABLE
BIT
No.
D4
D3
D2
D1
D0
D7
D6
D5
Data
SEL SW1 SEL SW2 SEL SW3
7
7
7
7
7
7 : Don’t Care
♦CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
BIT
No.
D4
0
D3
0
D2
0
D1
0
D0
0
D7
0
D6
0
D5
0
Data
INSTRUCTION CODE
SEL SW1
SEL SW2
SEL SW3
OUT1
OUT2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CVBS IN1
CVBS IN2
CVBS IN3
CVBS IN4
CVBS IN5
Y IN 1
C IN 1
C IN 1
C IN 1
C IN 1
C IN 1
C IN 1
C IN 2
C IN 3
Y IN 2
Y IN 3
- 6 -
NJW1340
EQUIVALENT CIRCUIT
No.
SYMBOL
FUNCTION
INSIDE EQUIVALENT CIRCUIT
VOLTAGE
Chroma signal input
20kΩ
200Ω
1
3
5
CIN1
CIN2
CIN3
2.8V
Y signal input,
YIN1 correspond to the
synchronous detection at
the power saving mode.
7
9
11
YIN1
YIN2
YIN3
200Ω
Composite video signal
input,
13
15
17
19
21
CVBSIN1
CVBSIN2
CVBSIN3
CVBSIN4
CVBSIN5
2.5V
CVBSIN1 correspond to
the synchronous detection
at the power saving mode.
Power Save control
16kΩ
34kΩ
POWER
SAVE
4
Signal detection control, Y
IN1 or CVBS IN1
8kΩ
16
DETSW
40kΩ
- 7 -
NJW1340
No.
SYMBOL
FUNCTION
INSIDE EQUIVALENT CIRCUIT
VOLTAGE
Capacitor connection for
smoothing mono multi.
10kΩ
200Ω
22
MMINTEG
Capacitor and resistance
connection for mono multi
time constant.
The accuracy of external
resistance recommends
within ±5%.
200Ω
23
MMTC
32KΩ
Capacitor connection for
CLAMP
24
CLAMP
0.9V
225Ω
Capacitor connection for
CLAMP
25
CLAMP
1.3V
200Ω
48KΩ
- 8 -
NJW1340
No.
26
SYMBOL
FUNCTION
I2C clock
INSIDE EQUIVALENT CIRCUIT
VOLTAGE
4kΩ
SCL
I2C data
4kΩ
27
SDA
Slave address setting
66Ω
28
ADDRESS
Composite video signal, Y
signal output
Chroma signal output
29
31
OUT1
OUT2
0.9V
2.0V
56Ω
- 9 -
NJW1340
No.
SYMBOL
FUNCTION
INSIDE EQUIVALENT CIRCUIT
VOLTAGE
Detection signal output.
The synchronous detection
result output at the power
saving mode.
100KΩ
29
DETOUT
GND
6
8
10
12
14
18
30
GND
Vcc
VCC1
VCC2
20
- 10 -
NJW1340
TEST CIRCUIT
OUT2
GND
OUT1
ADDRESS SDA
SCL
CLAMP
MMTC
MMINTEG CVBSIN5
VCC2
CVBSIN4 GND CVBSIN3
DETOUT
3.3µF
1nF
50kΩ
1µF
+
+
10kΩ
10kΩ
75Ω
75Ω
75Ω
1µF
1µF
1µF
10µF
10µF
+
+
+
+
+
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+
+
+
+
+
+
+
+
0.1µF
0.1µF
0.1µF
1µF
1µF
1µF
1µF
1µF
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
POWER
SAVE
CIN1
VCC1
CIN2
CIN3
GND
YIN1
YIN2
YIN3
CVBSIN1
CVBSIN2
DETSW
(Note) It the following refers when the synchronous signal detection unused.
16pin DETSW
OPEN
22pin MMINTEG OPEN
23pin MMTC
24pin CLAMP
25pin CLAMP
32pin DETOUT
OPEN
OPEN
OPEN
OPEN
- 11 -
NJW1340
QTYPICAL CHARACTERISTICS
Voltage Gain vs Frequency
0
-10
-20
-30
-40
-50
105
106
107
Freq [MHz]
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 12 -
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NJRC
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