NJW4160R-TE1 [NJRC]
Switching Regulator/Controller,;
| 型号： | NJW4160R-TE1 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Switching Regulator/Controller, |
| 文件： | 总22页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW4160
Switching Regulator IC for Buck Converter
External MOSFET driving
ꢀGENERAL DESCRIPTION
■ PACKAGE OUTLINE
The NJW4160 is switching regulator a buck converter that
operates wide input range from 3V to 35V. Because a highly
effective Pch MOSFET drive circuit is built-in, a large current
application can be achieved.
NJW4160R
(MSOP8(VSP8))
NJW4160M
(DMP8)
Pulse-by-pulse type over current protection circuit limits output
current when over current situations.
It is suitable for logic voltage generation from high voltage that
Car Accessory, Office Automation Equipment, Industrial
Instrument and so on.
ꢀFEATURES
ꢁPch MOSFET Driving
ꢁWide Operating Voltage Range
ꢁPWM Control
Driving Voltage V+-5.35V(typ.)
3V to 35V
ꢁWide Oscillating Frequency
ꢁOver Current Protection
ꢁUVLO (Under Voltage Lockout)
ꢁStandby Function
50kHz to 1MHz
ꢁPackage Outline
NJW4160M: DMP8
NJW4160R: MSOP8(VSP8)
*MEETJEDEC MO-187-DA
ꢀPIN CONFIGURATION
PIN FUNCTION
1. OUT
1
2
3
4
8
7
6
5
2. SI
3. V+
4. EN
5. IN-
6. FB
7. CT
8. GND
NJW4160R
NJW4160M
Ver.2012-12-05
- 1 -
NJW4160
ꢀBLOCK DIAGRAM
V+
SI
ON/OFF
Enable
Control
EN
VIPK
Pulse by
Pulse
5V
Reg.
Low Frequency
Control
OSC
Driver
OUT
0.8V
Vref
PWM Comparator
Error AMP
IN-
FB
CT
GND
ꢀABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
OUT pin Voltage
EN pin sink Current
IN- pin Voltage
(Ta=25°C)
UNIT
V
V
µA
V
V
SYMBOL
MAXIMUM RATINGS
V+
VOUT
IEN
+40
V+-6 to V+
500
+6
+6 (*1)
VIN-
VCT
CT pin Voltage
MSOP8(VSP8) : 595 (*2)
DMP8: 530 (*2)
-40 to +85
-40 to +150
Power Dissipation
PD
mW
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
°C
°C
(*1): When Supply voltage is less than +6V, the absolute maximum voltage is equal to the Supply voltage.
(*2): Mounted on glass epoxy board based on EIA/JEDEC. (76.2 × 114.3 × 1.6mm: 2-Layers)
ꢀRECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Timing Capacitor
SYMBOL
MIN.
3
120
50
TYP.
MAX.
35
3,300
1,000
UNIT
V
pF
kHz
V+
CT
–
–
–
Oscillating Frequency
fOSC
Ver.2012-12-05
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NJW4160
ꢀELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V+=12V, VEN is connected to V+ via 200kΩ pull-up, CT=470pF, Ta=25°C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Oscillator Block
Oscillation Frequency
Charge Current
fOSC
Ichg
CT=470pF
270
180
180
–
300
200
200
0.6
330
220
220
–
kHz
µA
µA
V
Discharge Current
Voltage amplitude
Idis
VOSC
Frequency Supply Voltage
Deviation
Frequency Temperature
Deviation
Oscillation Frequency
(Low Frequency Control)
fDV
fDT
V+=3V to 35V
–
–
–
1
5
–
–
–
%
%
Ta=-40°C to +85°C
fOSC_LOW VIN-=0.3V, VFB=0.7V
100
kHz
Error Amplifier Block
Reference Voltage
Input Bias Current
Open Loop Gain
Gain Bandwidth
VB
IB
-1.0%
-0.1
–
0.8
–
+1.0%
+0.1
–
V
µA
dB
AV
GB
80
1
–
–
MHz
Output Source Current
Output Sink Current
IOM+
IOM-
VFB=1V, VIN-=0.7V
VFB=1V, VIN-=0.9V
50
6
90
13
140
20
µA
mA
PWM Comparate Block
Input Threshold Voltage
(FB pin)
VT_0
VT_50
Duty=0%, VIN-=0.6V
Duty=50%, VIN-=0.6V
0.32
0.63
100
0.4
0.7
–
0.48
0.77
–
V
V
Maximum Duty Cycle
MAXDUTY VFB=1.2V
%
Current Limit Detection Block
Current Limit Detection
Voltage
VIPK
95
–
120
100
145
–
mV
ns
Delay Time
TDELAY
Output Block
Output High Level
ON Resistance
ROH
ROL
IO=-50mA
–
3.5
7
Ω
Ω
Output Low Level
ON Resistance
Output Sink Current
IO=+50mA
–
9
–
IOL
OUT pin= V+ - 4.8V
20
30
45
mA
V
Output pin Limiting Voltage
VOLIM
V+ -5.5V V+ -5.35V V+ -5.0V
Under Voltage Lockout Block
ON Threshold Voltage
VT_ON
V+= L → H
V+= H → L
2.65
2.4
2.8
2.95
2.7
V
V
OFF Threshold Voltage
VT_OFF
2.55
Ver.2012-12-05
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NJW4160
ꢀELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V+=12V, VEN is connected to V+ via 200kΩ pull-up, CT=470pF, Ta=25°C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Enable Control Block
ON Control Voltage
OFF Control Voltage
EN pin Voltage at Open
EN pin Zener Voltage
EN pin Source Current
EN pin Sink Current
VON
VOFF
VEN= L → H
1.6
0
–
VZ_EN
0.5
2.0
–
V
V
VEN= H → L
–
VEN_OPEN
VZ_EN
1.5
4.8
0.6
–
1.8
5.2
2.0
20
V
V
IEN= 450µA
IEN_SOURCE VEN= 0V
6.0
40
µA
µA
IEN_SINK
VEN= 4.8V
General Characteristics
Quiescent Current
Standby Current
RL=no load,
VIN-=0.7V, VFB=0.7V
VEN=0V
IDD
–
–
1.1
3.5
1.5
6
mA
IDD_STB
µA
ꢀAPPLICATION EXAMPLE
Non-isolated Buck Converter
VIN
RSENSE
REN
Pow er MOSFET
L
C
IN1
VOUT
4
3
2
1
C
IN2
EN
V +
SI
OUT
CFB
RFB
SBD
COUT
R2
NJW4160
IN-
5
FB
6
CT
7
GND
8
R1
CT
RNF
CNF
Ver.2012-12-05
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NJW4160
ꢀCHARACTERISTICS
Oscillation Frequency vs. Supply Voltage
(CT=470pF, Ta=25oC)
Reference Voltage vs. Supply Voltage
(Ta=25oC)
310
305
300
295
290
0.81
0.805
0.8
0.795
0.79
0
10
20
30
40
0
10
20
30
40
Supply Voltage V+ (V)
Supply Voltage V+ (V)
Error Amplifier Block
Voltage Gain, Phase vs. Frequency
(V+=12V, Gain=40dB, Ta=25 oC)
Quiescent Current vs. Supply Voltage
(RL=no load, VIN-=VFB=0.7, Ta=25oC)
60
45
180
135
90
1.6
1.4
1.2
1
Phase
Gain
30
15
0
0.8
0.6
0.4
0.2
0
45
0
0.1
1
10
100
1000 10000
0
10
20
30
40
Supply Voltage V+ (V)
Frequency f (kHz)
EN pin Current vs.EN pin Voltage
(V+=12V, Ta=25oC)
30
25
20
15
10
5
Sink
VEN_OPEN
0
VZ_EN
-5
Source
1
-10
0
2
3
4
5
6
EN pin Volatage VEN (V)
Ver.2012-12-05
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NJW4160
ꢀCHARACTERISTICS
Oscillator Frequency vs. Temperature
(V+=12V, CT=470pF)
Reference Voltage vs. Temperature
(V+=12V)
330
320
310
300
290
280
270
0.81
0.805
0.8
0.795
0.79
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
Current Limit Detection Votage
vs.Temperature
OUT pin Limited Voltage vs.Temperature
(V+=12V)
(V+=12V)
150
12
10
8
140
130
120
110
100
90
6
4
2
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
Output Low Level ON Resistance vs.Temperature
Output High Level ON Resistance vs.Temperature
(IO=-50mA)
(IO=-50mA)
30
7
25
20
6
V+=3V
5
V+=3V
4
15
3
10
V+=12V, 35V
2
5
V+=12V, 35V
1
0
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
Ver.2012-12-05
- 6 -
NJW4160
ꢀCHARACTERISTICS
Under Voltage Lockout Voltage
Enable Control ON/OFF Voltage vs.Temperature
vs. Temperature
(V+=12V)
3
2.9
2.8
2.7
2.6
2.5
2.4
1.6
1.4
1.2
VT_ON
1
VON
0.8
0.6
VT_OFF
VOFF
0.4
0.2
0
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Standby Current vs. Temperature
(VEN=0V)
Quiescent Current vs. Temperature
(CT=470pF, RL=no load, VIN-=VFB=0.7V)
1.4
6
5
4
3
2
1
0
V+=35V
1.2
1
V+=35V
V+=12V
V+=12V
V+=3V
0.8
0.6
0.4
0.2
0
V+=3V
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
Ver.2012-12-05
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NJW4160Application Manual
Technical Information
ꢀPIN DESCRIPTIONS
PIN
PIN NAME
NUMBER
FUNCTION
Output pin for Power MOSFET Driving
1
OUT
The OUT pin Voltage is clamped with V+ -5.35V(typ.) at the time of Low level, in
order to protect a gate of Pch MOSFET.
Current Sensing pin
2
3
4
SI
V+
When difference voltage between the V+ pin and the SI pin exceeds 120mV(typ.),
over current protection operates.
Power Supply pin
ON/OFF Control pin
Normal Operation at the time of High Level.
Standby Mode at the time of Low Level.
Output Voltage Detecting pin
EN
5
6
IN-
FB
Connects output voltage through the resistor divider tap to this pin in order to
voltage of the IN- pin become 0.8V.
Feedback Setting pin
The feedback resistor and capacitor are connected between the FB pin and the
IN- pin.
Oscillating Frequency Setting pin by Timing Capacitor
Oscillating Frequency should set between 50kHz and 1MHz.
GND pin
7
8
CT
GND
Ver.2012-12-05
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NJW4160 Application Manual
Technical Information
ꢀDescription of Block Features
ꢁError Amplifier Section (ER⋅AMP)
0.8V±1% precise reference voltage is connected to the non-inverted input of this section.
To set the output voltage, connects converter's output to inverted input of this section (IN- pin). If requires output
voltage over 0.8V, inserts resistor divider.
This AMP section has high gain and external feedback pin (FB pin). It is easy to insert a feedback resistor and a
capacitor between the FB pin and the IN- pin, making possible to set optimum loop compensation for each type of
application.
ꢁOscillation Circuit Section (OSC)
Oscillation frequency can be set by inserting capacitor between the CT pin and GND. Referring to the sample
characteristics in "Timing Capacitor and Oscillation Frequency", set oscillation frequency between 50kHz and 1MHz.
The triangular wave of the oscillating circuit is generated in the IC, having amplitude between 0.4V and 1.0V at
CT=470pF(ref.).
If voltage of the IN- pin becomes less than 0.3V, the oscillation frequency decreases to one third (33%) and the
energy consumption is suppressed.
Oscillation frequency vs.Timing Capacitor
(V+=12V, Ta=25oC)
1000
100
10
10
100
1000
10000
Timing Capacitor CT (pF)
ꢁPWM Comparator Section (PWM)
This section controls the switching duty ratio.
PWM comparator receives the signal of the error amplifier and the triangular wave, and controls the duty ratio
between 0% and 100%. The timing chart is shown in Fig.1.
FB pin Voltage
1.0V
OSC
Waveform
0.4V
High
OUT pin
Low
GND
Fig. 1. Timing Chart PWM Comparator and OUT pin
Ver.2012-12-05
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NJW4160Application Manual
Technical Information
ꢀDescription of Block Features (Continued)
ꢁDriver Section (Driver)
The output driver circuit is configured a totem pole type, it can efficiently drive a Pch MOSFET switching device.
When the output is low level, the OUT pin voltage is clamped with V+ -5.35V (typ.) by the internal regulator to protect
gate of Pch MOSFET. (Ref. Fig.2. OUT pin)
V+
5V
To turn of f Pc h MOSFET
High Level Output
Regulator
VGS
V+
OUT
V+-5.35V
GND
To turn on Pch MOSFET
Low Level Output
From PWM
Comparator
Driver
OFF ON
OFF ON
Fig. 2. Driver Circuit and the OUT pin Voltage
When supply voltage is decreasing, gate drive voltage output from the OUT pin is also decreasing. Although the
OUT pin voltage is kept gate drive voltage by bypassing the internal regulator around supply voltage 5V. Fig.3.
shows the example of the OUT pin voltage vs. supply voltage characteristic
The optimum drive ability of MOSFET depends on the oscillation frequency and the gate capacitance of MOSFET.
OUT pin Voltage vs. Supply Voltage
(IO_SINK=0mA, Ta=25oC)
6
5
4
3
2
1
0
3
4
5
6
7
8
Supply Voltage V+ (V)
Fig. 3. OUT pin Voltage vs. Supply Voltage Characteristic
Ver.2012-12-05
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NJW4160 Application Manual
Technical Information
ꢀDescription of Block Features (Continued)
ꢁPower Supply, GND pin (V+, GND)
In line with MOSFET drive, current flows into the IC according to frequency. If the power supply impedance
provided to the power supply circuit is high, it will not be possible to take advantage of IC performance due to input
voltage fluctuation. Therefore insert a bypass capacitor close to the V+ pin – the GND pin connection in order to
lower high frequency impedance.
ꢁUnder Voltage Lockout Function (UVLO)
The UVLO circuit operating is released above V+=2.8V(typ.) and IC operation starts. When power supply voltage
is low, IC does not operate because the UVLO circuit operates. There is 250mV width hysteresis voltage at rise and
decay of power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing.
ꢁEnable Function (Enable Control)
With the voltage of the EN pin, the operation of NJW4160 can be set as in Table1.
Table1. EN pin voltage and NJW4160 status
Condition of applied
State of NJW4160
Example of connecting EN pin
voltage to EN pin
The EN pin voltage is clamped to VZ_EN=5.2V (typ.) with the
internal Zener diode.
You should adjust the flow current into the Zener diode to less
than 500µA.
V+
REN
V+
1.6V to VZ_EN
*Internal Zener Voltage
*
EN
ON/OFF
Enable
Control
less than 500µA
5.2V
Normal Mode
When the EN pin is open, VEN_OPEN=1.8V (typ.) is generated
with the internal current source and two diodes.
V+
EN
The EN pin OPEN
ON/OFF
Enable
Control
Generate 1.8V
Connect to GND
V+
EN
ON/OFF
Enable
Standby Mode
0V to 0.5V
Control
Ver.2012-12-05
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NJW4160 Application Manual
Technical Information
ꢀDescription of Block Features (Continued)
ꢁOver Current Protection Circuit
At when the potential difference between the V+ pin and the SI pin becomes 120mV or more, the over current
protection circuit is stopped the switch output. The switching current is detected by inserted current sensing resistor
(Rsc) between the V+ pin and the SI pin. Fig.4. shows the timing chart of the over current protection detection.
The switching output holds low level until next pulse output at OCP operating. The NJW4160 output returns
automatically along with release from the over current condition because the OCP is pulse-by-pulse type.
If voltage of the IN- pin becomes less than 0.3V, the oscillation frequency decreases to one third (33%) and the
energy consumption is suppressed.
FB pin Voltage
OSC
Waveform
High
OUT pin
Low
GND
VIPK
Rsc Sense
0
Static State
Static State
Detect
Overcurrent
Fig. 4. Timing Chart at Over Current Detection
The current waveform contains high frequency superimposed noises due to the parasitic elements of MOSFET,
the inductor and the others. Depending on the application, inserting RC low-pass filter between current sensing
resistor (RSENSE) and the SI pin to prevent the malfunction due to such noise. The time constant of RC low-pass filter
should be equivalent to the spike width (T≤ RS1 × CS1) as a rough guide (Fig. 5).
RSENSE
Spike Noise
RS1
Low Pass Filter
CS1
V+
SI
OUT
T
To Pulse
by Pulse
Current Waveform example
VIPK
Current Limit Detection
Fig. 5. Current Waveform and Filter Circuit
Ver.2012-12-05
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NJW4160 Application Manual
Technical Information
ꢀApplication Information
ꢁInductors
Current
Peak Current Ipk
Large currents flow into inductor, therefore you
must provide current capacity that does not
saturate.
Inductor
Current ∆IL
(1) Continuous
Conduction Mode
Reducing L, the size of the inductor can be
smaller. However, peak current increases and
adversely affecting efficiency.
(2) Critical Mode
(3) Continuous
Conduction Mode
0
Frequency
On the other hand, increasing L, peak current
can be reduced at switching time. Therefore
conversion efficiency improves, and output ripple
voltage reduces. Above a certain level, increasing
inductance windings increases loss (copper loss)
due to the resistor element.
tON
tOFF
fOSC
Fig. 6. Inductor Current State Transition
Ideally, the value of L is set so that inductance current is in continuous conduction mode. However, as the load
current decreases, the current waveform changes from (1) CCM: Continuous Conduction Mode → (2) Critical Mode
→ (3) DCM: Discontinuous Conduction Mode (Fig. 6.).
In discontinuous mode, peak current increases with respect to output current, and conversion efficiency tend to
decrease. Depending on the situation, increase L to widen the load current area to maintain continuous mode.
ꢁCatch Diode
When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output
capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's
forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a
low forward saturation voltage, is ideal.
An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when
the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such
factors as noise generation.
ꢁSwitching Element
You should use a switching element (Pch MOSFET) that is specified for use as a switch. And select sufficiently low
R
ON MOSFET at less than VGS=5V because the NJW4160 OUT pin voltage is clamped V+-5.35V (typ.).
However, when the supply voltage of the NJW4160 is low, the OUT pin voltage becomes low. You should select a
suitable MOSFET according to the supply voltage specification. (Ref. Driver section)
Large gate capacitance is a source of decreased efficiency. That is charge and discharge from gate capacitance
delays switching rise and fall time, generating switching loss.
The spike noise might occur at the time of charge/discharge of gate by the parasitic inductance element. You
should insert resistance between the OUT pin and the gate and limit the current for gate protection when gate
capacitance is small. However, it should be noted that the efficiency might decrease because the shape of waves
may become duller when resistance is too large. The last fine-tuning should be done on the actual device and
equipment.
Ver.2012-12-05
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NJW4160Application Manual
Technical Information
ꢀApplication Information (Continued)
ꢁInput Capacitor
Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply
impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW4160
performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as
possible.
ꢁOutput Capacitor
An output capacitor stores power from the inductor, and stabilizes voltage provided to the output.
When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple
current, and breakdown voltage.
Also, the ambient temperature affects capacitors, decreasing capacitance and increasing ESR (at low
temperature), and decreasing lifetime (at high temperature). Concerning capacitor rating, it is advisable to allow
sufficient margin.
Output capacitor ESR characteristics have a major influence on output ripple noise. A capacitor with low ESR can
further reduce ripple voltage. Be sure to note the following points; when ceramic capacitor is used, the capacitance
value decreases with DC voltage applied to the capacitor.
Ver.2012-12-05
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NJW4160 Application Manual
Technical Information
ꢀApplication Information (Continued)
ꢁBoard Layout
In the switching regulator application, because the current flow corresponds to the oscillation frequency, the
substrate (PCB) layout becomes an important.
You should attempt the transition voltage decrease by making a current loop area minimize as much as possible.
Therefore, you should make a current flowing line thick and short as much as possible. Fig.7. shows a current loop
at step-down converter.
SW
L
SW
L
COUT
COUT
VIN
C
SBD
VIN
C
SBD
IN
IN
NJW4160
NJW4160
(a) Buck Converter SW ON
(b) Buck Converter SW OFF
Fig. 7. Current Loop at Buck Converter
Concerning the GND line, it is preferred to separate the power system and the signal system, and use single
ground point.
The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has
high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance.
Fig. 8. shows example of wiring at buck converter.
SW
L
VOUT
VIN
C
SBD
COUT
IN
OUT
(Bypass Capacitor) V+
RFB
CFB
NJW4160
IN-
CT
R2
R1
CT
GND
To avoid the influence of the voltage
drop, the output voltage should be
detected near the load.
Separate Digital(Signal)
GND from Pow er GND
Because IN- pin is high impedance, the
voltage detection resistance: R1/R2 is
put as much as possible near IC(IN-).
Fig. 8. Board Layout at Buck Converter
Ver.2012-12-05
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NJW4160Application Manual
Technical Information
ꢀCalculation of Package Power
You should consider derating power consumption under using high ambient temperature.
Moreover, you should consider the power consumption that occurs in order to drive the switching element.
Supply Voltage:
V+
Quiescent Current:
Oscillation Frequency:
ON time:
IDD
fOSC
ton
Qg
Gate charge amount:
The gate of MOSFET has the character of high impedance. The power consumption increases by quickening the
switching frequency due to charge and discharge the gate capacitance. Power consumption: PD is calculated as
follows.
PD = (V+ × IDD) + (V+ × Qg × fOSC) [W]
You should consider temperature derating to the calculated power consumption: PD.
You should design power consumption in rated range referring to the power dissipation vs. ambient temperature
characteristics (Fig. 9).
MSOP8(VSP8) Package
DMP8 Package
Power Dissipation vs. Ambient Temperature
Power Dissipation vs. Ambient Temperature
(Tj= ~150oC)
(Tj= ~150oC)
1000
1000
At on 4 layer PC Board
At on 2 layer PC Board
At on 4 layer PC Board
At on 2 layer PC Board
800
600
400
200
0
800
600
400
200
0
0
25
50
75
100 125 150
0
25
50
75
100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 2Layers)
Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 4Layers),
internal Cu area: 74.2×74.2mm
Fig. 9. Power Dissipation vs. Ambient Temperature Characteristics
Ver.2012-12-05
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NJW4160 Application Manual
Technical Information
ꢀApplication Design Examples
ꢁStep-Down Application Circuit
Input Voltage
Output Voltage
Output Current
: VIN=12V
: VOUT=5V
: IOUT=3A
Oscillation frequency : fosc=300kHz
Output Ripple Voltage : Vripple(P-P)=less than 20mV
RSENSE
VIN=12V
0.03
Ω
REN
200k
C
IN1
Pow er MOSFET
L 10 H/4A
Ω
10 F/25V
µ
µ
VOUT =5V
R2
4
3
V +
2
1
C
IN2
CFB
220pF
0.1 F/50V
EN
SI
OUT
µ
SBD
NJW4160
27k
RFB
Ω
0
Ω
COUT
10 F/6.5V
IN-
5
FB
6
CT
7
GND
8
µ
R1
5.1k
Ω
CT
470pF
RNF
15k
CNF
1,000pF
Ω
Ver.2012-12-05
- 17 -
NJW4160Application Manual
Technical Information
ꢀApplication Design Examples (Continued)
ꢁSetting Oscillation Frequency
Peak Current Ipk
From the Oscillation frequency vs. Timing Capacitor
Characteristic, CT=470 [pF], t=3.33[µs] at fosc=300kHz.
Inductance
Current ∆IL
Step-down converter duty ratio is shown with the following
equation.
Output Current IOUT
0
VOUT +VF
5 + 0.4
Duty =
×100 =
×100 = 45
[%]
VIN
12
tON
tOFF
Period t
Therefore, tON=1.50 [µs], tOFF=1.83 [µs]
Frequency fOSC=1/t
Fig. 10. Inductor Current Waveform
ꢁSelecting Inductance
∆IL is Inductance ripple current. When to ∆IL= output current 34%:
∆IL = 0.34 × IOUT = 0.34 × 3 = 1.02 [A]
This obtains inductance L. VDS_RON is drop voltage by MOSFET on resistance.
VIN −VDS−RON −VOUT
∆IL
12 − 0.2 − 5
L =
×tON
=
×1.5µ = 10 [µH ]
1.02
Inductance L is a theoretical value. The optimum value varies according such factors as application specifications
and components. Fine-tuning should be done on the actual device.
This obtains the peak current Ipk at switching time.
∆IL
2
1.02
2
Ipk = IOUT
+
= 3 +
= 3.51[A]
The current that flows into the inductance provides sufficient margin for peak current at switching time.
In the application circuit, use L=10µH/4A.
ꢁSetting Over Current Detection
In this application, current limitation value: ILIMIT is set to Ipk=4A.
ILIMIT = VIPK / RSC = 120mV / 30mΩ =4 [A]
The limit value increases slightly according to response time from the overcurrent detection with the SI pin to the
OUT pin stop.
VIN
L
12
ILIMIT _ DELAY = ILIMIT
+
×TDELAY = 4.0 +
×100n = 4.12[A]
10µ
Ver.2012-12-05
- 18 -
NJW4160 Application Manual
Technical Information
ꢀApplication Design Examples (Continued)
ꢁSelecting the Input Capacitor
The input capacitor corresponds to the input of the power supply. It is required to adequately reduce the
impedance of the power supply. The input capacitor selection should be determined by the input ripple current and
the maximum input voltage of the capacitor rather than its capacitance value.
The effective input current can be expressed by the following formula.
VOUT
×
(
VIN −VOUT
)
IRMS = IOUT
×
[A]
VIN
In the above formula, the maximum current is obtained when VIN = 2 × VOUT, and the result in this case is
RMS = IOUT (MAX) ÷ 2.
I
When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has
adequate margin.
ꢁSelecting the Output Capacitor
The output capacitor is an important component that determines output ripple noise. Equivalent Series Resistance
(ESR), ripple current, and capacitor breakdown voltage are important in determining the output capacitor.
The output ripple noise can be expressed by the following formula.
Vripple( p− p)
ESR =
∆IL
When selecting output capacitance, select a capacitor that allows for sufficient ripple current.
The effective ripple current that flows in a capacitor (Irms) is obtained by the following equation.
∆IL
1.02
Irms
=
=
= 294 [mArms]
2 3 2 3
Consider sufficient margin, and use a capacitor that fulfills the above spec.
In the application circuit, use COUT=10µF/6.3V,.
ꢁSetting Output Voltage
The output voltage VOUT is determined by the relative resistances of R1, R2. The current that flows in R1, R2 must
be a value that can ignore the bias current that flows in ER AMP.
R2
R1
27k
⎛
⎜
⎞
⎠
⎛
⎜
⎞
⎠
VOUT
=
+1 ×V =
+1 ×0.8 = 5.04[V]
⎟
⎟
B
5.1k
⎝
⎝
Ver.2012-12-05
- 19 -
NJW4160Application Manual
Technical Information
ꢀCompensation design example
A switching regulator requires a feedback circuit for acquiring a stable
output. Because the frequency characteristics of the application change
according to the inductance, output capacitor, and so on, the compensation
constant should ideally be determined in such a way that the maximum band
is acquired while the necessary phase for stable operation is maintained.
These compensation constants play an important role in the adjustment of
the NJW4160 when mounted in an actual unit. Finally, select the constants
while performing measurement, in consideration of the application
specifications.
Pole
-20dB/dec
0
°
-45
°
°
-90
fP/10
fP
10fP
Frequency
Pole
+20dB/dec
Zero
ꢁFeedback and Stability
Basically, the feedback loop should be designed in such a way that the open
loop phase shift at the point where the loop gain is 0 dB is less than -180°. It is
also important that the loop characteristics have margin in consideration of
ringing and immunity to oscillation during load fluctuations. With the NJW4160,
the feedback circuit can be freely designed, enabling the arrangement of the
poles and zeros which is important for loop compensation, to be optimized.
+90
+45
°
°
0
°
fZ/10
fZ
10fZ
Frequency
Zero
The characteristics of the poles and zeros are shown in Fig.11.
Poles: The gain has a slope of -20 dB/dec, and the phase shifts -90°.
Zeros: The gain has a slope of +20 dB/dec, and the phase shift +90°.
Fig. 11. Characteristics of Pole and Zero
If the number of factors constituting poles is defined as “n”, the change in the gain and phase will be “n”-fold. This
also applies to zeros as well. The poles and zeros are in a reciprocal relationship, so if there is one factor for each pole
and zero, they will cancel each other.
ꢁConfiguration of the compensation circuit
VIN
LC Gain
Driver
L
VOUT
RESR
CFB
RFB
R2
COUT
ER⋅AMP
Vref
=0.8V
PWM
IN-
FB
R1
CNF
RNF
C1(option)
Fig. 12. Compensation Circuit Configuration
Ver.2012-12-05
- 20 -
NJW4160 Application Manual
Technical Information
ꢀCompensation Design (Continued)
ꢁPoles and zeros due to the inductance and output capacitor
Double poles fP(LC) are generated by the inductance and output capacitor. Simultaneously, single zeros fZ(ESR) are
generated by the output capacitor and ESR. Each pole and zero is expressed by the following formula.
1
1
fZ(ESR)
=
fP(LC) =
2πCOUTRESR
2π LCOUT
If the ESR of the output capacitor is high, fZ(ESR) will be located in the vicinity of fP(LC). In an application such as this,
the zero fZ(ESR) compensates the double poles fP(LC), resulting in a tendency for stability to be readily maintained.
However, if the ESR of the output capacitor is low, fZ(ESR) shifts to the high region, and the phase is shifted -180° by
fP(LC).The NJW4160 compensation circuit enables compensation to be realized by using zeros fZ1 and fZ2.
Gain (dB)
ꢁPoles and zeros due to error amplifier
Double
pole
The single poles and zeros generated by the error amplifier
are obtained using the following formula.
LC Gain
-40dB/dec
-20dB/dec
Zero
Pole
1
fP1
=
1
fZ1
=
R1R2
⎛
⎜
⎞
⎟
Loop
Gain
2πCNFAV
2πCNFRNF
R1+ R2
⎝
⎠
0dB frequency
(Av: Amplifier Open Loop Gain=80dB)
1
*
Gain increase
due to Zero
fP2
=
1
fZ2
=
R1R2
⎛
⎜
⎞
⎟
2πCFB
R
+
FB
2πCFBR2
R1+ R2
⎝
⎠
Compensation
Gain
1
fP3
=
(Option)
2πC1RNF
fZ1 and fZ2 are located on both sides of fP(LC)
.
fP1
fZ1 or fZ2
fP(LC) fP2 fP3 fZ(ESR)
Because the inductance and output capacitor vary, they are
Fig. 13. Loop Gain examples
each set using the following as a rough guide.
fP(LC) × 0.5-fold – 0.9-fold
fP(LC) × 1.1-fold – 2.0-fold
There is also a method in which fZ1 and fZ2 are located at positions lower than even fP(LC). Because there is a
tendency for the phase shift to increase and the gain to rise, it can be expected that the response will improve.
However, there is a tendency for the phase margin to become insufficient, so care is necessary.
fP1 creates poles in the low frequency region due to the Miller effect of the error amplifier. The stability becomes
better as fP1 becomes lower. On the other hand, the frequency characteristics do not improve, so the response is
adversely affected. fP1 is set using a frequency gain of 20 dB for fP(LC) as a rough guide.
If the open loop gain of the error amplifier is made 80 dB, design is carried out using fP1 < fP(LC) ÷ 103 (= 60 dB) as a
rough guide.
Above several 100 kHz, various poles are generated, so the upper limit of the frequency range where the loop
gain is 0 dB is set to fifth (1/5) to tenth (1/10) of oscillation frequency. The fZ(ESR) in the high frequency region
sometimes causes a loop gain to be generated (See Fig.13 Loop Gain “). Using fP2 and fP3, perform adjustment with
the NJW4160 mounted in an actual unit, so as to adequately reduce the loop gain in the high frequency region.
Ver.2012-12-05
- 21 -
NJW4160
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2012-12-05
- 22 -
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