NJW4800 [NJRC]
30V/4A Half Bridge Driver; 30V / 4A半桥驱动器
| 型号： | NJW4800 |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | 30V/4A Half Bridge Driver |
| 文件： | 总16页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW4800
30V/4A Half Bridge Driver
ꢀGENERAL DESCRIPTION
■ PACKAGE OUTLINE
The NJW4800 is a general purpose, half bridge power driver
capable of supplying 4A current. The internal gate driver drives
high-side/low-side power MOSFET; therefore, it has fast switching.
Additionally, it has protection features such as over current
protection and thermal shutdown.
NJW4800GM1
And in the case of failure, it can output a fault flag.
It is suitable for power switching applications of DSP/micro
controller.
ꢀFEATURES
● Output Switch Current
● Operating Voltage
±4A
7.5V to 30V
● Up to 1.2MHz Switching Frequency
● Thermal Shut Down
● Over Current Protection
● Under Voltage Lockouts
● Fault Indicator Output
● Stand-by Current
IQOFF =3µA typ.
● High Heat Radiation Package
● Package Outline
HSOP8
ꢀPIN CONFIGURATION
PIN FUNCTION
1. PWM
2. VDD
3. OUT
4. GND
5. BS
1
2
3
4
8
7
6
5
6. STBY
7. REG
8. FLT
Exposed PAD on
backside connect to GND
Ver.2010-09-29
- 1 -
NJW4800
ꢀBLOCK DIAGRAM
RFLT
FLT
CREG
VDD
REG
Over current
Protection
BS
Regulator (5V)
Level Shift
Thermal
Shut Down
High Side
Gate Driver
CBS
Under Voltage
Lock Out
OUT
PWM
STBY
Low Side
Gate Driver
Input Control
100k
Ω
750k
Ω
GND
Ver.2010-09-29
- 2 -
NJW4800
ꢀABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
(Ta=25°C)
SYMBOL
MAXIMUM RATINGS
35
UNIT
V
REMARKS
VDD-GND pin
STBY,
PWM-GND pin
FLT-GND pin
BS-GND pin
BS-OUT pin
V+
VSTBY
VPWM
VFLT
Input Voltage
V
-0.3 ∼ 6
FLT pin Voltage
BS pin Voltage
BS-OUT pin Voltage
V
V
V
-0.3 ∼ 6
40
-0.3 ∼ 6
VBS
VBS–OUT
900 (*1)
3100 (*2)
-40 ~ +150
-40 ~ +85
-50 ~ +150
Power Dissipation
PD
W
–
Operating Junction Temperature
Operating Temperature Range
Storage Temperature Range
Tj
Topr
Tstg
–
–
–
°C
°C
°C
ꢀRECOMMENDED OPERATING CONDITIONS
(Ta=25°C)
REMARKS
VDD-GND pin
OUT pin
PARAMETER
Operating Voltage
SYMBOL
Vopr
MIN.
7.5
0
TYP.
–
–
MAX.
30
4
UNIT
V
A
Output Switch Current
IOM
VSTBY
VPWM
VFLT
,
STBY,
PWM-GND pin
FLT-GND pin
Input Voltage
0
0
–
–
5.5
V
V
FLT pin Voltage
VREG1
ꢀTHERMAL CHARACTERISTICS
PARAMETER SYMBOL
Junction-to-
(Ta=25°C)
UNIT
THERMAL RESISTANCE
139 (*1)
40 (*2)
19 (*1)
3.7 (*2)
θja
°C/W
°C/W
Ambient Temperature
Junction-to-Case
ψjt
(*1): Mounted on glass epoxy board based on EIA/JEDEC. (76.2 × 114.3 × 1.6mm: 2-Layers)
(*2): Mounted on glass epoxy board based on EIA/JEDEC.
(76.2 × 114.3 × 1.6mm: 4-Layers Internal foil area: 74.2 × 74.2mm)
Power Dissipation vs. Ambient Temperature
(Topr=-40~+85oC, Tj= ~150oC)
4
3.5
At on 4 layer PC Board
3
2.5
2
1.5
1
At on 2 layer PC Board
0.5
0
-50
-25
0
25
50
75
100
Ambient Temperature Ta (oC)
Ver.2010-09-29
- 3 -
NJW4800
ꢀELECTRICAL CHARACTERISTICS (Unless otherwise noted, V+=12V, VSTBY=0V, CBS=0.1µF, CREG=1µF, Ta=25°C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
General Characteristics
Quiescent Current 1 (Operating)
IQ1
IQ2
VPWM=0V
–
–
–
1
9
3
2
mA
mA
µA
Quiescent Current 2 (Switching)
Quiescent Current 3 (Standby)
VPWM=0V to 3V, fPWM=1.2MHz
VSTBY=5.5V, VPWM=0V
14
10
IQOFF
Output Block
High-side SW ON Resistance
Low-side SW ON Resistance
Over Current Limit
Output Rise Time
RDSH
RDSL
ILIMIT
tr
IOSOURCE=1A, VBS–OUT=5V
IOSINK=1A
–
–
4
–
–
–
–
–
0.25
0.25
5.5
3
0.45
0.45
7
Ω
Ω
A
High-side and Low-side
V
PWM=0V to 3V
PWM=3V to 0V
PWM=0V to 3V
–
ns
ns
ns
ns
ns
Output Fall Time
tf
V
3
–
Dead Time
Dt
V
20
60
60
–
PWM Rise Delay Time
PWM Fall Delay Time
td_ON
td_OFF
VPWM=0V to 3V
VPWM=3V to 0V
–
–
OUT pin – VDD pin
VPDOV
V+=5.7V, IORH=1A
–
0.85
1.1
V
Potential Difference
GND pin – OUT pin
Potential Difference
Output Pull-down Resistance
VPDGO
RPD
V+=5.7V, IORL=1A
–
50
–
0.85
100
–
1.1
200
1
V
V+ =5.7V, VSTBY=5.5V
V+=30V, VSTBY=5.5V,
VOUT=0V
kΩ
µA
Output Leak Current
(High Side SW OFF)
OUT pin Output Current
(FLT Signal Output )
IOLEAKOUT
IO-FLT
V+=5.7V, VOUT=0V
–
30
60
µA
Input Circuit Block
STBY pin High Voltage
(Standby Mode)
STBY pin Low Voltage
(Operating Mode)
STBY pin Input Current
STBY Pull-down Resistance
VIHSTBY
2.4
0
–
–
5.5
0.8
V
V
VILSTBY
IISTBY
IISTBY
VSTBY=5.5V
–
500
2.2
0
0.01
750
–
1
1000
5.5
0.9
1
µA
kΩ
V
PWM pin High Voltage
PWM pin Low Voltage
PWM pin Input Current
Continuous Output High Time
VIHPWM
VILPWM
IIPWM
–
V
VPWM=5.5V
VPWM=5.5V
–
0.01
300
µA
µs
tHPWM
140
–
Under Voltage Lockout (UVLO) Block
UVLO Release Voltage
VUVLO2
VUVLO1
5.9
5.65
–
6.6
7.3
7.05
–
V
V
V
V+ = L → H
V+ = H → L
UVLO Operation Voltage
6.35
0.25
UVLO Hysteresis Voltage
VUVLO2-VUVLO1
∆VUVLO
Ver.2010-09-29
- 4 -
NJW4800
ꢀELECTRICAL CHARACTERISTICS (Unless otherwise noted, V+=12V, VSTBY=0V, CBS=0.1µF, CREG=1µF, Ta=25°C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Internal Power Supply Circuit
Output Voltage 1
VREG1
IREG=0mA
4.75
–
5
2
5.25
20
V
∆VREG–VDD V+=8 ∼ 30V, IREG=0mA
∆VREG–IO IREG=0 ∼ 20mA
Line Regulation
Load Regulation
mV
mV
–
20
50
VREG1×0.95,
Input signal=500kHz
REG pin Output Current
IOREG
30
–
–
mA
Fault Function (FLT pin)
Low Level Output Voltage
OFF Leak Current
VLFLT
IOLEAKFLT VFLT=5.5V
–
–
0.25
–
0.5
1
V
IFLT=500µA
µA
ꢀPIN OPERATION TABLE
INPUT
OUTPUT
High-side
SW
OFF
ON (*3)
OFF
Mode
Low-side
PWM
STBY
VDD
FLT
SW
ON
OFF
OFF
OFF
OFF
OFF
V+ ≥ VRUVLO
V+ ≥ VRUVLO
–
L
H
L
H
L
L
L
H
H
L
ON
ON
OFF
OFF
OFF
OFF
Normal
Normal
Stand-by
Stand-by
UVLO
–
OFF
OFF
OFF
V+ < VDUVLO
V+ < VDUVLO
H
L
UVLO
(*3) If PWM=H continues by tHPWM or more and is input, it becomes low-side SW=ON during tHPWM/128.
INPUT
OUTPUT
High-side
SW
Mode
Low-side
SW
Tj
IOUT
FLT
–
OFF
OFF
OFF
OFF
OFF
OFF
TSD
OCP
Tj >150°C
–
IOUT ≥ IOM
Ver.2010-09-29
- 5 -
NJW4800
ꢀTIMING CHART
Fig1. Output Rise/Fall Time, PWM Rise/Fall Delay Time
50%
50%
PWM
tr
tf
90%
90%
50%
50%
OUT
10%
td_ON
10%
td_OFF
Fig2. Maximum Continuous Output Time (High-level)
PWM
tHPWM/128
OUT
tHPWM
Fig3. Switching and Dead Time
ON
High Side
SW
OFF
ON
Low Side
SW
OFF
Dead Time 50ns typ.
Ver.2010-09-29
- 6 -
NJW4800
ꢀTYPICALAPPLICATIONS
V+
CP=1µF CIN=100µF
CREG
RFLT
=1µF
=47kΩ
VDD
REG
BS
CBS=0.1µF
FLT
NJW4800
GND
VOUT
FAULT
PWM
PWM
STBY
OUT
Controller
(NJU7600)
PWM Signal
Stand-by
Synchronous PWM step down switching regulator
V+
CP=1µF CIN=100µF
CREG
=1µF
RFLT
=47kΩ
VDD
NJW4800
GND
REG
FLT
BS
CBS=0.1µF
FAULT
PWM
Signal
PWM
STBY
OUT
Stand-by
Class-D single ended audio amplifier
V+
CP=1µF CIN=100µF
V+
CP=1µF CIN=100µF
VDD
REG
BS
VDD
REG
FLT
BS
FLT
NJW4800
GND
FAULT
NJW4800
PWM
Digital
Audio
Signal
FAULT
PWM
OUT
Signal
PWM Signal
PWM
STBY
OUT
PWM Signal
STBY
GND
4
Stand-by
Stand-by
V+
V+
CP=1µF CIN=100µF
M
CP=1µF CIN=100µF
VDD
NJW4800
GND
VDD
NJW4800
GND
REG
BS
REG
BS
FLT
FLT
FAULT
FAULT
PWM
OUT
PWM
STBY
OUT
PWM Signal
PWM Signal
STBY
Stand-by
Stand-by
Class-D full bridge audio amplifier
Full bridge motor driver
Ver.2010-09-29
- 7 -
NJW4800
ꢀCHARACTERISTICS
Over Current Limit vs. Temperature
(High-side, V+=12V)
Over Current Limit vs. Temperature
(Low-side, V+=12V)
7
6.5
6
7
6.5
6
CBS=0.47µF
REG=1µF
CBS=0.47µF
CREG=1µF
C
5.5
5
5.5
5
4.5
4.5
4
4
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
Low-side SW ON Resistance vs. Temperature
High-side SW ON Resistance vs. Temperature
(V+=12V, IOSINK=1A)
(IOSOURCE=1A, VBS-OUT=5V)
0.5
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
Ver.2010-09-29
- 8 -
NJW4800
ꢀCHARACTERISTICS
Continuous Output High Time vs. Temperature
(V+=12V, VPWM=3V)
Internal Power Supply Circuit Load Regulation
(V+=12V, Ta=25oC)
400
380
360
340
320
300
5.1
5
CBS=0.47µF
REG=1µF
CREG=1µF
C
4.9
4.8
4.7
0
20
40
60
80
100
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Output Current IREG (mA)
STBY pin Voltage vs. Temperature
(V+=12V)
Under Voltage Lockout Block vs. Temperature
7.2
2
7
1.8
6.8
VRUVLO
VIHSTBY
1.6
1.4
1.2
1
6.6
6.4
VDUVLO
6.2
VILSTBY
6
5.8
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ambient Temperature Ta (oC)
PWM pin Voltage vs. Temperature
(V+=12V)
Frequency vs. Operating Voltage
(VPWM=0V to 3V, Ta=25oC)
2
1.8
1.6
1.4
1.2
1
20
15
10
5
CBS=0.47µF
C
REG=1µF
VIHPWM
V+=30V
V+=12V
VILPWM
V+=7.5V
0
0
200 400 600 800 1000 1200
Frequency fPWM (kHz)
-50 -25
0
25 50 75 100 125 150
Ambient Temperature Ta (oC)
Ver.2010-09-29
- 9 -
NJW4800
ꢀCHARACTERISTICS
Quiescent Current 1 vs. Temperature
(V+=12V, VPWM=0V)
Quiescent Current 1 vs. Operating Voltage
(VPWM=0V, Ta=25oC)
2
1.5
1
2
1.5
1
CBS=0.47µF
CREG=1µF
CBS=0.47µF
C
REG=1µF
0.5
0.5
0
0
-50 -25
0
25 50 75 100 125 150
0
5
10 15 20 25 30 35
Operating Voltage V+ (V)
Ambient Temperature Ta (oC)
Quiescent Current 2 vs. Temperature
(V+=12V, VPWM=0V to 3V, fPWM=1.2MHz)
Quiescent Current 2 vs. Operating Voltage
(VPWM=0V to 3V, fPWM=1.2MHz, Ta=25oC)
20
15
10
5
20
15
10
5
CBS=0.47µF
CREG=1µF
CBS=0.47µF
CREG=1µF
0
0
-50 -25
0
25 50 75 100 125 150
0
5
10 15 20 25 30 35
Operating Voltage V+ (V)
Ambient Temperature Ta (oC)
Quiescent Current 3 vs. Temperature
(V+=12V, VSTBY=2V, VPWM=0V)
Quiescent Current 3 vs. Operating Voltage
(VSTBY=2V, fPWM=0V, Ta=25oC)
10
8
10
CBS=0.47µF
CREG=1µF
CBS=0.47µF
CREG=1µF
8
6
4
2
0
6
4
2
0
-50 -25
0
25 50 75 100 125 150
0
5
10
15 20 25 30 35
Ambient Temperature Ta (oC)
Operating Voltage V+ (V)
Ver.2010-09-29
- 10 -
NJW4800
ꢀPIN DESCRIPTION
PIN
NUMBER
PIN NAME
FUNCTION
PWM Signal Input Terminal
As for Control Logic, Refer to PIN OPERATION TABLE (page.5)
Power Supply Terminal
You should connect capacitor (AL and MLCC) for reducing Input Impedance.
Output Terminal
1
PWM
VDD
2
3
4
5
OUT
GND
BS
The High-side/Low-side Switch are Limited to 5.5A(typ.) by Over Current
Protection Circuit.
Ground Terminal
Boot Strap Output Terminal
Boot Strap Output drives the High-side Switch. You should connect capacitor
larger than 0.1µF between BS Terminal (5-pin) and Out Terminal (3-pin).
Standby Terminal
6
7
STBY
REG
NJW4800 becomes standby status by High Level
NJW4800 operates by Low Level
Built-in Regulator (5V) Output Terminal
You should connect capacitor larger than 1µF for stable output.
Fault Signal Output Terminal
It is Open Drain Output Type. You should connect through Pull-up Resister to
REG Terminal (7-pin) or External Power Supply.
It outputs Low Level under normal operating condition and outputs High Level
under Abnormal Conditions.
8
–
FLT
Exposed
PAD
Connected to 4pin (Ground Terminal)
Ver.2010-09-29
- 11 -
NJW4800
ꢀFUNCTIONAL EXPLANATION
ꢁHigh-side, Low-side Switch
The SW output drives the load. It is controlled by the logic input signal from PWM terminal at PWM. When the signal at
PWM is high (above 2.2V), the high-side switch is turned on. When the signal at PWM is low (less than 0.9V), the
low-side switch is turned on.
The NJW4800 uses built-in Nch MOSFETs (RON=0.25Ω typ.) for both the high-side and low-side switches. The
high-side SW gate is driven with V++5V that generated by bootstrap. The high-side SW turn on time is limited to
300µsec(typ.). (ex. Fig2)
ON
There is a dead time region (20nsec (typ.): design value) to
High Side
prevent short circuit (high-side and low-side) where both the
high-side and low-side switches are off. (ex. Fig3)
The NJW4800 is suitable for high-frequency switching
regulator. The NJW4800 operates at frequencies up to
1.2MHz.
SW
OFF
ON
Low Side
SW
OFF
The OUT terminal is pulled down inside with 100kΩ,
compensates the leak current of the High-side SW.
Dead Time 20ns typ.
Fig3. SW Function and Dead Time Relation
ꢁOver Current Protection Function
The internal over-current protection circuit monitors the flow currents of both the high-side and low-side switches. The
over-current protection circuit operates at 5.5A (typ.) and stops the SW operation. The FLT signal is output from FLT
terminal at the same time. The over-current protection operation is released at the PWM input signal falling edge. (ex.
Fig4)
If OUT terminal is shorted directly to GND, a large surge current is flowing for fast current change and may exceed
current limit. Because that time big electric power consumption occurs instantaneously in NJW4800, you should design
sufficient heat dissipation.
When a load condition is inductive property, a reverse direction current flows to the high-side and low-side SW body
diode by inductive kickback.
The built-in over-current protection circuit has not aimed at protection against the inductive kickback.
Therefore, an external diode should be considered usage against reverse-current regeneration according to the kind of
the application.
The Overcurrent Protection is
released with the falling edge
High
PWM Input
Low
ON
High Side SW
Low Side SW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OFF
ON
OFF
ON
Current Limit
OFF
High
Fault Output
(FLT pin Pull-Up)
Low
Fig4. Timing Chart of High-side/Low-side Switch at Over Current Protection Operating
Ver.2010-09-29
- 12 -
NJW4800
ꢁBoot Strap
In order to drive the gate of the high side SW, the voltage that is higher than power supply voltage is necessary.
The bootstrap condenser generates the power supply voltage of V++5V to BS terminal and it supplies the power to the
gate of the high side SW. As Shown as Fig5 in detail.
Power Line
Power Line
V+
V+
Regulator Voltage
Regulator Voltage
VDD
OFF
VDD
V+=5V is generated to
the BS terminal.
BS
Regulator
5V
Regulator
5V
ON
CBS
CBS
CBS is
High Side
Gate Driver
High Side
Gate Driver
charged to 5V
OUT becomes V+
voltage
OUT
OUT
ON
OFF
Low Side
Low Side
Gate Driver
Gate Driver
High-side SW: OFF
Low-side SW: ON
High-side SW: ON
Low-side SW: OFF
Fig5. High-side SW driven by Boot Strap
You should connect bootstrap condenser larger than CBS=0.1µF between BS Terminal and OUT Terminal.
The internal counter decides the bootstrap condenser Charge and Discharge time.
A capacitor discharge time (tHPWM) for High-side SW Maximum ON Time is 300ms (typ).
A capacitor charge time (tHPWM / 128) for Low-side SW Minimum ON Time is 2.34µs (typ).
ꢁBuilt-in Regulator
The REG Terminal outputs Reference Voltage (5V).
It can be used as generating of the voltage for the bootstrap or a power supply voltage for other device(s). You should
connect capacitor (CREG) larger than 1µF for stable regulator output.
This regulator current capability (IOREG) is 30mA (min) at (VREG1×0.95). This regulator over current protection is a
drooping characteristic type. It has drooping characteristic at over current protection function.
ꢁThermal Shut Down Function
When NJW4800 chip temperature exceeds the 170°C, internal thermal shutdown circuit operates and SW function is
stopped. The Fault signal is output simultaneously from the FLT terminal. In order to return SW operation, you should
make chip surface temperature (Junction Temperature: Tj) below the 150°C*.
This function is a circuit to prevent IC at the high temperature from malfunctioning and is not something that urges
positive use. You should make sure to operate inside the junction temperature range rated. (* Design value)
Ver.2010-09-29
- 13 -
NJW4800
ꢁUnder Voltage Lockout(UVLO)
The UVLO circuit operating is released above V+=6.6V(typ.) and IC operation starts. When power supply voltage is low,
because the UVLO circuit operates, IC does not operate. There is 0.25V width hysteresis voltage at rise and decay of
power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing.
ꢁFAULT Signal Output
This Terminal is Open Drain Output Type. You should connect through Pull-up Resister to REG Terminal (7-pin) or
External Power Supply. It outputs Low Level under normal operating condition and outputs High Level under Abnormal
Conditions.
The following information is output as FAULT signal.
・Stop Operation at Under Voltage Lockout (UVLO)
・Over Current Protection Function
・Thermal Shut Down
At the time of standby state, it outputs High Level.
When outputting the FAULT signal, it has stopped SW operation, but the internal regulator continues operation.
Because of this 30mA it is flowing via the OUT terminal from the regulator circuit.
ꢁStandby Function
NJW4800 stops the operating and becomes standby status when 2.4V or more is supplied to STBY terminal.
You should connect the terminal with GND level to prevent the malfunction by a noise when you do not use this function.
Ver.2010-09-29
- 14 -
NJW4800
ꢀAPPLICATION TIPS
In the application that does a high-speed switching of NJW4800, because the current flow corresponds to the input
frequency, the substrate (PCB) layout becomes an important.
NJW4800 is driving the High-side/Low-side SW gate with high speed to reduce switching losses. The transient voltage
is generated by parasitic inductance and a high-speed current change of high side and low side SW.
You should attempt the transition voltage decrease by making a current loop area minimize as much as possible.
Therefore, you should make a current flowing line thick and short as much as possible.
You should insert a bypass capacitor between VDD terminal and GND terminal to prevent malfunction by generating
over voltage and/or exceed maximum input voltage rating. The recommended bypass capacitor is 1µF or more high
frequency capacitor.
A 100µF aluminum electrolysis capacitor is recommended for smoothing condenser. However, you should use larger
capacitor by sufficient evaluation (assessment) due to load condition and/or application use environment. (There is a
possibility that the supply voltage rises by inductive kickback when the supply current of the inductive load is large.)
The bypass capacitors should be connected as much as possible near VDD terminal.
Ex. Bill of Materials
Components
CIN
Parts Name
－
Functions
Aluminum-Cap.
Manufacturers
Nippon Chemi-con
CP
CREG
CBS
GRM21BB11H104KA01B
GRM31MB31H105KA87B
GRM21BR71H474KA88B
RK73B1JT473
Murata
Murata
Murata
KOA
Ceramic-Cap. 0.1µF, 50V (B-val)
Ceramic-Cap. 1µF, 50V (B-val)
Ceramic-Cap. 0.1µF, 50V (X7R-val)
47kΩ
RFLT
Ver.2010-09-29
- 15 -
NJW4800
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2010-09-29
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