SM5846AP [NPC]
Multi-function Digital Filter; 多功能数字滤波器
| 型号： | SM5846AP |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | Multi-function Digital Filter |
| 文件： | 总36页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM5846AP
Multi-function Digital Filter
NIPPON PRECISION CIRCUITS INC.
Audio
ICs
Filter Construction
OVERVIEW
■ Interpolation filter (linear 3-stage FIR filter)
The SM5846AP is a multi-function digital filter that
incorporates 4/8 times oversampling digital audio
signal reproduction, digital deemphasis, digital
attenuation and soft mute functions. The I/O inter-
face allows serial data transmission of 16/20/24/32-
bit input data and 20/24-bit output data.
•
Normal-speed sampling mode
1st stage (fs to 2fs) 121st order
2nd stage (2fs to 4fs) 21st order
3rd stage (4fs to 8fs) 13th order
High-speed sampling mode:
•
1st stage (fs to 2fs) 177th order
2nd stage (2fs to 4fs) 29th order
3rd stage (4fs to 8fs) 17th order
FEATURES
Functions
■ Deemphasis filter (IIR filter)
■ Arithmetic units
■ 8-times oversampling (interpolation)
■ Switchable 8/4 times oversampling output
■ Two master clock frequencies
(refer to Clock Functions)
• 384fs/512fs (normal-speed sampling)
• 192fs/256fs (high-speed sampling)
■ Digital deemphasis
• 25× 24-bit parallel adder
• 32-bit accumulator
■ Overflow limiter built-in
Applications
■ Digital audio equipment
• Compatible with 32/44.1/48 kHz (normal-
speed) and 64/88.2/96 kHz (high-speed) input
sampling frequencies
PINOUT (TOP VIEW)
• ON/OFF control
■ Digital attenuator
• 128-step attenuation using linear 7-bit data set-
ting
■ Soft muting
• 1016/fs (normal-speed sampling)
• 2032/fs (high-speed sampling)
■ Output data round-off operation (normal round-off
or rectangular distribution dither round-off)
■ Selectable LR clock polarity
■ Microprocessor controllable
■ Input data format
• 2s complement, MSB first, alternating L/R
serial
• 16/20/24/32-bit data selectable
■ Output data format
28
27
1
2
3
4
LRCI
MDS
DIN
BCKI
VDD1
DITH
CKEN
26 BCKO
25
24
WCKO
DOL
5
6
7
23
22
21
XTI
DOR
VDD2
XTO
VSS1
CKO
VSS2
8
9
20 ASEL1
19 OBS
CKS 10
ASEL2/MDCK 11
HS/MDT 12
18 TEST2
17 TEST1
SYNC/MDLE
RST
DEEM
LRS
13
14
16
15
• 2s complement, MSB first, simultaneous L/R
serial
• 20/24-bit data selectable.
ORDERING INFOMATION
■ 24-bit internal data processing
■ Jitter-free mode/synchronous mode selectable
■ Crystal oscillator circuit built-in
■ TTL-compatible outputs
Device
Package
SM5846AP
28pin DIP
■ Molybdenum-gate CMOS
NIPPON PRECISION CIRCUITS—1
SM5846AP
PACKAGE DIMENSIONS
Unit: mm
28-pin plastic DIP
Audio
ICs
37.3 0.3
+
−
0.3
0.05
1.5
2.54
0.45 0.1
NIPPON PRECISION CIRCUITS—2
SM5846AP
FILTER CHARACTERISTICS
Normal-speed Sampling
Parameter
Rating
Passband bandwidth
Stopband bandwidth
Passband ripple
0 to 0.4535fs
Audio
ICs
0.5465 to 7.4535fs
±0.0004 dB
Stopband attenuation
≥ 75 dB
When CKS is HIGH: 63.89/fs (when SYNC is LOW) and 63.51/fs to 64.26/fs (when SYNC is HIGH)
When CKS is LOW: 63.76/fs (when SYNC is LOW) and 63.59/fs to 64.14/fs (when SYNC is HIGH)
1
Group delay time
1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs).
Overall frequency characteristic
0
20
40
60
80
100
120
140
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency
(fs)
Passband frequency characteristic
-0.0005
-0.00025
0.00000
0.00025
0.0005
0.000
0.125
0.250
0.375
0.500
Frequency
(fs)
Transition band characteristic
0
20
40
60
80
100
120
140
0.00
0.125
0.25
0.375
0.50
0.625
0.75
0.825
1.00
Frequency
(fs)
NIPPON PRECISION CIRCUITS—3
SM5846AP
High-speed Sampling (8fs Output)
Parameter
Passband bandwidth
Stopband bandwidth
Passband ripple
Rating
0 to 0.4535fs
Audio
ICs
0.5465 to 7.4535fs
±0.00001 dB
Stopband attenuation
≥ 105 dB
When CKS is HIGH: 51.91/fs (when SYNC is LOW) and 51.53/fs to 52.28/fs (when SYNC is HIGH)
When CKS is LOW: 51.78/fs (when SYNC is LOW) and 51.40/fs to 52.15/fs (when SYNC is HIGH)
1
Group delay time
1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs).
Overall frequency characteristic
0
20
40
60
80
100
120
140
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency
(fs)
Passband frequency characteristic
-0.0001
-0.00005
0.00000
0.00005
0.0001
0.000
0.125
0.250
0.375
0.500
Frequency
(fs)
Transition band characteristic
0
20
40
60
80
100
120
140
0.00
0.125
0.25
0.375
0.50
0.625
0.75
0.825
1.00
Frequency
(fs)
NIPPON PRECISION CIRCUITS—4
SM5846AP
High-speed Sampling (4fs Output)
Parameter
Passband bandwidth
Stopband bandwidth
Passband ripple
Rating
0 to 0.4535fs
Audio
ICs
0.5465 to 7.4535fs
±0.00001 dB
Stopband attenuation
≥ 104 dB
When CKS is HIGH: 50.78/fs (when SYNC is LOW) and 50.40/fs to 51.15/fs (when SYNC is HIGH)
When CKS is LOW: 50.77/fs (when SYNC is LOW) and 50.40/fs to 51.15/fs (when SYNC is HIGH)
1
Group delay time
1. The time difference due to digital filter operation between the end of serial data input (at rate fs) and the start of serial data output (at rate 8fs).
Overall frequency characteristic
0
20
40
60
80
100
120
140
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Frequency
(fs)
Passband frequency characteristic
-0.0001
-0.00005
0.00000
0.00005
0.0001
0.000
0.125
0.250
0.375
0.500
Frequency
(fs)
Transition band characteristic
0
20
40
60
80
100
120
140
0.125
0.25
0.375
0.50
0.625
0.75
0.825
1.00
Frequency
(fs)
NIPPON PRECISION CIRCUITS—5
SM5846AP
Deemphasis Filter Characteristics (Normal-speed Sampling)
Parameter
Sampling frequency (fs)
Rating
32 kHz
44.1 kHz
0 to 20.0 kHz
±0.01 dB
0 to 6°
48 kHz
Audio
ICs
Passband bandwidth
0 to 14.5 kHz
0 to 21.7 kHz
Attenuation
Phase
Deviation from ideal
characteristics
Deemphasis passband characteristic (logarithmic scale)
The phase traces are from top to bottom fs = 32/44.1/48 kHz, respectively.
0
2
0
Phase
-20
-40
4
6
-60
8
Attenuation
10
10
20
50 100 200
500
1k
2k
5k
10k 20k
Frequency (Hz)
Deemphasis passband characteristic (linear scale)
The phase traces are from top to bottom fs = 32/44.1/48 kHz, respectively.
0
2
0
Phase
-20
-40
-60
4
6
8
Attenuation
10
0
4k
8k
12k
16k
20k 22k 24k
Frequency (Hz)
NIPPON PRECISION CIRCUITS—6
SM5846AP
Deemphasis Filter Characteristics (High-speed Sampling)
Parameter
Sampling frequency (fs)
Rating
64 kHz
88.2 kHz
0 to 40.0 kHz
±0.001 dB
0 to 1°
96 kHz
Audio
ICs
Passband bandwidth
0 to 29.0 kHz
0 to 43.5 kHz
Attenuation
Phase
Deviation from ideal
characteristics
Deemphasis passband characteristic (logarithmic scale)
The phase traces are from top to bottom fs = 64/88.2/96 kHz, respectively.
0
0
2
4
6
8
Phase
-20
-40
-60
Attenuation
10
10
20
50 100 200
500
1k
2k
5k
10k 20k
Frequency (Hz)
Deemphasis passband characteristic (linear scale)
The phase traces are from top to bottom fs = 64/88.2/96 kHz, respectively.
0
0
2
4
6
Phase
-20
-40
-60
8
Attenuation
10
0
4k
8k
12k
16k
20k 22k 24k
Frequency (Hz)
NIPPON PRECISION CIRCUITS—7
SM5846AP
SPECIFICATIONS
Absolute Maximum Ratings
V
= 0 V
Audio
ICs
SS
Parameter
Symbol
Rating
Unit
V
Supply voltage range
Input voltage range
V
−0.3 to 7.0
DD
V
− 0.3 to V + 0.3
V
IN
DD
Storage temperature range
Power dissipation
T
−40 to 125
750
°C
mW
°C
s
stg
P
D
Soldering temperature
Soldering time
T
255
sld
t
10
sld
Recommended Operating Conditions
V
= 0 V
SS
Parameter
Symbol
Rating
4.5 to 5.5
−20 to 70
Unit
V
Supply voltage range
V
DD
Operating temperature range
T
°C
opr
DC Electrical Characteristics
V
= 4.5 to 5.5 V, V = 0 V, T = −20 to 70 °C
SS a
DD
Rating
Parameter
Symbol
Condition
Unit
min
typ
110
–
max
130
–
1
Supply current consumption
HIGH-level input voltage
LOW-level input voltage
I
–
mA
V
DD
V
All inputs
All inputs
0.7V
DD
IH
V
–
–
0.3V
V
IL
DD
XTI AC-coupled input voltage
HIGH-level output voltage
LOW-level output voltage
XTI HIGH-level input current
XTI LOW-level input current
V
0.3V
–
–
–
V
p-p
INAC
DD
V
All outputs, I = −1 mA
V − 0.4
DD
–
V
V
OH
OH
V
All outputs, I = 2 mA
–
–
0.4
20
20
OL
OL
I
V
= V
DD
–
–
10
10
µA
µA
IH
IN
I
V = V
IN SS
IL
Inputs excluding XTI,
= V
LOW-level input current
Input leakage current
I
–
–
10
–
20
µA
µA
IL
V
IN
SS
Inputs excluding XTI,
= DV
I
1.0
LH
V
IN
DD
1. V = 5.0 V, f = 18.432 MHz, 384fs operation, no output load.
DD
sys
NIPPON PRECISION CIRCUITS—8
SM5846AP
AC Characteristics
XTI input timing
V
= 4.5 to 5.5 V, V = 0 V, T = −20 to 70 °C
SS a
Audio
ICs
DD
Rating
Parameter
Symbol
Condition
Unit
min
10
typ
–
max
18.5
–
Oscillator frequency
f
MHz
ns
OSC
XTI clock pulse cycle time
t
54
–
XI
XTI HIGH-level clock pulsewidth
XTI LOW-level clock pulsewidth
t
24
–
–
ns
CWH
t
24
–
–
ns
CWL
XTI
0.5VDD
tCHW
tCHW
tXI
RST input timing
V
= 4.5 to 5.5 V, V = 0 V, T = −20 to 70 °C
SS a
DD
Rating
Parameter
Symbol
Condition
Unit
min
1
typ
–
max
–
When power is applied
At all other times
µs
ns
Reset pulsewidth
t
RST
50
–
–
0.5VDD
RST
tRST
NIPPON PRECISION CIRCUITS—9
SM5846AP
Serial data input timing (BCKI, DIN, LRCI)
= 4.5 to 5.5 V, V = 0 V, T = −20 to 70 °C
V
DD
SS
a
Audio
ICs
Rating
Parameter
Symbol
Condition
Unit
min
100
50
typ
–
max
–
BCKI pulse cycle time
BCKI HIGH-level pulsewidth
BCKI LOW-level pulsewidth
DIN setup time
t
ns
ns
ns
ns
ns
ns
ns
BCY
t
–
–
BCWH
t
50
–
–
BCWL
t
20
–
–
DS
DIN hold time
t
20
–
–
DH
BCKI rising edge to LRCI edge time
LRCI edge to BCKI rising edge time
t
50
–
–
BL
t
50
–
–
LB
tBCY
tBCWH
tBCWL
0.5VDD
BCKI
DIN
t
DS
t
DH
0.5VDD
0.5VDD
VALID
tLB
tBL
LRCI
NIPPON PRECISION CIRCUITS—10
SM5846AP
Microprocessor serial interface timing (MDCK, MDT, MDLE)
V
= 4.5 to 5.5 V, V = 0 V, T = −20 to 70 °C
SS a
DD
Audio
ICs
Rating
Parameter
MDCK pulse cycle time
Symbol
Condition
Unit
min
100
50
typ
–
max
t
–
–
–
–
–
ns
ns
ns
ns
ns
MCY
MDCK HIGH-level pulsewidth
MDCK LOW-level pulsewidth
MDT setup time
t
–
MCWH
t
50
–
MCWL
t
20
–
MDS
MDT hold time
t
20
–
MDH
MDCK rising edge to MDLE edge
time
t
50
50
–
–
–
–
ns
ns
MCL
MDLE edge to MDCK rising edge
time
t
MLC
MDLE HIGH-level pulsewidth
MDLE LOW-level pulsewidth
t
20
20
–
–
–
–
ns
ns
MLWH
t
MLWL
tMCY
tMCWH
tMCWL
0.5VDD
MDCK
MDT
tMDS
tMDH
0.5VDD
0.5VDD
tMCL
tMCL
MDLE
tMLWL
tMLWH
NIPPON PRECISION CIRCUITS—11
SM5846AP
Output signal timing (CKO, BCKO, DOR, DOL, WCKO)
V
= 4.5 to 5.5 V, V = 0 V, T = −20 to 70 °C, C = 15 pF
DD
SS
a
L
Rating
typ
17
17
20
20
20
20
–
Audio
ICs
Parameter
Symbol
Condition
Unit
min
–
max
35
35
60
60
60
60
15
15
15
15
15
15
t
CKH
XTI to CKO propagation delay time
XTI to BCKO propagation delay time
ns
t
–
CKL
t
–
sbH
Normal and high-speed
mode 4fs output
t
–
sbL
ns
t
–
sbH
High-speed mode 8fs
output
t
–
sbL
t
−5
−5
−5
−5
−5
−5
bdH
BCKO to DOR propagation delay
time
ns
ns
ns
t
–
bdL
t
–
bdH
BCKO to DOL propagation delay time
t
–
bdL
t
–
bdH
BCKO to WCKO propagation delay
time
t
–
bdL
CKO output
XTI
0.5VDD
tCKH
tCKL
CKO
1.5V
NIPPON PRECISION CIRCUITS—12
SM5846AP
BCKO output
Audio
ICs
0.5VDD
1.5V
XTI
tsbH
BCKO *1
BCKO *2
tsbL
tsbH
1.5V
tsbL
*1 : High speed mode 8fs output
*2 : Normal and high-speed mode 8fs output
DOR, DOL, WCKO output
1.5V
BCKO
tbdH
tbdL
DOR
DOL
1.5V
WCKO
NIPPON PRECISION CIRCUITS—13
SM5846AP
PIN DESCRIPTION
1
Number
1
Name
DIN
I/O
Description
Ip
Ip
–
Data input
Audio
ICs
2
BCKI
Bit clock input
3
VDD1
DITH
5V supply voltage
Dither ON/OFF control
Crystal oscillator operation enable
4
Ip
Ip
I
5
CKEN
XTI
6
Crystal oscillator input/external clock input
Crystal oscillator output
7
XTO
O
–
8
VSS1
Ground
9
CKO
O
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
–
Master clock output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CKS
Master clock input frequency select
Operating mode select/microprocessor interface clock input
Operating mode select/microprocessor interface data input
Sync mode select/microprocessor interface latch enable input
Reset input
ASEL2/MDCK
HS/MDT
SYNC/MDLE
RST
LRS
LR clock polarity select
DEEM
TEST1
TEST2
OBS
Deemphasis ON/OFF select
Test pin 1.Tie HIGH or leave open for normal operation.
Test pin 2.Tie LOW for normal operation.
Output data length select
ASEL1
VSS2
Operating mode select
Ground
VDD2
DOR
–
5V supply voltage
O
O
O
O
Ip
Ip
Right-channel data output
DOL
Left-channel data output
WCKO
BCKO
MDS
Word clock output
Output data bit clock output
Mode set method select
LRCI
LR clock input
1. Ip = input pin with pull-up resistor, I = input, O = output
NIPPON PRECISION CIRCUITS—14
SM5846AP
BLOCK DIAGRAM
Audio
ICs
Reset Circuit
Clock Generator
DOR
Output data
Interface
DOL
BCKO
WCKO
(serial output)
Output data
Interface
(serial input)
DIN
Arithmetic Block
Control
BCKI
LRCI
LRS
OBS
Control
Control
DITH
Micro controller
Interface
(serial input)
Operation Mode
Control
NIPPON PRECISION CIRCUITS—15
SM5846AP
SYSTEM CONFIGURATION
Setting
+5V
DOR
DOL
DIN
BCKI
LRCI
DAC
BCKO
WCKO
DSP
Setting
Reset Circuits
+5V
Oscilation
Control
DATA FLOW
ATT1/ATT2 soft muting uses the D-ATT function to set the gain to −∞.
Normal-speed sampling (fs = 32/44.1/48 kHz)
FIRI
DEMI
DLY
ATT1
FIR2
FIR3
fs
LPF
LPF
LPF
IN
(fs)
8fs
4fs
2fs
2fs
2fs
2fs
OUT
(8fs)
(×2)
(×2)
(×2)
2fs
SWa (121 order)
2fs
2fs
2fs
4fs
(21 order)
8fs
(13 order)
(D-ATT / Soft Mute)
High-speed sampling (fs = 64/88.2/96 kHz)
FIR4
FIR5
DEM2
ATT2
FIR6
LPF
(×2)
LPF
(×2)
LPF
(×2)
4fs
fs
2fs
4fs
4fs
8fs
IN
(fs)
2fs
SWb(177 order)
4fs
(29 order)
4fs
4fs
8fs
(17 order)
8fs/4fs
(D-ATT / Soft Mute)
SWd(ON / OFF)
OUT
( 8fs / 4fs )
SWg ( 8fs / 4fs )
4fs
NIPPON PRECISION CIRCUITS—16
SM5846AP
FUNCTIONAL DESCRIPTION
Mode Switching and Function Switching
The SM5846AP supports several operating modes and
function switches. Internal control flags, set by the digital
inputs or serial data input signal from a microprocessor,
determine the status of those function switches.
Mode switching/function switch controls
Control request
Stage
Name
Function
Input
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Control flag
System
MDS
HS
IC control request switch (input pin/control flag)
Yes
Yes
Yes
Operating mode switch
Clock switch
ASEL2
ASEL1
CKS
Operating mode switching
Input clock frequency switching
CKEN
DEEM
FSEL2
FSEL1
MUTE
Crystal oscillator operating control switching
Deemphasis ON/OFF switching
Yes
Yes
Yes
Yes
Deemphasis filter sampling frequency set
Filter switch
Mute ON/OFF control
Dither ON/OFF control
Yes
Yes
DITH
(pos. logic)
(neg. logic)
SYNC
LRS
Yes
Yes
Yes
Jitter-free/sync mode switching
LRCI (LR clock) input polarity switching
Input interface switch
Output interface switch
IBS2
IBS1
OBS
Yes
Yes
Yes
Input data length set
Output data length set
Yes
Control request switching
MDS input and device control
Input pin functions when MDS is LOW
Mode switching/function switching is performed under
input pin control when MDS is HIGH, and under internal
flag control when MDS is LOW.
All pins that are part of the microprocessor interface
can be used whenever MDS is LOW.
Pin name
Function
Notes
1
MDS
HIGH
LOW
Control request
Input pins
Serial data transfer data
clock
HS/MDT
Used for the
microprocessor
interface
ASEL2/MDC Serial data transfer clock
Control flags
K
input
1. Switching MDS during device operation is prohibited.
Serial data transfer latch
enable input
SYNC/MDLE
CKS
CKEN
LRS
CKS function switch input
CKEN function switch input
LRS function switch input
Input pin control only
because there is no
corresponding
control flag.
NIPPON PRECISION CIRCUITS—17
SM5846AP
Control flag functions when MSD is HIGH
(default)
Other requests are controlled by internal flag only
because there is no corresponding input pin. These
control flags are valid when MDS is HIGH. The
default values are shown in the following table.
Flag name
FSEL2
FSEL1
MUTE
IBS2
Default value
HIGH
Default setting
44.1 kHz deemphasis filter
sampling frequency
HIGH
HIGH
Muting OFF
LOW
16-bit input data length
IBS1
HIGH
Clock Functions
Input clock frequency switching (CKS)
This switch is used to select the input clock fre-
quency—384fs or 512fs (normal-speed sampling),
and 192fs or 256fs (high-speed sampling).
System clock
Frequency (MHz)
CKS
Input sampling frequency fs (kHz)
Notes
(× fs)
512fs
256fs
32
64
16.384
16.384
12.288
16.9344
18.432
12.288
16.9344
18.432
Normal-speed sampling mode
High-speed sampling mode
LOW
32
44.1
48
384fs
192fs
Normal-speed sampling mode
High-speed sampling mode
HIGH
64
88.2
96
Crystal oscillator control switch (CKEN)
This switch is used to start/stop the crystal oscillator
circuit.
CKEN
HIGH
LOW
Crystal oscillator operation
Oscillating
Stopped
NIPPON PRECISION CIRCUITS—18
SM5846AP
Crystal oscillator circuit
The built-in crystal oscillator circuit comprises a
feedback resistor and several logic gates. The system
clock can be generated using an external quartz crys-
tal and 2 capacitors.
System
Clock
Rf
CKEN
XTI
C1
CKO
XTO
C2
X'tal
System Clock
Output
Oscilation/Stop
Contorol
External clock
When an external clock is used, XTO is left open-
circuit and the clock signal is input on XTI.
System
Clock
Rf
XTO
CKEN
XTI
CKO
Open
System Clock
Output
External Clock
Input
Oscilation/ Stop
Contorol
NIPPON PRECISION CIRCUITS—19
SM5846AP
Filter Stage
Other control settings
Input data length select
Operating mode
The SM5846A supports 3 different operating modes
to control output data rate switching. The operating
mode is selected by the state of HS, ASEL1 and
ASEL2.
ISB1 and ISB2 flags are used to set the input data
length.
Input data
IBS2
IBS1
Notes
length
20 bits
24 bits
16 bits
32 bits
1
Operating mode
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
HS
ASEL1 ASEL2
The length is set to the
default value of 16 bits
(IBS2 = LOW and IBS1 =
HIGH) after a reset.
Speed
Oversampling
Normal-speed
sampling
HIGH
LOW
LOW
HIGH
HIGH
8-times
HIGH
LOW
8-times
4-times
High-speed
sampling
LRCI input polarity select
1. Only the above 3 modes are valid.
Pin LRS is used to set the LRCI input polarity.
Operating speed and sampling frequency
LRS
LRCI
HIGH
LOW
HIGH
LOW
Input channel
Left
The SM5846AP supports sampling frequencies of
32/44.1/48 kHz (normal-speed sampling mode) and
64/88.2/96 kHz (high-speed sampling mode).
HIGH
HIGH
LOW
LOW
Right
Right
Operating speed
Normal-speed sampling
High-speed sampling
Input sampling frequency
32/44.1/48 kHz
Left
64/88.2/96 kHz
Sync mode select
The SYNC pin or flag setting can be used to select
either jitter-free mode or sync mode to control syn-
chronization between input data and internal arith-
metic blocks.
Deemphasis filter
The SM5846AP contains a digital deemphasis filter
controlled by DEEM.
DEEM
HIGH
LOW
Deemphasis
ON
SYNC
HIGH
LOW
Mode
Notes
Jitter-free mode
Sync mode
The SYNC flag is set HIGH
(default) after a reset.
OFF
The sampling frequency is selected by FSEL1 and
FSEL2.
Sampling frequency fs (kHz)
FSEL2 FSEL1
Normal-speed
sampling
High-speed
sampling
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
44.1
48
88.2
96
44.1
32
88.2
64
Digital attenuator
The digital attenuator is controlled by serial data
from the microprocessor interface. This data can set
attenuation and muting. Note that the digital attenua-
tor is only enabled when MDS is LOW. ATT1 and
ATT2 are used to set the attenuation in normal-speed
sampling and high-speed sampling, respectively.
NIPPON PRECISION CIRCUITS—20
SM5846AP
Attenuation setting
The data stored in the D-ATT attenuation register,
accessed through the microprocessor interface,
determines the attenuation setting of the digital
attenuator. The D-ATT register data format is shown
below.
bit1
"0"
bit2
a1
bit3
a2
bit4
a3
bit5
a4
bit6
a5
bit7
a6
bit8
a7
MSB
DATT attenation data (7bit)
Register information
LSB
The attenuation setting is given by the following
equations.
Attenuation = 0 [dB]
(DATT = 0)
127 – DATT
------------------------------
128
(0 < DATT <127)
(DATT = 127)
Attenuation = 20log
[dB]
10
Attenuation = –∞
The attenuation for a selection of values is given in
the following table.
Digital attenuator operation
The attenuation register is reset to 0 (attenuation = 0
dB) after a system reset signal.
Microprocess
or command
(hex)
DATT register
value
Attenuation
(dB)
Relative gain
When data is written to the attenuation register,
through the microprocessor interface, the attenuation
changes from the current value to the new value at
the speed shown in the following table.
0
1
00H
01H
02H
↓
0
× 1.0
−0.137
−0.206
↓
× 0.984375
× 0.9765625
↓
2
Speed of
attenuation change
Time from min. to
max. attenuation
Operating speed
↓
Normal-speed
sampling
1016/fs (23.0 ms at
44.1 kHz)
63
64
↓
3FH
40H
↓
−6.021
−6.157
↓
× 0.5
8/fs per step change
× 0.4921875
↓
2032/fs (23.0 ms at
88.2 kHz)
High-speed sampling 16/fs per step change
125
126
127
7DH
7EH
7FH
−36.12
−42.14
× 0.015625
× 0.0078125
× 0
Soft muting operation
Soft muting ON/OFF is controlled by the MUTE
flag, accessed through the microprocessor interface.
−∞
MUTE Muting
Notes
HIGH
LOW
OFF
ON
The MUTE flag is set HIGH (default) after a
system reset.
When muting is ON, the attenuation ramps down to
−∞ at the speed shown in the table. Similarly when
muting is OFF, the attenuation level returns to the
original value at the same speed.
If the contents of the DATT attenuation register are
changed while muting is ON (attenuation = −∞),
only the register contents are replaced. If muting is
subsequently turned OFF, the attenuation value
changes to the new value at the same speed as shown
in the table.
NIPPON PRECISION CIRCUITS—21
SM5846AP
Output data round-off
Dither round-off
Output data round-off processing is required because
the internal data length of the digital filter is different
from the output data length (internal data processing
width > output data width).
Dither round-off is carried out by adding a pseudo-
random number between 0 and 1 LSB, derived from
a rectangular distribution, to the filter output data to
form 20/24-bit output data, depending on the
selected output data length. The random number
rectangular distribution is shown below (average =
1/2 LSB).
The SM5846AP can select either normal round-off
or dither round-off on the output data. Round-off
processing can be selected either by input pin or con-
trol flag settings.
Output
data
round-off
DITH
pin
DITH
flag
MDS
Notes
Probavility
Dither
round-off
HIGH
LOW
HIGH
×
Normal
round-off
The DITH flag is set
HIGH (default) after a
system reset.
Normal
round-off
0
1/2
1
(LSB)
HIGH
LOW
LOW
×
Dither
round-off
Overflow limiter
Normal round-off
If an overflow or underflow condition occurs after
round-off or filter arithmetic processing, the output
data will be fixed at positive or negative maximum
value.
Normal round-off is carried out by adding 1/2 LSB
to the filter output data to form 20/24-bit output data,
depending on the selected output data length.
NIPPON PRECISION CIRCUITS—22
SM5846AP
Audio data input interface pins
Audio Data Input Interface
Audio data is input using pins LRCI, BCKI, and
DIN. The LRCI input polarity is determined by pin
LRS.
Serial data transmission is used for the digital audio
data input.
Audio
ICs
The data has the following format:
Pin name
LRCI
BCKI
DIN
Function
Left/right-channel latch clock input
Bit transfer clock input
■ 16/20/24/32-bit data length
■ Alternating left/right-channel serial data transmis-
sion
■ MSB first
Serial data input
■ Rear packed
■ 2s complement for negative values
LRS
LRCI input polarity switch
Serial data on DIN is input to the serial-to-parallel
shift register on the falling edge of the bit transfer
clock BCKI. The parallel data is then stored in the
left/right-channel input buffers on the HIGH/LOW-
level pulse of the LRCI latch clock signal, depend-
ing on the selected polarity of the LRCI clock.
Audio data input interface schematic
32bit SIPO Shiftregister
D
DIN
C
Q
BCKI
32bitRegister
32bitRegister
D
D
Right channel
Input Data Buffer
Left channel
Input Data Buffer
Q
C
C
Q
LRCI
LRS
Left channel
Input Data
Right channel
Input Data
NIPPON PRECISION CIRCUITS—23
SM5846AP
Input data interface example (LRS = HIGH)
32-bit input data length
Audio
ICs
fs
Right channel Input Data
Left channel Input Data
(MSB)
(LSB) (MSB)
(LSB)
31
30
29
28
2
1
0
31
30
29
28
2
1
0
DIN
BCKI
(64fs)
LRCI
24-bit input data length
fs
Right channel Input Data
Left channel Input Data
(LSB)
(MSB)
(LSB)
(MSB)
23
22
2
1
0
23
22
2
1
0
DIN
BCKI
(64fs)
LRCI
20-bit input data length
fs
Left channel
Input Data
Right channel
Input Data
(MSB)
(LSB)
(MSB)
(LSB)
19
18
2
1
0
19
18
2
1
0
DIN
BCKI
(64fs)
LRCI
16-bit input data length
fs
Right channel
Input Data
Left channel
Input Data
(MSB)
(LSB)
(MSB)
(LSB)
15
14
1
0
15
14
1
0
DIN
BCKI
(64fs)
LRCI
NIPPON PRECISION CIRCUITS—24
SM5846AP
Input data validity
32-bit input data length
8
6
4
2
0
31 30
28
26
24
Polarity
Mark
Decimal point
Effective Number of Bits (24bits)
Low order 8 bits cut it off
(No round-offattention)
Input Data (32bits)
24-bit input data length
23 22
20
18
16
6
4
2
0
Polarity
Mark
Decimal point
Effective Number of Bits (24Bits)
Input Data (24Bits)
20-bit input data length
19 18
16
14
4
2
0
0
0
0
0
Polarity
Mark
Decimal point
Effective Number of bits (24bits)
Input Data (20bits)
Input to "0"(4 bits)
16-bit input data length
15 14
12
2
0
0 0 0 0 0 0 0 0
Polarity
Mark
Decimal point
Effective Number of Bits (24bits)
Input to "0"(8 bits)
Input Data (16bits)
NIPPON PRECISION CIRCUITS—25
SM5846AP
Audio Data Output Interface
Serial data is output on DOL and DOR on the fall-
ing edge of the bit transfer clock BCKO. Generally,
external circuits, such as a serial D/A converter,
sample the serial data output on DOL and DOR on
the rising edge of the bit transfer clock signal, and
then shift the data into a register. At the completion
of one data cycle (20/24-bit selectable) transfer, the
word clock WCKO goes LOW with a 50% duty
ratio. Then the external circuit writes parallel data to
a buffer register on the falling edge of word clock
WCKO.
Serial data transmission is used for the digital audio
data output.
Audio
ICs
The data has the following format:
■ 20/24-bit data length
■ Simultaneous left/right-channel serial data transmis-
sion
■ MSB first
■ Bit transfer clock burst (NPC format)
■ 2s complement for negative values
Audio data output interface pins
Output data length select
Audio data is output using pins WCKO, BCKO, DOL
and DIN.
The output data length is set by either the OBS pin
or flag.
Pin name
WCKO
BCKO
DOL
Function
Output data
OBS
Notes
length
24 bits
20 bits
Word clock output
HIGH
LOW
The OBS flag is set LOW
(default) after a system reset.
Bit transfer clock output
Left-channel serial data output
Right-channel serial data output
DOR
NIPPON PRECISION CIRCUITS—26
SM5846AP
Audio data output interface
L-ch Serial DAC
DOL
D
Audio
ICs
VOUT(L-ch)
VO
C
Following Block
STB
R-ch Serial DAC
D
C
DOR
D
C
20/24bit
SIPO
Shiftregister
BCKO
WCKO
STB
D
20/24bit SIPO
Shiftregister
IN
VOUT(R-ch)
VO
DAC
output data format
24-bit output data length
23 22
20
18
16
6
4
2
0
Polarity
Mark
Decimal point
Output Data (24bits)
20-bit output data length
19 18
16
14
4
2
0
Polarity
Mark
Decimal point
Output Data (20bits)
NIPPON PRECISION CIRCUITS—27
SM5846AP
Audio data output timing
Normal-speed sampling: 384fs clock, 24-bit data output, 8fs output data rate
Audio
ICs
1 frame (1/8fs)
1
10
12
20
24
fCK/2
(192fs)
WCKO
BCKO
DOL
3
2
1
0
23
22
21
20
DOR
MSB
LSB
24bits
Normal-speed sampling: 384fs clock, 20-bit data output, 8fs output data rate
1 frame (1/8fs)
1
2
10
12
20
21
24
fCK/2
(192fs)
WCKO
BCKO
DOL
19
18
17
1
0
DOR
MSB
LSB
20bits
NIPPON PRECISION CIRCUITS—28
SM5846AP
Normal-speed sampling: 512fs clock, 24-bit data output, 8fs output data rate
Audio
ICs
1 frame (1/8fs)
1
2
13
14
15
16
17
18
25
30
32
fCK/2
(256fs)
WCKO
BCKO
DOL
23
22
21
0
DOR
MSB
LSB
24bits
Normal-speed sampling: 512fs clock, 20-bit data output, 8fs output data rate
1 frame (1/8fs)
1
2
13
14
15
16
17
18
19
20
21
30
32
fCK/2
(256fs)
WCKO
BCKO
DOL
DOR
19
18
17
0
MSB
LSB
20bits
NIPPON PRECISION CIRCUITS—29
SM5846AP
High-speed sampling: 192fs clock, 24-bit data output, 8fs output data rate
Audio
ICs
1 frame (1/8fs)
20
21
1
2
10
12
24
fCK
(192fs)
WCKO
BCKO
DOL
23
22
21
20
3
2
1
0
DOR
MSB
LSB
24bits
High-speed sampling: 192fs clock, 20-bit data output, 8fs output data rate
1 frame (1/8fs)
1
2
10
12
20
21
24
fCK
(192fs)
WCKO
BCKO
DOL
19
18
17
1
0
DOR
MSB
LSB
20bits
NIPPON PRECISION CIRCUITS—30
SM5846AP
High-speed sampling: 256fs clock, 24-bit data output, 8fs output data rate
Audio
ICs
1 frame (1/8fs)
1
2
13
14
15
16
17
18
25
30
32
fCK
(256fs)
WCKO
BCKO
DOL
DOR
23
22
21
0
MSB
LSB
24bits
High-speed sampling: 256fs clock, 20-bit data output, 8fs output data rate
1 frame (1/8fs)
1
2
13
14
15
16
17
18
19
20
21
30
32
fCK
(256fs)
WCKO
BCKO
DOL
19
18
17
0
DOR
LSB
MSB
20bits
NIPPON PRECISION CIRCUITS—31
SM5846AP
High-speed sampling: 192fs clock, 24-bit data output, 4fs output data rate
1 frame (1/4fs)
1
10
12
20
24
fCK/2
(96fs)
WCKO
BCKO
DOL
DOR
23
22
21
20
3
2
1
0
MSB
LSB
24bits
High-speed sampling: 192fs clock, 20-bit data output, 4fs output data rate
1 frame (1/4fs)
1
21
20
10
12
24
fCK/2
(96fs)
WCKO
BCKO
DOL
DOR
0
1
19
18
17
MSB
LSB
20bits
NIPPON PRECISION CIRCUITS—32
SM5846AP
High-speed sampling: 256fs clock, 24-bit data output, 4fs output data rate
1 frame (1/4fs)
1
18
17
2
13
14
16
25
30
15
32
fCK/2
(128fs)
WCKO
BCKO
DOL
DOR
0
23
22
21
LSB
MSB
24bits
High-speed sampling: 256fs clock, 20-bit data output, 4fs output data rate
1 frame (1/4fs)
1
2
13
14
15
16
17
18
19
20
21
30
32
fCK/2
(128fs)
WCKO
BCKO
DOL
0
19
18
17
DOR
LSB
MSB
20bits
NIPPON PRECISION CIRCUITS—33
SM5846AP
Microprocessor Interface
Microprocessor interface pins
Pin name
Function
MDT
Serial data input
When MDS is LOW, the SM5846AP is controlled by
internal flags set by serial data transferred over the
microprocessor interface comprising MDLE, MDCK
and MDT.
Internal control flag serial data on MDT is input into
an internal shift register on the rising edge of
MDCK. After 8-bit data has been input, the data in
the shift register is stored in one of four internal flag
registers on the rising edge of MDLE latch enable.
Pin name
MDLE
Function
The address of the flag register is derived by decod-
ing bits 1 to 3 of the 8-bit data.
Microprocessor data latch enable input
Microprocessor data transfer clock input
MDCK
Microprocessor interface
8bit SIPO Shift Register
D
MDT
C
MDCK
Q
8bit Register
8bit Register
8bit Register
8bit Register
D
D
Q
D
Q
D
Q
C
C
C
C
Q
Decoder
MDLE
D-ATT Attenation
Mode flag1
Mode flag2
Mode flag3
Microprocessor interface data input timing
MDCK and MDLE can also follow the dotted lines above
MDLE
MDCK
MDT
bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8
MSB LSB
NIPPON PRECISION CIRCUITS—34
SM5846AP
Serial data format
Register
D-ATT attenuation
Mode flag 1
Bit 1
Bit 2
a1
0
Bit 3
Bit 4
Bit 5
a4
Bit 6
a5
Bit 7
a6
Bit 8
0
1
1
1
a2
a3
a7
SYNC
MUTE
ASEL1
TEST1 = 0
DITH
HS
OBS
1
FSEL1
IBS1
FSEL2
IBS2
1
DEEM
Mode flag 2
1
1
0
Mode flag 3
1
ASEL2
TEST2 = 0
Address information is displayed in double-line cells of the table.
Test bits (mode flag 1 bit 4 and mode flag 3 bit 6) should be set to 0.
A 0.01 µF external capacitor is recommended. How-
ever, the time constant can be lengthened if longer
time is required for the XTI and LRCI clocks to sta-
bilize after power-ON.
System Reset
When a reset is necessary
The external capacitor discharges through the inter-
nal pull-up resistor at power-OFF as this is the only
possible discharge path. This could cause reset fail-
ure if power is reapplied while the external capacitor
is discharging. Therefore, a diode should be con-
nected between RST and VDD to quickly discharge
the capacitor and ensure correct power-ON reset
operation.
The device must be reset under the following condi-
tions.
■ When power is first applied
■ When the LRCI clock or system clock stop
Reset input conditions
The RST input is active LOW.
External power-ON reset circuit
At power-ON reset, RST must go LOW and then go
HIGH after the XTI and LRCI clocks stabilize (reset
release).
Reset timing
Discharge
for Diode
The internal arithmetic registers and output sequence
are initialized on the rising edge of the LRCI clock
after reset release. The internal control flags and D-
ATT attenuation register are initialized after RST
goes LOW. Outputs DOL and DOR are tied LOW
while RST is LOW.
Internal Pull-up Register
RST
Schmitt Buffer
External
Capacitor
C
Power-ON reset using a capacitor
The RST input configuration is a Schmitt-trigger
input with a pull-up resistor, which means that a sim-
ple power-ON reset circuit can be made by connect-
ing a capacitor between RST and VSS as shown
below.
‘
Internal Pull-up Register
RST
Schmitt Buffer
External
C
Capacitor
NIPPON PRECISION CIRCUITS—35
SM5846AP
register initial values
Internal control flag/D-ATT attenuator
Register
D-ATT attenuation
Mode flag 1
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
a4 = 0
HS = 1
OBS = 0
1
Bit 6
Bit 7
a6 = 0
Bit 8
0
1
1
1
a1 = 0
a2 = 0
a3 = 0
a5 = 0
a7 = 0
Audio
ICs
0
1
1
SYNC = 1
MUTE = 1
ASEL1 = 1
TEST1 = 0
DITH = 1
ASEL2 = 1
FSEL1 = 1
IBS1 = 1
TEST2 = 1
FSEL2 = 1
IBS2 = 0
1
DEEM = 0
Mode flag 2
1
0
Mode flag 3
When external muting is required
Test Precautions
The SM5846AP has a relatively long group delay
time because multi-stage filters are employed to
achieve the desired filter characteristics. Under the
following conditions, undesirable noise output can
occur during the group delay time period. In this
case, it may be necessary to use external muting.
The following conditions should be maintained for
normal operation.
■ MDS and DITH inputs should not be simulta-
neously LOW.
■ TEST1 (bit 4 of mode flag 1 register) should not
be set to 1.
■ When power is first applied.
The state of internal registers may be undefined
during power-ON.
■ When switching the operating mode.
When switching the operating mode using HS,
ASEL1 and ASEL2, the internal register assign-
ments may be changed.
■ TEST2 (bit 4 of mode flag 3 register) should be set
to 0 after system reset (including power-ON).
■ Mode flag 3 register bit 5 and/or bit 7 should not
be set to 0.
■ If the LRCI and/or XTI clock stop.
If a disturbance occurs during an input data cycle,
normal filter output may not be achieved.
■ When switching deemphasis ON/OFF.
Switching the deemphasis filter parameters may
cause switching noise output.
■ When switching the sampling frequency (clock
frequency).
■ When switching between input/output data for-
mats (including LRCI clock polarity switching).
Note that switching MDS is inhibited during system
operation.
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2 chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
NIPPON PRECISION CIRCUITS INC.
Facsimile: 03-3642-6698
NC9616BE 1998.01
NIPPON PRECISION CIRCUITS—36
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