74F402 [NSC]
Serial Data Polynomial Generator/Checker; 串行数据多项式发生器/校验器
| 型号： | 74F402 |
| 厂家： | 
National Semiconductor |
| 描述： | Serial Data Polynomial Generator/Checker |
| 文件： | 总12页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1995
54F/74F402 Serial Data Polynomial
Generator/Checker
General Description
Features
Y
Y
Y
Y
Y
Y
Y
Y
Guaranteed 30 MHz data rate
Six selectable polynomials
Other polynomials available
Separate preset and clear controls
Expandable
The ’F402 expandable Serial Data Polynomial generator/
checker is an expandable version of the ’F401. It provides
an advanced tool for the implementation of the most widely
used error detection scheme in serial digital handling sys-
tems. A 4-bit control input selects one-of-six generator poly-
nomials. The list of polynomials includes CRC-16, CRC-
Automatic right justification
Error output open collector
Typical applications:
CCITT and Ethernet , as well as three other standard poly-
É
th
th
nd
nomials (56 order, 48 order, 32 order). Individual clear
and preset inputs are provided for floppy disk and other
applications. The Error output indicates whether or not a
transmission error has occurred. The CWG Control input
inhibits feedback during check word transmission. The
Floppy and other disk storage systems
Digital cassette and cartridge systems
Data communication systems
’F402 is compatible with FAST devices and with all TTL
families.
É
Package
Number
Commercial
Military
Package Description
74F402PC
N16E
J16A
W16A
E20A
16-Lead (0.300 Wide) Molded Dual-In-Line
×
54F402DM (Note 1)
54F402FM (Note 1)
54F402LM (Note 1)
16-Lead Ceramic Dual-In-Line
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
DMQB, FMQB and LMQB.
e
Note 1: Military grade device with environmental and burn-in processing. Use suffix
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9535–1
TL/F/9535–2
TL/F/9535–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
EthernetÉ is a registered trademark of Xerox Corporation.
C
1995 National Semiconductor Corporation
TL/F/9535
RRD-B30M105/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
HIGH/LOW
Output I /I
OH OL
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
S –S
0
Polynomial Select Inputs
Check Word Generate Input
Serial Data/Check Word
Data Input
1.0/0.67
1.0/0.67
3
CWG
b
b
b
5.7 mA( 2 mA)/8 mA (4 mA)
D/CW
D
285(100)/13.3(6.7)
1.0/0.67
b
20 mA/ 0.4 mA
ER
RO
CP
Error Output
*/26.7(13.3)
285(100)/13.3(6.7)
1.0/0.67
*/16 mA (8 mA)
b
Register Output
Clock Pulse
5.7 mA( 2 mA)/8 mA (4 mA)
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
SEI
RFB
MR
P
Serial Expansion Input
Register Feedback
Master Reset
1.0/0.67
1.0/0.67
1.0/0.67
Preset
1.0/0.67
*Open Collector
Functional Description
The ’F402 Serial Data Polynomial Generator/Checker is an
expandable 16-bit programmable device which operates on
serial data streams and provides a means of detecting
transmission errors. Cyclic encoding and decoding schemes
for error detection are based on polynomial manipulation in
modulo arithmetic. For encoding, the data stream (message
polynomial) is divided by a selected polynomial. This divi-
sion results in a remainder (or residue) which is appended to
the message as check bits. For error checking, the bit
stream containing both data and check bits is divided by the
same selected polynomial. If there are no detectable errors,
this division results in a zero remainder. Although it is possi-
ble to choose many generating polynomials of a given de-
gree, standards exist that specify a small number of useful
polynomials. The ’F402 implements the polynomials listed in
Table I by applying the appropriate logic levels to the select
XOR gates. The Check Word Generate (CWG) must be held
HIGH while the data is being entered. After the last data bit
is entered, the CWG is brought LOW and the check bits are
shifted out of the register(s) and appended to the data bits
(no external gating is needed).
To check an incoming message for errors, both the data
and check bits are entered through the D Input with the
CWG Input held HIGH. The Error Output becomes valid af-
ter the last check bit has been entered into the ’F402 by a
LOW-to-HIGH transition of CP, with the exception of the
Ethernet polynomial (see Applications paragraph). If no de-
tectable errors have occurred during the data transmission,
the resultant internal register bits are all LOW and the Error
Output (ER) is HIGH. If a detectable error has occurred, ER
is LOW. ER remains valid until the next LOW-to-HIGH tran-
sition of CP or until the device has been preset or reset.
pins S , S , S and S .
2
0
1
3
A HIGH on the Master Reset Input (MR) asynchronously
clears the entire register. A LOW on the Preset Input (P)
asynchronously sets the entire register with the exception
of:
The ’F402 consists of a 16-bit register, a Read Only Memory
(ROM) and associated control circuitry as shown in the
Block Diagram. The polynomial control code presented at
inputs S , S , S and S is decoded by the ROM, selecting
2
0
1
3
1 The Ethernet residue selection, in which the registers
containing the non-zero residue are cleared;
the desired polynomial or part of a polynomial by establish-
ing shift mode operation on the register with Exclusive OR
(XOR) gates at appropriate inputs. To generate the check
bits, the data stream is entered via the Data Inputs (D), us-
ing the LOW-to-HIGH transition of the Clock Input (CP). This
data is gated with the most significant Register Output (RO)
via the Register Feedback Input (RFB), and controls the
2 The 56th order polynomial, in which the 8 least significant
register bits of the least significant device are cleared;
and,
e
3 Register S 0, in which all bits are cleared.
2
TABLE I
Select Code
Hex
Polynomial
Remarks
S
3
S
S
S
0
2
1
e
0
0
L
L
L
L
0
S
32
X
12
X
26
23
10
22
8
16
a
a
a
a
a
a
a
a
C
D
H
H
H
H
L
L
L
X
X
X
X
X
X
X
7
Ethernet
11
5
X
4
X
2
X
a
a
a
a
a
a
H
X
X
1
Polynomial
32
X
15
X
31
X
13
X
27
12
26
11
25
9
19
16
X
a
a
a
a
a
a
a
a
a
a
a
E
F
H
H
H
H
H
H
L
X
X
X
X
X
X
X
Ethernet
Residue
7
6
5
4
X
2
X
a
a
a
a
a
a a
X 1
H
X
X
X
16
15
2
5
a
a
a
a
a
7
L
H
L
H
H
H
H
X
X
X
X
X
X
1
1
CRC-16
16
12
a
B
H
CRC-CCITT
56
39
22
5
55
38
19
49
37
17
45
36
16
41
X
31
X
15
X
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
3
2
4
8
L
L
L
L
H
H
L
H
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
56th
14
X
12
X
11
X
9
X
a
a
a
a
L
H
L
Order
a
a
1
H
L
X
a
48
23
15
36
21
13
35
8
a
a
a
a
a
a
5
9
1
L
H
L
H
L
L
L
L
L
H
H
H
X
X
X
X
X
X
X
48th
Order
2
a
a
X
X
X
1
32
X
11
X
23
X
2
X
21
a
a
a
a
6
L
H
L
H
H
L
L
32nd
a
A
H
1
Order
Block Diagram
TL/F/9535–5
3
TABLE II
Select Code
P
3
P
P
1
P
0
C
C
1
C
0
Polynomial
2
2
e
0
0
0
0
0
0
1
0
0
S
C
D
1
1
1
1
1
1
1
1
1
1
0
0
1
1
Ethernet
Polynomial
E
F
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Ethernet
Residue
7
1
1
1
1
1
1
1
1
1
1
0
0
0
0
CRC-16
B
CRC-CCITT
3
2
4
8
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
56th
Order
5
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
48th
Order
6
1
1
1
1
1
1
1
1
1
1
0
0
0
0
32nd
A
Order
Applications
In addition to polynomial selection there are four other ca-
pabilities provided for in the ’F402 ROM. The first is set or
clear selectability. The sixteen internal registers have the
capability to be either set or cleared when P is brought
LOW. This set or clear capability is done in four groups of 4
The ’F402 expandable CRC generator checker contains 6
th nd
popular CRC polynomials, 2-16 Order, 2-32 Order, 1-
th
th
48 Order and 1-56 Order. The application diagram
th
shows the ’F402 connected for a 56 Order polynomial.
Also shown are the input patterns for other polynomials.
When the ’F402 is used with a gated clock, disabling the
clock in a HIGH state will ensure no erroneous clocking
occurs when the clock is re-enabled. Preset and Master Re-
set are asynchronous inputs presetting the register to S or
(see Table II, P –P ). The second ROM capability (C ) is in
0
0
3
determining the polarity of the check word. As is the case
with the Ethernet polynomial the check word can be invert-
ed when it is appended to the data stream or as is the case
with the other polynomials, the residue is appended with no
th
clearing to 1s respectively (note Ethernet residue and 56
Order select code 8, LSB, are exceptions to this).
inversion. Thirdly, the ROM contains a bit (C ) which is used
1
to select the RFB input instead of the SEI input to be fed
into the LSB. This is used when the polynomial selected is
actually a residue (least significant) stored in the ROM
which indicates whether the selected location is a polynomi-
al or a residue. If the latter, then it inhibits the RFB input.
To generate a CRC, the pattern for the selected polynomial
is applied to the S inputs, the register is preset or cleared as
required, clock is enabled, CWG is set HIGH, data is applied
to D input, output data is on D/CW. When the last data bit
has been entered, CWG is set LOW and the register is
clocked for n bits (where n is the order of the polynomial).
The clock may now be stopped if desired (holding CWG
LOW and clocking the register will output zeros from D/CW
after the residue has been shifted out).
As mentioned previously, upon a successful data transmis-
sion, the CRC register has a zero residue. There is an ex-
ception to this, however, with respect to the Ethernet poly-
nomial. This polynomial, upon a successful data transmis-
sion, has a non-zero residue in the CRC register (C7 04 DD
To check a CRC, the pattern for the selected polynomial is
applied to the S inputs, the register is preset or cleared as
required, clock is enabled, CWG is set HIGH, the data
stream including the CRC is applied to D input. When the
last bit of the CRC has been entered, the ER output is
7B) . In order to provide a no-error indication, two ROM
16
locations have been preloaded with the residue so that by
selecting these locations and clocking the device one addi-
tional time, after the last check bit has been entered, will
result in zeroing the CRC register. In this manner a no-error
indication is achieved.
e
e
checked: HIGH error free data, LOW corrupt data. The
clock may now be stopped if desired.
th
With the present mix of polynomials, the largest is 56 or-
th
der requiring four devices while the smallest is 16 order
requiring just one device. In order to accommodate multi-
th
To implement polynomials of lower order than 56 , select
the number of packages required for the order of polynomial
and apply the pattern for the selected polynomial to the S
inputs (0000 on S inputs disables the package from the
feedback chain).
th
plexing between high order polynomials (X 16 order) and
lower order polynomials, a location of all zeros is provided.
This allows the user to choose a lower order polynomial
even if the system is configured for a higher order one.
4
Applications (Continued)
TL/F/9535–6
5
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
TRI-STATE Output
É
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Conditions
Min
Typ
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.4
2.4
2.7
I
I
I
2 mA (RO, D/CW)
5.7 mA (RO, D/CW)
5.7 mA (RO, D/CW)
CC
OH
OH
OH
74F 10% V
74F 5% V
V
V
CC
CC
e
e
e
e
V
OL
Output LOW
Voltage
54F 10% V
54F 10% V
74F 10% V
74F 10% V
0.4
I
I
I
I
4 mA (D/CW, RO)
8 mA (ER)
CC
CC
CC
CC
OL
OL
OL
OL
0.4
0.5
0.5
Min
16 mA (ER)
8 mA (D/CW, RO)
e
I
I
I
Input HIGH Current
54F
74F
20.0
5.0
V
V
V
2.7V
7.0V
IH
IN
mA
mA
mA
V
Max
Max
Max
0.0
e
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
BVI
IN
e
V
CC
Output HIGH
54F
74F
250
50
CEX
OUT
Leakage Current
e
All Other Pins Grounded
V
Input Leakage
Test
I
ID
1.9 mA
ID
74F
74F
4.75
e
IOD
I
Output Leakage
Circuit Current
V
150 mV
OD
3.75
mA
0.0
All Other Pins Grounded
b
e
0.5V
I
I
I
Input LOW Current
0.4
mA
mA
Max
Max
V
V
V
IL
IN
b
b
e
0V (D/CW, RO)
Output Short-Circuit Current
20
130
OS
OHC
OUT
OUT
e
Open Collector, Output
OFF Leakage Test
V
CC
(ER)
250
165
mA
Min
I
Power Supply Current
110
mA
Max
CC
6
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
T
, V
CC
e
Mil
T
, V
Com
e
50 pF
A
A CC
e a
Symbol
Parameter
V
Units
CC
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
30
45
30
30
MHz
ns
max
t
t
Propagation Delay
CP to D/CW
8.5
15.0
18.0
19.0
23.0
7.5
9.5
26.5
26.5
7.5
9.5
21.0
25.0
PLH
PHL
10.5
t
t
Propagation Delay
CP to RO
8.0
8.0
13.5
14.0
17.0
18.0
7.0
7.0
26.0
22.5
7.0
7.0
19.0
20.0
PLH
PHL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation Delay
CP to ER
15.5
8.5
26.0
14.5
33.0
18.5
14.0
7.5
38.5
23.5
14.0
7.5
35.0
20.5
PLH
PHL
t
t
Propagation Delay
P to D/CW
11.0
11.5
18.5
19.5
23.5
24.5
10.0
10.5
31.0
32.0
10.0
10.5
25.5
26.5
PLH
PHL
t
Propagation Delay
P to RO
PLH
9.5
16.0
17.0
20.5
21.5
8.5
9.0
31.5
26.0
8.5
9.0
22.5
23.5
t
Propagation Delay
P to ER
PLH
10.0
t
t
Propagation Delay
MR to D/CW
10.5
11.0
18.0
19.0
23.0
24.0
9.5
29.0
28.5
9.5
25.5
26.0
PLH
PHL
10.0
10.0
t
Propagation Delay
MR to RO
PHL
9.0
15.5
28.0
19.5
35.5
8.0
23.5
39.0
8.0
21.5
37.5
t
Propagation Delay
MR to ER
PLH
16.5
14.5
14.5
t
t
Propagation Delay
D to D/CW
6.0
7.5
10.5
12.0
13.5
16.0
5.0
6.5
19.5
20.0
5.0
6.5
15.0
18.0
PLH
PHL
t
t
Propagation Delay
CWG to D/CW
6.5
7.0
11.0
12.0
14.0
15.5
5.5
6.0
21.5
21.5
5.5
6.0
15.5
17.5
PLH
PHL
t
t
Propagation Delay
11.5
9.5
19.5
16.0
24.5
20.0
9.0
8.5
29.0
25.0
10.5
8.5
26.5
22.0
PLH
PHL
S
n
to D/CW
7
AC Operating Requirements
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
e a
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
SEI to CP
4.5
4.5
6.0
6.0
5.0
5.0
t (L)
s
ns
ns
ns
ns
t (H)
h
Hold Time, HIGH or LOW
SEI to CP
0
0
1.0
1.0
0
0
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
RFB to CP
11.0
11.0
14.0
14.0
12.5
12.5
t (L)
s
t (H)
h
Hold Time, HIGH or LOW
RFB to CP
0
0
0
0
0
0
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
13.5
13.0
16.0
15.5
15.0
14.5
t (L)
s
S to CP
1
t (H)
h
Hold Time, HIGH or LOW
S to CP
1
0
0
0
0
0
0
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
D to CP
9.0
9.0
11.5
11.5
10.0
10.0
t (L)
s
t (H)
h
Hold Time, HIGH or LOW
D to CP
0
0
0
0
0
0
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
CWG to CP
7.0
5.5
9.0
8.0
8.0
6.5
t (L)
s
ns
ns
t (H)
h
Hold Time, HIGH or LOW
CWG to CP
0
0
0
0
0
0
t (L)
h
t
t
(H)
(L)
Clock Pulse Width
HIGH or LOW
4.0
4.0
7.0
5.0
4.5
4.5
w
w
t
t
t
(H)
(L)
MR Pulse Width, HIGH
P Pulse Width, LOW
4.0
4.0
7.0
5.0
4.5
4.5
ns
ns
w
w
Recovery Time
MR to CP
rec
3.0
5.0
4.0
6.5
3.5
6.0
ns
t
Recovery Time
P to CP
rec
8
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 402
P
C
Temperature Range Family
e
e
54F Military
Special Variations
e
74F Commercial
QB
Military grade device with
environmental and burn-in
processing
Device Type
Temperature Range
e
Package Code
a
C
Commercial (0 C to 70 C)
§
§
e
e
e
e
P
D
F
L
Plastic DIP
Ceramic DIP
Flatpak
Leadless Chip Carrier (LCC)
e
b a
Military ( 55 C to 125 C)
M
§
§
9
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
10
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300 Wide) Molded Plastic Dual-In-Line Package (P)
×
NS Package Number N16E
11
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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National Semiconductor
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a
a
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(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
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49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
74F402PCQR
IC F/FAST SERIES, 1-BIT CRC GENERATOR CKT, PDIP16, PLASTIC, DIP-16, Arithmetic Circuit
NSC
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