74F823PCQR [NSC]
IC F/FAST SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24, Bus Driver/Transceiver;
| 型号： | 74F823PCQR |
| 厂家： | 
National Semiconductor |
| 描述： | IC F/FAST SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24, Bus Driver/Transceiver 触发器 |
| 文件： | 总8页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1994
54F/74F823
9-Bit D-Type Flip-Flop
General Description
The ’F823 is a 9-bit buffered register. It features Clock En-
able and Clear which are ideal for parity bus interfacing in
high performance microprogramming systems.
Features
Y
TRI-STATE outputs
É
Clock Enable and Clear
Y
Y
Direct replacement for AMD’s Am29823
The ’F823 is functionally and pin compatible with AMD’s
Am29823.
Package
Commercial
74F823SPC
Military
Package Description
Number
N24C
J24F
24-Lead (0.300 Wide) Molded Dual-In-Line
×
54F823SDM (Note 2)
24-Lead (0.300 Wide) Ceramic Dual-In-Line
×
74F823SC (Note 1)
M24B
W24C
E28A
24-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
54F823FM (Note 2)
54F823LM (Note 2)
24-Lead Cerpack
24-Lead Ceramic Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX.
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
SDMQB, FMQB and LMQB.
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9596–2
IEEE/IEC
TL/F/9596–4
TL/F/9596–3
TL/F/9596–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9596
RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 1.2 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
8
OE
CLR
CP
Output Enable Input
Clear
1.0/1.0
Clock Input
1.0/2.0
b
EN
Clock Enable
TRI-STATE Outputs
1.0/1.0
20 mA/ 0.6 mA
b
O –O
0
150/40 (33.3)
3 mA/24 mA (20 mA)
8
2
Functional Description
The ’F823 device consists of nine D-type edge-triggered
flip-flops. It has TRI-STATE true outputs and is organized in
broadside pinning. The buffered Clock (CP) and buffered
Output Enable (OE) are common to all flip-flops. The flip-
flops will store the state of their individual D inputs that meet
the setup and hold times requirements on the LOW-to-HIGH
CP transition. With the OE LOW the contents of the flip-
flops are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops. In addi-
tion to the Clock and Output Enable pins, the ’F823 has
Clear (CLR) and Clock Enable (EN) pins.
When the CLR is LOW and the OE is LOW, the outputs are
LOW. When CLR is HIGH, data can be entered into the flip-
flops. When EN is LOW, data on the inputs is transferred to
the outputs on the LOW to HIGH clock transition. When the
EN is HIGH, the outputs do not change state regardless of
the data or clock inputs transitions. This device is ideal for
parity bus interfacing in high performance systems.
Function Table
Internal
Inputs
EN
Output
O
Function
OE
CLR
CP
D
Q
H
H
H
L
H
H
H
H
L
L
L
H
H
X
X
L
L
L
L
L
L
H
L
X
X
X
X
X
X
H
H
L
NC
NC
NC
NC
H
Z
Z
Hold
Hold
Hold
Hold
X
Z
X
NC
Z
H
L
X
Clear
L
X
H
L
Clear
H
H
L
H
H
H
H
H
H
L
L
L
L
H
H
Z
Load
L
Z
Load
H
L
Data Available
Data Available
No Change in Data
No Change in Data
L
H
X
X
L
H
L
NC
NC
NC
NC
L
L
e
e
e
e
L
LOW Voltage Level
HIGH Voltage Level
Immaterial
H
X
Z
High Impedance
e
L
NC
LOW-to-HIGH Transition
No Change
e
Logic Diagram
TL/F/9596–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
b
b
a
65 C to 150 C
Storage Temperature
§
§
a
55 C to 125 C
Ambient Temperature under Bias
§
§
§
§
§
§
Recommended Operating
Conditions
b
b
a
55 C to 175 C
Junction Temperature under Bias
Plastic
a
55 C to 150 C
Free Air Ambient Temperature
Military
Commercial
V
Pin Potential to
CC
Ground Pin
b
a
55 C to 125 C
§
0 C to 70 C
§
b
a
0.5V to 7.0V
a
§
§
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
Supply Voltage
Military
Commercial
b
a
30 mA to 5.0 mA
a
a
a
4.5V to 5.5V
a
4.5V to 5.5V
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
DC Electrical Characteristics
54F/74F
Symbol
Parameter
Units
V
CC
Conditions
Min
Typ
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
e b
e b
e b
54F 10% V
2.5
2.4
2.5
2.4
2.7
2.7
I
I
I
I
I
I
1 mA
3 mA
1 mA
3 mA
1 mA
3 mA
CC
CC
CC
CC
OH
OH
OH
OH
OH
OH
54F 10% V
74F 10% V
74F 10% V
Output HIGH
Voltage
V
74F 5% V
74F 5% V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.5
I
I
20 mA
24 mA
OL
CC
OL
OL
V
Min
Max
Max
Max
0.0
0.5
CC
e
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
2.7V
IH
IN
mA
mA
mA
V
e
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
7.0V
BVI
IN
e
V
CC
Output HIGH
54F
74F
250
50
CEX
OUT
Leakage Current
e
All Other Pins Grounded
V
Input Leakage
Test
I
1.9 mA
ID
OD
IL
ID
74F
74F
4.75
e
All Other Pins Grounded
I
I
Output Leakage
Circuit Current
V
150 mV
IOD
3.75
mA
0.0
b
b
e
e
Input LOW
Current
0.6
1.2
mA
mA
Max
Max
V
V
0.5V (OE, CLR, EN)
0.5V (CP)
IN
IN
e
I
I
I
I
I
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Buss Drainage Test
50
mA
mA
mA
mA
mA
Max
Max
Max
0.0V
Max
V
V
V
V
V
2.7V
0.5V
0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
b
e
e
e
50
b
b
60
150
500
100
5.25V
ZZ
e
Power Supply Current
75
HIGH Z
CCZ
O
4
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
Propagation Delay
100
160
60
70
MHz
ns
max
t
t
2.0
2.0
5.6
5.2
9.5
9.5
2.0
2.0
10.5
10.5
2.0
2.0
10.5
10.5
PLH
PHL
CP to O
n
t
Propagation Delay
CLR to O
PHL
4.0
7.1
12.0
4.0
13.0
4.0
13.0
ns
ns
n
t
t
Output Enable Time
OE to O
2.0
2.0
5.8
5.5
10.5
10.5
2.0
2.0
13.0
13.0
2.0
2.0
11.5
11.5
PZH
PZL
n
t
t
Output Disable Time
OE to O
1.5
1.5
2.9
2.7
7.0
7.0
1.0
1.0
7.5
7.5
1.5
1.5
7.5
7.5
PHZ
PLZ
n
AC Operating Requirements
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
e a
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
2.5
2.5
4.0
4.0
3.0
3.0
t (L)
s
D to CP
n
ns
t (H)
h
Hold Time, HIGH or LOW
D to CP
n
2.5
2.5
2.5
2.5
2.5
2.5
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
EN to CP
4.5
2.5
5.0
3.0
5.0
3.0
t (L)
s
ns
ns
t (H)
h
Hold Time, HIGH or LOW
EN to CP
2.0
0
3.0
1.0
2.0
0
t (L)
h
t
t
(H)
(L)
CP Pulse Width
HIGH or LOW
5.0
5.0
6.0
6.0
6.0
6.0
w
w
t
t
(L)
CLR Pulse Width, LOW
CLR Recovery Time
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
w
rec
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 823
S
C
X
Temperature Range Family
e
e
54F Military
Special Variations
e
74F Commercial
QB
Military grade device with
environmental and burn-in
processing
Device Type
Temperature Range
Package Code
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
e
e
e
e
e
SP
SD
F
L
S
Slim Plastic DIP
Slim Ceramic DIP
Flatpak
Leadless Chip Carrier (LCC)
Small Outline (SOIC)
b a
Military ( 55 C to 125 C)
§
§
5
Physical Dimensions inches (millimeters)
28-Lead Ceramic Leadless Chip Carrier, Type C (L)
NS Package Number E28A
24-Lead (0.300 Wide) Ceramic Dual-In-Line Package (SD)
×
NS Package Number J24F
6
Physical Dimensions inches (millimeters) (Continued)
24-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M24B
24-Lead (0.300 Wide) Molded Dual-In-Line Package (SP)
×
NS Package Number N24C
7
Physical Dimensions inches (millimeters) (Continued)
24-Lead Ceramic Flatpak (F)
NS Package Number W24C
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