CLC409AJP [NSC]
Very Wideband, Low Distortion Monolithic Op Amp; 甚宽带，低失真单片运算放大器
| 型号： | CLC409AJP |
| 厂家： | 
National Semiconductor |
| 描述： | Very Wideband, Low Distortion Monolithic Op Amp |
| 文件： | 总10页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2002
CLC409
Very Wideband, Low Distortion Monolithic Op Amp
General Description
Features
n 350MHz small signal bandwidth
n -65/−72dBc 2nd/3rd harmonics (20MHz)
n Low noise
The CLC409 is a very wideband, DC coupled monolithic
operational amplifier designed specifically for wide dynamic
range systems requiring exceptional signal fidelity. Benefit-
ing from National’s current feedback architecture, the
CLC409 offers a gain range of 1 to 10 while providing
stable, oscillation free operation without external compensa-
tion, even at unity gain.
n 8ns settling to 0.1%
n 1200V/µs slew rate
n 13.5mA supply current ( 5V)
n 60mA output current
With its 350MHz small signal bandwidth (VOUT = 2VPP),
10-bit distortion levels through 20MHz (RL = 100Ω), 8-bit
Applications
distortion levels through 60MHz, 2.2nV/
input referred
n Flash A/D driver
noise and 13.5mA supply current, the CLC409 is the ideal
driver or buffer for high speed flash A/D and D/A converters.
n D/A transimpedance buffer
n Wide dynamic range IF amp
n Radar/communication receivers
n DDS post-amps
n Wideband inverting summer
n Line driver
Wide dynamic range systems such as radar and communi-
cation receivers requiring a wideband amplifier offering ex-
ceptional signal purity will find the CLC409’s low input re-
ferred noise and low harmonic and intermodulation distortion
make it an attractive high speed solution.
Constructed using an advanced, complimentary bipolar pro-
cess and National’s proven current feedback architecture,
the CLC409 is available in several versions to meet a variety
of requirements.
Harmonic Distortion vs. Load and Frequency
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-92034
Space level versions also available.
For more information, visit http://www.national.com/mil
01274804
Connection Diagrams
01274815
01274814
Pinout
Pinout
DIP & SOIC
SOT23-5
© 2002 National Semiconductor Corporation
DS012748
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature Range
Storage Temperature Range
Lead Solder Duration (+300˚C)
ESD rating (human body model)
−40˚C to +85˚C
−65˚C to +150˚C
10 sec
1000V
Supply Voltage (VCC
IOUT
)
7V
Operating Ratings
Thermal Resistance
Output is short circuit protected to
ground, but maximum reliability will
be maintained if IOUT does not
exceed...
Package
MDIP
(θJC
)
(θJA)
60mA
VCC
95˚C/W
75˚C/W
115˚C/W
115˚C/W
160˚C/W
185˚C/W
Common Mode Input Voltage
Differential Input Voltage
Junction Temperature
SOIC
10V
SOT23-5
+150˚C
Electrical Characteristics
AV = +2, VCC
=
5V, RL = 100Ω, Rf = 250Ω; unless specified
Symbol
Parameter
Conditions
Typ
Max/Min
(Note 2)
+25˚C
Units
Ambient Temperature
Frequency Domain Performance
CLC409AJ
+25˚C
−40˚C
+85˚C
<
>
>
>
>
>
>
80
SSBW
LSBW
-3dB Bandwidth
VOUT 2VPP
350
110
250
250
200
MHz
MHz
<
VOUT 5VPP
90
90
<
Gain Flatness
Peaking
VOUT 0.5VPP
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
GFPL
GFPH
GFR1
GFR2
LPD
DC to 75MHz
0
0.4
0.8
0.4
0.8
0.4
0.8
dB
dB
dB
dB
deg
%
>
Peaking
75MHz
0
Rolloff
DC to 125MHz
0.2
1.0
0.3
0.03
0.03
1.0
1.0
1.0
@
Rolloff
200MHz
2.0
2.2
3.0
Linear Phase Deviation
Differential Gain
DC to 100MHz
0.8
0.8
1.0
<
<
<
<
<
<
<
<
<
<
<
<
DG1
RL =150Ω, 3.58MHz
RL =150Ω, 4.43MHz
0.07
0.07
0.02
0.02
0.06
0.06
0.02
0.02
0.06
0.06
0.02
0.02
DG2
%
DP1
Differential Phase
RL = 150Ω, 3.58MHz
RL =150Ω, 4.43MHz
0.01
0.01
deg
deg
DP2
Time Domain Response
<
<
<
<
<
<
<
<
<
<
<
<
TRS
TRL
TS
Rise and Fall Time
2V Step
5V Step
2V Step
2V Step
1.3
3.5
8
1.6
4.2
1.6
4.2
1.6
4.6
ns
ns
Settling Time to 0.1%
Overshoot
12
15
12
18
12
18
ns
OS
5
%
>
>
>
1000
SR
Slew Rate
1200
1000
1000
V/µs
Distortion And Noise Response
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
HD2L
HD2
2nd Harmonic Distortion
3rd Harmonic Distortion
2VPP, 5MHz
2VPP, 20MHz
2VPP, 60MHz
2VPP, 5MHz
2VPP, 20MHz
2VPP, 60MHz
−86
−65
−49
−84
−72
−59
−78
−56
−41
−76
−65
−52
−81
−56
−44
−76
−65
−52
−81
−56
−44
−76
−65
−52
dBc
dBc
dBc
dBc
dBc
dBc
HD2H
HD3L
HD3
HD3H
Equivalent Input Noise
Non-Inverting Voltage
Inverting Current
>
>
>
>
<
<
<
<
<
<
<
3.1
<
20
<
4.5
<
−154
VN
1MHz
1MHz
1MHz
1MHz
2.2
14.3
3.2
2.8
2.8
nV/
ICN
NCN
SNF
INV
18
18
pA/
Non-Inverting Current
Total Noise Floor
4.0
4.0
pA/
<
<
−157
38
−155
−155
dBm1Hz
µV
<
<
<
52
Total Integrated Noise
1MHz to 150MHz
47
47
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2
Electrical Characteristics (Continued)
AV = +2, VCC
=
5V, RL = 100Ω, Rf = 250Ω; unless specified
Parameter Conditions
Symbol
Typ
Max/Min
Units
(Note 2)
Static, DC Performance
<
<
<
<
<
9.5
VIO
Input Offset Voltage (Note 3)
0.5
25
8.5
4.5
-
mV
µV/˚C
µA
<
<
DVIO
IBN
Average Temperature Coefficient
Input Bias Current (Note 3)
50
44
50
22
<
Non Inverting
10
22
-
<
<
DIBN
IBI
Average Temperature Coefficient
Input Bias Current (Note 3)
100
10
275
125
nA/˚C
µA
<
<
<
Inverting
36
20
-
30
<
<
DIBI
PSRR
CMRR
ICC
Average Temperature Coefficient
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Supply Current (Note 3)
100
50
200
100
nA/˚C
dB
>
>
>
>
>
>
45
45
45
45
45
45
50
dB
<
<
<
14.2
No Load
13.5
14.2
14.2
mA
Miscellaneous Performance
>
<
>
<
>
1000
<
2
<
0.2
>
3.2
2.0
50
RIN
CIN
RO
Non-Inverting Input Resistance
1000
1
250
500
kΩ
pF
Ω
<
<
Non-Inverting Input Capacitance
Output Impedance
2
2
DC
0.1
3.5
2.2
60
0.3
0.2
>
>
VO
Output Voltage Range
Common Mode Input Range
Output Current
RL = 100Ω
3.0
1.5
36
3.2
2.0
50
V
CMIR
IO
V
mA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: AJ-level: spec. is 100% tested at +25˚C.
Ordering Information
Package
Temperature Range
Industrial
Part Number
Package
Marking
NSC
Drawing
N08E
8-pin plastic DIP
8-pin plastic SOIC
5-pin SOT
−40˚C to +85˚C
−40˚C to +85˚C
−40˚C to +85˚C
CLC409AJP
CLC409AJE
CLC409AJM5
CLC409AJP
CLC409AJE
A18
M08A
MA05A
3
www.national.com
Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC
=
5V, RL = 100Ω, Rf = 500Ω;
Unless Specified).
Non-Inverting Frequency Response
Inverting Frequency Response
01274801
01274802
Frequency Response for Various RLS
Small Signal Pulse Response
01274803
01274816
Short-Term Settling Response
Long-Term Settling Time
01274817
01274818
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4
Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC
=
5V, RL = 100Ω, Rf = 500Ω;
Unless Specified). (Continued)
Harmonic Distortion vs. Load and Frequency
2-Tone, 3rd Order Spurious Levels
01274805
01274804
Settling Time vs. Capacitive Load
2nd Harmonic Distortion vs. POUT
01274807
01274806
3rd Harmonic Distortion vs. POUT
Typical D.C. Errors vs. Temperature
01274808
01274819
5
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Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC
=
5V, RL = 100Ω, Rf = 500Ω;
Unless Specified). (Continued)
Equivalent Input Noise
PSRR, CMRR, and Closed Loop RO
01274809
01274810
Open-Loop Transimpedance Gain, Z(s)
01274811
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6
Application Division
01274812
FIGURE 1. Recommended Non-Inverting Gain Circuit
01274813
FIGURE 2. Recommended Inverting Gain Circuit
Harmonic Distortion
Feedback Resistor
The CLC409 achieves its excellent pulse and distortion per-
formance by using the current feedback topology pioneered
by Comlinear Corporation. The loop gain for a current feed-
back op amp, and hence the frequency response, is pre-
dominantly set by the feedback resistor value. The CLC409
is optimized for use with a 250Ω feedback resistor. Using
lower values can lead to excessive ringing in the pulse
response while a higher value will limit the bandwidth. Appli-
cation Note OA-13 discusses this in detail along with the
occasions where a different Rf might be advantageous.
The CLC409 has been optimized for exceptionally low har-
monic distortion while driving very demanding resistive or
capacitive loads. Generally, when used as the input amplifier
to very high speed flash ADCs, the distortions introduced by
the converter will dominate over the low CLC409 distortions
shown on the plots on the previous page. The 0.01µF ca-
pacitor (Css) shown across the supplies in Figure 1 and
Figure 2 is critical to achieving the lowest 2nd harmonic
distortion.
The 2-tone, 3rd order spurious plot shows a relatively con-
stant difference between the test power level and the spuri-
ous level with that difference depending on frequency. The
7
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through from the convert signal. Also, Cin is oftentimes a
voltage dependent capacitance. This input impedance
non-linearity will induce distortion terms that will increase as
Rs is increased. Only slight adjustments up or down from the
recommended Rs value should therefore be attempted in
optimizing system performance.
Application Division (Continued)
CLC409 does not show an intercept type performance.
(where the relative spurious levels change at a 2X rate vs.
the test tone powers), due to an internal full power bandwidth
enhancement circuit that boosts the performance as the
output swing increases while dissipating negligible quiescent
power under low output power conditions. This feature en-
hances the distortion performance and full power bandwidth
to match that of much higher quiescent supply current parts.
DC Accuracy and Noise
The CLC409 offers an improved offset voltage over the pin
compatible CLC400 low gain amplifier. The offset adjustment
available on the CLC400 was therefore not included in this
part. The Output Offset equation below shows the output
offset computation equation for the non-inverting configura-
tion with an example using the typical bias current and offset
specifications for AV = +2.
Output Offset
VO=( IbnRin Vio)(1+Rf/Rg) IbiRf
Example Computation for AV=+2, Rf=250Ω, Rin=25Ω:
VO=( 10µA (25Ω) 0.5mV)2 10µA (250Ω)= 3.25mV
This low output offset voltage is a marked improvement over
earlier very high speed amplifiers. Further improvement in
the output offset voltage and drift is possible using the com-
posite amplifiers described in Application Note OA-7.
The two input bias currents are physically unrelated in both
magnitude and polarity for the current feedback topology. It
is not possible, therefore, to cancel their effects by matching
the source impedance for the two inputs (as is commonly
done for matched input bias current devices).
01274820
FIGURE 3. Input Amplifier to ADC
Figure 3 shows a typical application using the CLC409 to
drive an ADC. The series resistor, Rs, between the amplifier
output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the
output pin, can quickly lead to unacceptable levels of ringing
in the pulse response. The plot of Rs and settling time vs. CL
on the previous page is an excellent starting point for setting
Rs. The value derived in that plot minimizes the step settling
time into a fixed discrete capacitive load. Several additional
constraints should be considered, however, in driving the
capacitive input or an ADC.
The total output noise is computed in a similar fashion to
output offset voltage. Using the input noise voltage and two
input noise currents, the output noise is developed through
the same gain equations for each term but combined as the
square root of the sum of squared contributing elements.
See Application Note OA-12 for a full discussion of noise
calculations for current feedback amplifiers.
Printed Circuit Layout
As with any high speed component, a careful attention to the
board layout is necessary for optimum performance. Evalu-
ation PC boards (CLC730013-DIP, CLC730027-SOIC, and
CLC730068-SOT) for the CLC409 are available. This addi-
tional supply bypassing capacitor, Css, can easily be added
to the board if desired. Further layout suggestions can be
found in Application Note OA-15.
There is an option to increase Rs, bandlimiting at the ADC
input for either noise or Nyquist bandlimiting purposes. In-
creasing Rs too much, however, can induce an unacceptably
large input glitch due to switching transients coupling
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8
Physical Dimensions inches (millimeters)
unless otherwise noted
8-Pin MDIP
NS Package Number N08E
8-Pin SOIC
NS Package Number M08A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
5-Pin SOT23
NS Package Number MA05A
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