CLC5801IM [NSC]
High Speed Low Noise Voltage Feedback Amplifier; 高速低噪声电压反馈放大器
| 型号： | CLC5801IM |
| 厂家： | 
National Semiconductor |
| 描述： | High Speed Low Noise Voltage Feedback Amplifier |
| 文件： | 总14页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2000
CLC5801
High Speed Low Noise Voltage Feedback Amplifier
General Description
The CLC5801 is a low-cost, wideband voltage feedback
amplifier excellent for low noise applications. It combines
a wide bandwidth of 420MHz with very low noise
Features
±
(TA = 25˚C, VS
=
5V, RL = 100Ω Typical unless specified).
n 420MHz, −3dB bandwidth (AV = 10)
n 2nV/
n 1.8pA/
input voltage noise
input current noise
(2nV/
, 1.8pA/
) and low DC errors (100µV VOS)
making it an excellent precision high speed op amp offering
closed-loop gains of ≥ 10.
n 100µV input offset voltage
n 300V/µs slew rate
The CLC5801 employs a traditional voltage-feedback topol-
ogy and provides all the benefits of balanced inputs, such as
low offsets and drifts, as well as 96dB open-loop gain, 95dB
CMRR and a 90dB PSRR. Providing a wide 420MHz band-
width at a gain of AV = 10, a fast 300V/µs slew rate, the
CLC5801 is well suited for wide band active filters and low
noise loop filters for PLLs.
n 16mA supply current
n 18ns settling time
Applications
n Ultrasound preamplifier
n CD-ROM preamplifer
The low noise, wide gain-bandwidth, high slew rate and low
DC errors enable applications such as medical diagnostic ul-
trasound, magnetic tape and disk storage, communications
and optoelectronics that require maximum high-frequency
signal-to-noise ratios. Low noise and offset make the
CLC5801 and ideal preamplifier for CD-ROMs and receiv-
ers.
n Photo-diode transimpedance amplifier
n Low-noise loop filters for PLLs
n High-performance receivers
n ADC preamplifier
Equivalent Input Noise
The CLC5801 consumes 16mA of supply current and can be
used in either dual 5V systems or single supply applications.
It can easily drive a 100Ω load to within 1.6V of either rail.
The CLC5801 is available in both SOIC-8 and the tiny
SOT23-5.
DS101307-1
Connection Diagrams
5-Pin SOT23-5
8-Pin SOIC
DS101307-2
DS101307-3
Top View
Top View
© 2000 National Semiconductor Corporation
DS101307
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Ordering Information
Package
Part Number
Packaging
Marking
CLC5801IM
CLC5801IM
A50A
Transport Media
NSC
Drawing
M08A
8-pin SOIC
CLC5801IM
CLC5801IMX
CLC5801IM5
CLC5801IM5X
Rails
2.5k Tape and Reel
1k Units Tape and Reel
3k Units Tape and Reel
5-pin SOT23-5
MF05A
A50A
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2
Absolute Maximum Ratings (Note 1)
Operating Rating(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Thermal Resistance (θJC
SOIC
)
65˚C/W
SOT23-5
115˚C/W
±
VCC
7V
Thermal Resistance (θJA
SOIC
)
IOUT Short Circuit protected to
ground. Maximum reliability is
obtained if IOUT does not exceed:
145˚C/W
185˚C/W
125mA
SOT23-5
±
Common-Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering 10 sec)
ESD (human body model)
VCC
Temperature Range
−40˚C to +85˚C
+125˚C
−65˚C to +150˚C
+300˚C
±
±
10 to 1000V/V
Recommended Gain Range
1000V
Electrical Characteristics
±
5V, Rg = 26.1Ω, Rf= 499Ω, RL= 100Ω; unless specified).
(TA= 25˚C, VCC
=
Symbol
Parameter
Conditions
Typ
Min/Max Ratings
Units
(Note 2)
+25˚C −40˚C +25˚C +85˚C
Frequency Domain Response
<
GBW
Gain Bandwidth Product
−3dB Bandwidth (AV = +10)
−3dB Bandwidth (AV = +20)
−3dB Bandwidth
VO 0.4VPP
1.8
420
90
1.3
GHz
MHz
<
VO 0.4VPP
SSBW
<
VO 0.4VPP
70
30
<
LSBW
GFP
GFR
LPD
VO 5.0VPP
35
<
<
<
Gain Flatness Peaking
Gain Flatness Rolloff
DC to 30MHz, VO 0.4VPP
0.4
0.2
0.8
0.5
0.5
1.5
dB
dB
DC to 30MHz, VO 0.4VPP
Linear Phase Deviation
DC to 30MHz, VO 0.4VPP
Deg
Time Domain Response
TRS
TSS
OS
Rise and Fall Time
0.4V step
2V step
4.0
18
5
4.7
30
ns
ns
Settling Time to 0.2%
Overshoot
0.4V step
2V step
10
%
SR
Slew Rate
300
250
V/µs
Distortion And Noise Response
HD2
HD3
IMD
VN
2nd Harmonic Distortion
1VPP,10MHz
1VPP,10MHz
10MHz
−53
−78
34
−48
−65
dBc
dBc
dBm
nV/
3rd Harmonic Distortion
3rd Order Intermod. Intercept
Equivalent Input Noise Voltage
1MHz to 100MHz
2.0
2.7
2.5
ICN
Equivalent Input Noise Current
1MHz to 100MHz
1.8
pA/
Static, DC Performance
AOL
VIO
Open-Loop Gain
DC
96
77
1000
8
86
86
1000
4
dB
µV
±
±
±
±
Input Offset Voltage (Note 3)
Offset Voltage Average Drift
Input Bias Current (Note 3)
Bias Current Average Drift
Input Offset Current
100
800
–
±
DVIO
IB
2
µV/˚C
µA
12
40
20
–
20
DIB
−100
−250
3.4
−120
2.0
µA/˚C
µA
±
IIO
0.2
2.0
–
±
±
±
DIIO
PSRR
CMRR
ICC
Offset Current Average Drift
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Supply Current (Note 3)
3
50
25
nA/˚C
dB
DC
DC
90
95
16
80
85
88
17
84
84
18
86
17
dB
∞
RL
=
mA
3
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Electrical Characteristics (Continued)
±
5V, Rg = 26.1Ω, Rf= 499Ω, RL= 100Ω; unless specified).
(TA= 25˚C, VCC
=
Symbol Parameter
Conditions
Typ
Min/Max Ratings
Units
(Note 2)
+25˚C −40˚C +25˚C +85˚C
Miscellaneous Performance
RINC
RIND
CINC
CIND
ROUT
VO
Input Resistance
Common-Mode
Differential-Mode
Common-Mode
Differential-Mode
Closed Loop
∞
2
6
0.6
1
1.6
3
1.6
3
MΩ
kΩ
pF
pF
mΩ
V
Input Capacitance
1.5
1.9
5
3
3
3
3
3
3
Output Resistance
50
3.5
10
3.7
10
3.7
±
±
±
±
Output Voltage Range
RL
=
3.8
±
±
±
±
VOL
RL = 100Ω
Common-Mode
Source
3.4
3.8
2.8
3.4
3.2
3.5
3.2
3.5
V
±
±
±
±
CMIR
IOP
Input Voltage Range
Output Current
V
80
80
60
40
65
55
65
55
mA
ION
Sink
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Operating Ratings indicate conditions for which
the device is intended to be functional, but specific performance is not guaranteed,
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: 100% tested at +25˚C.
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4
±
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
Typical Performance Characteristics (TA = 25˚C, VCC
=
unless otherwise specified).
Non-Inverting Frequency Response
Inverting Frequency Response
DS101307-4
DS101307-5
Frequency Response for Various RLs
Open Loop Gain and Phase vs. RL
DS101307-6
DS101307-7
Open Loop Gain and Phase vs. Temp
Gain Flatness & Linear Phase Deviation
DS101307-9
DS101307-8
5
www.national.com
±
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
Typical Performance Characteristics (TA = 25˚C, VCC
=
unless otherwise specified).. (Continued)
Equivalent Input Noise
Maximum Output Swing vs. Frequency
DS101307-1
DS101307-11
Closed-Loop Output Impedance
CMRR vs. Common Mode Input Voltage
DS101307-13
DS101307-12
Common Mode Input Impedance
Differential Input Impedance
DS101307-14
DS101307-15
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6
±
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
Typical Performance Characteristics (TA = 25˚C, VCC
=
unless otherwise specified).. (Continued)
Pulse Response (VO = 1VPP
)
Large Signal Pulse Response (VO = 2VPP)
DS101307-16
DS101307-17
Settling Time vs. Gain
Short Term Settling Time
DS101307-18
DS101307-19
Long Term Settling Time
Settling Time vs. CL and RS
DS101307-20
DS101307-21
7
www.national.com
±
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
Typical Performance Characteristics (TA = 25˚C, VCC
=
unless otherwise specified).. (Continued)
2nd & 3rd Harmonic Distortion (VO = 1VPP
)
Distortion vs. Gain (VO = 1VPP, fo = 3MHz)
DS101307-23
DS101307-25
DS101307-27
DS101307-22
2-Tone, 3rd Order Intermod. Intercept.
Output Voltage vs. Load
DS101307-24
CMRR and PSRR
Typical DC Errors vs. Temperature
DS101307-26
www.national.com
8
Application Information
Introduction
The CLC5801 is a very wide gain-bandwidth, low noise volt-
age feedback operational amplifier which enables applica-
tions areas such as medical diagnostic ultrasound, magnetic
tape & disk storage and fiber-optics to achieve maximum
high-frequency signal-to-noise ratios. The following discus-
sion will describe the proper selection of external compo-
nents in order to achieve optimum device performance.
DS101307-29
FIGURE 2. Inverting Amplifier Configuration
Total Input Noise vs. Source Resistance
In order to determine maximum signal-to-noise ratios from
the CLC5801, an understanding of the interaction between
the amplifier’s intrinsic noise sources and the noise arising
from its external resistors is necessary.
DS101307-28
Figure 3 describes the noise model for the non-inverting am-
plifier configuration showing all noise sources. In addition to
the intrinsic input voltage noise (en) and current noise
FIGURE 1. Non-Inverting Amplifier Configuration
Bias Current Cancellation
+
(in = in = in−) sources, there also exists thermal voltage
In order to cancel the bias current errors of the non-inverting
configuration, the parallel combination of the gain-setting
(Rg) and feedback (Rf) resistors should equal the equivalent
source resistance (Rseq) as defined in Figure 1. Combining
this constraint with the non-inverting gain equation also seen
in Figure 1, allows both Rf and Rg to be determined explicitly
noise (
) associated with each of the external re-
sistors. Equation (1) provides the general form for total
equivalent input voltage noise density (eni). Equation (2) is a
simplification of Equation (1) that assumes Rf || Rg = Rseq for
bias current cancellation. Figure 4 illustrates the equivalent
noise model using this assumption. Figure 5 is a plot of eni
against equivalent source resistance (Rseq) with all of the
contributing noise sources of Equation (2) shown. This plot
gives the expected eni for a given Rseq which assumes Rf ||
Rg = Rseq for bias current cancellation. The total equivalent
output voltage noise (eno) is eni x AV.
from the following equations: Rf = AVRseq and Rg
=
Rf/(AV−1). When driven from a 0Ω source, such as that from
the output of an op amp, the non-inverting input of the
CLC5801 should be isolated with at least a 25Ω series resis-
tor.
As seen in Figure 2, bias current cancellation is accom-
plished for the inverting configuration by placing a resistor
(Rb) on the non-inverting input equal in value to the resis-
tance seen by the inverting input (Rf || (Rg + Rs)). Rb is
recommended to be no less than 25Ω for best CLC5801 per-
formance. The additional noise contribution of Rb can be
minimized through the use of a shunt capacitor.
DS101307-30
FIGURE 3. Non-Inverting Amplifier Noise Model
(1)
9
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Application Information (Continued)
DS101307-32
FIGURE 4. Noise Model with Rf || Rg = Rseq
DS101307-35
FIGURE 6. External Lag Compensation
(2)
Single-Supply Operation
As seen in Figure 5, eni is dominated by the intrinsic voltage
noise (en) of the amplifier for equivalent source resistance
below 121Ω. Between 121Ω and 5.11kΩ, eni is dominated by
The CLC5801 can be operated with single power supply as
shown in Figure 7. Both the input and output are capacitively
coupled to set the DC operating point.
the thermal noise (
Above 5.11kΩ, eni is dominated by the amplifier’s current
noise ( Rseq). The point at which the CLC5801’s volt-
age noise and current noise contribute equally occurs for
Rseq = 786Ω ( ). As an example, configured with a
) of the external resistors.
gain of +20V/V giving a −3dB of 90MHz and driven from an
Rseq = 25Ω, the CLC5801 produces a total equivalent input
noise voltage (
) of 26µVrms.
DS101307-36
FIGURE 7. Single Supply Operation
Low Noise Transimpedance Amplifier
Figure 8 shows a transimpedance amplifier used to amplify
the small signal from a Photodiode. Using a low noise ampli-
fier such as the CLC5801 and proper design, ensures that
the amplifier noise contribution is minimal. Here Rb can be
used to compensate for the input bias current of the
CLC5801. Generally, Rb is selected to be equal to Rf to can-
cel the effect of Ib flowing in each of the Op Amp input
terminals.
DS101307-34
FIGURE 5. Voltage Noise Density vs. Source
Resistance
If bias current cancellation is not a requirement, then Rf || Rg
does not need to equal Rseq. In this case, according to Equa-
tion (1), Rf || Rg should be as low as possible in order to mini-
mize noise. Results similar to Equation (1) are obtained for
the inverting configuration of Figure 2 if Rseq is replaced by
Rb and Rg is replaced by Rg + Rs. With these substitutions,
Equation (1) will yield eni referred to the non-inverting input.
Referring eni to the inverting input is easily accomplished by
multiplying eni by the ratio of non-inverting to inverting gains.
Inverting Gains Less Than 10V/V
The lag compensation of Figure 6 will achieve stability for
lower gains. Placing the network between the two input ter-
minals does not affect the closed-loop nor noise gain, but is
best used for the inverting configuration because of its affect
on the non-inverting input impedance.
DS101307-37
FIGURE 8. Transimpedance Amplifier Configuration
Figure 9 shows the equivalent noise analysis schematic for
this circuit. The complete expression for the amplifier stage
output rms noise is shown in Equation (3).
(3)
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10
High-Gain Sallen-Key Active Filters
Application Information (Continued)
The CLC5801 is well suited for high-gain Sallen-key type of
active filters. Figure 11 shows the 2nd order Sallen-Key low
pass filter topology. Using component predistortion methods
as discussed in OA-21 enables the proper selection of com-
ponents for these high-frequency filters.
DS101307-39
FIGURE 9. Transimpedance Amplifier Noise Model
Low Noise Integrator
DS101307-41
The Circuit in Figure 10 implements a deBoo integrator. Inte-
gration linearity is maintained through positive feedback. The
CLC5801’s low input offset voltage and matched inputs al-
lowing bias current cancellation provide for very precise inte-
gration. Stability is maintained through the constraint on the
circuit elements.
FIGURE 11. Sallen-Key Active Filter Topology
Low Noise Magnetic Media Equalizer
The circuit in Figure 12 implements a high-performance
low-noise equalizer for such applications as magnetic tape
channels. The circuit combines an integrator with a band-
pass filter to produce the low-noise equalization.
The circuit’s simulated frequency response is illustrated in
Figure 13.
DS101307-40
FIGURE 10. Low Noise Integrator
DS101307-42
FIGURE 12. Low Noise Magnetic Media Equalizer
11
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Low-Noise Phase-Locked Loop Filter
Application Information (Continued)
The CLC5801 is extremely useful as a Phase-Locked Loop
filter in such applications as frequency synthesizers and data
synchronizers. The circuit of Figure 14 implements one pos-
sible PLL filter with the CLC5801.
DS101307-44
FIGURE 14. Phase-Locked Loop Filter
DS101307-43
Printed Circuit Board Layout
FIGURE 13. Equalizer Frequency Response
Generally, a good high-frequency layout will keep power
supply and ground traces away from the inverting input and
output pins. Parasitic capacitances on these nodes to
ground will cause frequency response peaking and possible
circuit oscillation, see OA-15 for more information. National
includes an evaluation board with samples as a guide for
high frequency lay-out and as an aid in device testing and
characterization.
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12
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
Order Numbers CLC5801IM and CLC5801IMX
NS Package Number MA08A
13
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
5-Pin SOT23-5
Order Numbers CLC5801IM5 and CLC5801IM5X
NS Package Number MF05A
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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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