CLC949AJQ [NSC]

Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter; 非常低功耗， 12位， 20MSPS单片A / D Convertter


型号：	CLC949AJQ
厂家：	National Semiconductor
描述：	Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter 非常低功耗， 12位， 20MSPS单片A / D Convertter
文件：	总12页 (文件大小：740K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

August 1996

Comlinear CLC949

Very Low-Power, 12-Bit,

20MSPS Monolithic A/D Convertter

General Description

Features

The Comlinear CLC949 is a 12-bit analog-to-digital converter sub-

system including 12-bit quantizer, sample-and-hold amplifier, and

internal reference. The CLC949 has been optimized for low power

operation with high dynamic range. The CLC949 has a unique

feature which allows the user to adjust internal bias levels in the

converter which results in a trade-off between power dissipation

and maximum conversion rate. With bias set for 220mW power

dissipation the converter operates at 20MSPS. Under these

conditions, dynamic performance with a 9.9MHz analog input is

typically 68dB SNR and 72dBc SFDR. When bias is set for only

65mW power dissipation the converter maintains excellent perfor-

mance at 5MSPS. With a 2.4MHz analog input signal the SNR is

70dB and SFDR is 78dBc. This excellent dynamic performance in

the frequency domain without high power requirements make the

part a strong performer for communications and radar applications.

The low input noise of the CLC949, its 0.5LSB differential linearity

error specification, fast settling, and low power dissipation also

lead to excellent performance in imaging systems. All parts are

thoroughly tested to insure that guaranteed specifications are met.

■

Very low/programmable power

0.07W @ 5MSPS

0.22W @ 20MSPS

0.40W @ 30MSPS

■

Single supply operation (+5V)

■

0.5 LSB differential linearity error

Wide dynamic range

■

72dBc spurious-free dynamic range

68dB signal-to-noise ratio

No missing codes

■

Applications

■

CCD imaging

■

IR imaging

■

FLIR processing

■

Medical imaging

■

High definition video

■

Instrumentation

■

Radar processing

Digital communications

The CLC949 incorporates an input sample-and-hold amplifier

followed by a quantizer which uses a pipelined architecture to min-

imize comparator count and the associated power dissipation

penalty. An on-board voltage reference is provided. Analog input

signals, conversion clock, and a single supply are all that are

required for CLC949 operation.

■

The CLC949 exhibits very stable performance over the commercial

and industrial temperature ranges. Most parameters shift very

little as the ambient temperature changes from -40°C to 85°C. An

exception to this rule is the dynamic performance of the converter.

As the temperature is increased, the distortion increases,

especially at higher input frequencies. This can be seen in the plot

on page 3. For input frequencies below 7MHz, there is relatively

little variation in distortion as the temperature is changed, but at

higher input frequencies, it is apparent that the performance

degrades as the temperature is increased.

SFDR (dBc)

Note that the reason for this degradation is the reduced ability of

the CLC949 to handle high slew rates at high temperatures. In

applications such as CCD imaging systems, where the slew rate at

the A/D sampling instant is very low, this degradation will not be

nearly so pronounced.

For applications requiring high temperature operation and very low

distortion with high frequency input signals, use of an external

sample-and-hold amplifier may enhance performance by reducing

the slew rates that the CLC949 sees during its sampling period (just

after the falling edge of CLK).

Power Dissipation vs. Conversion Rate

200

150

100

The CLC949 is fabricated in a 0.9µm CMOS technology. The

CLC949ACQ is specified over the commercial temperature range

of 0°C to +70°C and the CLC949AJQ is specified over the indus-

trial range of -40°C to +85°C. Both are packaged in a 44-pin

Plastic Leaded Chip Carrier (PLCC)

Sample Rate (MSPS)

Printed in the U.S.A.

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(+V_DD= + 5V, Medium Bias (200µA): unless specified)

CLC949 Electrical Characteristics

PARAMETERS

CONDITIONS

TYP

MIN/MAX RATINGS

UNITS SYMBOL

Case Temperature

+25˚C

0 to 70˚C -40 to 85˚C

DYNAMIC CHARACTERISTICS

overvoltage recovery V_IN= 1.5FS

effective aperture delay

aperture jitter

slew rate

settling time

3.0

7.0

400

6.2

ps(rms)

V/µS

NOISE and DISTORTION (20MSPS)

Signal-to-Noise Ratio (no harmonics)

4.985MHz;

SNR2

SNR3

9.663MHz;

Spurious-Free Dynamic Range

4.985MHz;

FS -1dB

dBc

SFDR2

SFDR3

9.663MHz;

Intermodulation Distortion

f₁= 5.58MHz @ FS -7dB; f₂= 5.70MHz @ FS -7dB

3dB bandwidth (full power)

-70

100

dBc

MHz

IMD

NOISE and DISTORTION (5MSPS, low bias)

Signal-to-Noise Ratio (no harmonics)

2.4MHz;

Spurious-Free Dynamic Range

2.4MHz;

SNR1

FS -1dB

dBc

SFDR1

NOISE and DISTORTION (25.6MSPS, high bias)

Signal-to-Noise Ratio (no harmonics)

9.894MHz;

Spurious-Free Dynamic Range

9.894MHz;

SNR4

FS-1dB

dBc

SFDR4

DC ACCURACY and PERFORMANCE

differential non-linearity

integral non-linearity

common mode rejection ratio

missing codes

mid-scale offset

temperature coefficient

gain error

dc; FS

0.5

1.2

5.0

1.0

3.5

1.0

3.5

1.0

3.5

LSB

codes

µV/°C

%FS

DNL

INL

CMRR

VIO

DVIO

5.0

power supply rejection

V_dda

PSRA

PSRD

V_ddd

VOLTAGE REFERENCE CHARACTERISTICS

positive reference voltage (internal)

negative reference voltage (internal)

3.25

1.25

2.0

3.24-3.26 3.24-3.26

1.24-1.26 1.24-1.26

1.98-2.02 1.98-2.02

3.24-3.26

1.24-1.26

1.98-2.02

VREFP

VREFN

VDIFF

differential reference voltage (Vrefp - Vrefn)

ANALOG INPUT PERFORMANCE

common mode range

differential range

analog input bias current

analog input capacitance

2 - 3

± 2

±0.1

5.0

µA

VCM

VDM

IBN

±1.0

CIN

DIGITAL INPUTS

CMOS input voltage

logic LOW

logic HIGH

logic LOW

logic HIGH

4.0

±1.0

4.0

±1.0

4.0

±1.0

µA

VIL

VIH

IIL

CMOS input current

±0.1

IIH

DIGITAL OUTPUTS

CMOS output voltage

logic LOW

logic HIGH

0.25

4.8

0.5

4.5

0.5

4.5

0.5

4.5

VOL

VOH

TIMING

maximum conversion rate

minimum conversion rate

data hold time

7.0

6.5

4.5

6.5

4.5

6.5

4.5

6.5

MSPS

KSPS

CRM

THLD

pipeline delay

clocks

POWER REQUIREMENTS

supply current (+V_dd)

220

300

IDD

PDM

PDL

PDH

power dissipation

20MSPS

5MSPS

30MSPS

power dissipation (low bias)

power dissipation (high bias)

400

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels

are determined from tested parameters.

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(+V = + 5V, Med Bias, F_s= 20MSPS: unless specified)

CLC949 Typical Performance Characteristics

Output Spectrum 1MHz

Output Spectrum 9MHz

Output Spectrum 15MHz

-20

-40

-60

-80

-100

-120

-100

-120

-100

-120

Frequency (MHz)

SNR & SFDR vs. Input Amplitude 5MHz

SNR & SFDR vs. Input Amplitude 9MHz

SNR & SFDR vs. Input Amplitude 1MHz

SFDR

SNR

SFDR

SNR

SFDR

SNR

-50

-40

-30

-20

-10

-50

-40

-30

-20

-10

-50

-40

-30

-20

-10

Input Amplitude (dBFS)

SNR vs. Sample Rate vs. Bias

SFDR vs. Sample Rate vs. Bias

SNR & SFDR vs. Input Frequency

Medium Bias

High Bias

Low Bias

High Bias

Medium Bias

Low Bias

SFDR (dBc)

SNR (dB)

F_in= 5MHz

F_S= 20MHz

0.1

1.0

100

0.1

1.0

100

100k

10M

100M

Sample Rate (MSPS)

Input Frequency (MHz)

Two Tone Intermodulation Distortion

Integral Non-Linearity

Differential Non-Linearity

-20

2.5

1.5

-40

0.5

-60

-0.5

-1

-80

-0.5

-1

-1.5

-2

-100

-120

-2.5

-1.5

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

Output Code

Pulse Settling Response

SFDR vs. Input Frequency

I/O Timing (Convert CLK & Bit Skew)

4000

3000

400

300

200

100

-20°C

0°C

20°C

2000

1000

Output Data

Convert

40°C

60°C

80°C

100

150

200

100

Input Frequency (MHz)

Time (ns)

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Recommended Operating Conditions

Absolute Maximum Ratings*

supply voltage (V_DD

differential voltage between any two GND’s

analog input voltage range

digital input voltage range

output short circuit duration (one pin to gnd)

junction temperature

)

-0.5V to +7V

supply voltage (V_DD

)

+5V ± 5%

<10mV

1.25 – 3.25V

0 to V_DD

0°C to 70°C

> 25ns

200mV

-0.5V to +V_DD

infinite

differential voltage between any two GND’s

analog input voltage range (full scale)

digital input voltage range

operating temperature range

clock pulse-width high (C_pwh

+175°C

)

storage temperature range

lead solder duration (+300°C)

-65°C to +150°C

10 sec

*NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired.

Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device

reliability.

Pinout & Pin Description and Usage

will all be tied together. For more detailed discussion,

please refer to the paragraph on power and grounds in

the applications section of the databook.

5 4 3 2 1 44 43 42 41 40

V_REFMO

V_REFP

V_REFN

BCO

TOP VIEW

D12(LSB)

D11

Clock (CLK)

The CLK accepts a CMOS clock input. Samples are

taken on the falling edges of the CLK and data emerges

6 1/2 clock cycles later, on to the rising edge of the CLK.

D10

_REFPC10

V_REFNC11

NC 12

35 D9

34 D8

44-Pin PLCC

BIASC

GND_A

V_INP

Output Data (D1-D12, MSBINV, OE\)

The data emerges from the CLC949 as CMOS level

digital data on D1(MSB) through D12(LSB). The

outputs can be put into a high impedance state by

bringing OE\ high. There is an internal pulldown

resistor so that if this input is left open, the output data is

enabled. MSBINV will invert the MSB of the output data.

With MSBINV in the high state, the output data is two’s

complement, when low, the output data format is offset

binary. An internal pulldown resistor makes the output

default to offset binary if MSBINV is left open.

V_INN

GND_A

18 19 20 21 22 23 24 25 26 27 28

References (V

, V

REFN

REFP

REFNO

REFPO

REFNC

, V

)

REFPC

REFMO

To use the internal references, connect V

to V

REFP

REFPO

and V

to V

. The nominal value for V

REFNO

REFN

REFPO

3.25V and for V

internal reference points which should be bypassed to

GND with a 0.1µF capacitor. is an output

voltage that is equal to the mid point of the reference

range and can be used to apply the appropriate offset to

the analog inputs. For a more detailed discussion on

references, see the paragraph on references in the

applications section of this datasheet.

is 1.25V. V

and V

are

REFNO

REFPC

REFNC

Bias Control (BCO, BC1, BIASC)

The DC bias current of the CLC949 is controlled by three

pins: BCO, BC1, and BIASC. BC0 and BC1 are digital

CMOS inputs and set the bias current in accordance with

the truth table below:

REFMO

BC0 BC1

Bias Current

PD@10MSPS

Default: Med Bias (200µA) 200mW

Analog Input (V , V

)

INP

INN

The analog input to the CLC949 is a differential signal

applied to V and V . For more detail on driving the

Analog Mode

Variable

350mW

75mW

INP

INN

High Bias (400µA)

Low Bias (50µA)

inputs, see the paragraphs in the applications section of

this datasheet.

Power Supplies and Grounds (V , V

The power and ground pins of the CLC949 are split into

those that supply the analog portions of the integrated

, GND , GND )

A D

DDA DDD

In the analog mode, the user provides a bias current

through the BIASC pin of the CLC949. As the bias

current is increased, the power dissipation of the CLC949

is increased and the part becomes capable of increased

conversion rates.

circuit (V

, GND ) and the digital portions of the chip

DDA

, GND ). If your system uses separate power and

DDD

ground planes, then performance can be improved by

making use of the appropriate pins. In many systems,

the power pins will all be tied together and the GND pins

No connection - leave these pins open.

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CLC949 OPERATION

+5V

Application

2.2k

10k

In a high speed data acquisition system, the overall

performance is often determined by the A/D converter

and its surrounding circuitry. You should pay special

attention to the data converter and its support circuitry if

you want to obtain the best possible performance. The

information on these pages is intended to help you

design the circuitry surrounding the CLC949 in such

a way as to achieve superior results. Additional

information is available in the form of Comlinear

applications notes. Especially useful are AD-01 and

AD-02.

0.1µF

Sinusoisal

Clock Input

To CLC949

Clock

0.1µF

CLC006

74AC04

+5V

10k

50Ω

2.2k

10k

50Ω

0.1µF

Figure 2: Clock Generation

Here the CLC006 cable driver is used as a comparator to

generate a high speed clock. The CLC006 has less than

2ps of jitter and has rise and fall times less than 1ns. The

CLC006 output is then buffered by a 74AC04 which

maintains fast edge rates and provides CMOS levels for

the CLC949. If there is excessive jitter in the CLK, then

the digitized signal will exhibit an excessive amount of

noise, especially for high frequency inputs. For a more

detailed description of this phenomenon, please read the

Comlinear Application Note AD-03.

Circuit Description

The CLC949 ADC consists of an input Sample-and-Hold

Amplifier (SHA) followed by a pipelined quantizer.

Internal reference sources and output data latches

complete the major functions required of an A/D

converter. Digital error correction in the quantizer helps

to provide accurate conversions of high speed dynamic

signals. The speed of the analog circuitry is determined

in part by the internal bias currents applied. The CLC949

allows you to make this important tradeoff between

power and performance through settings on two digital

control pins and for fine adjustments through the use of

an external resistor.

In addition to the circuitry generating the clock, the

layout of the clock distribution network can affect the

overall performance of the converter. To obtain the best

possible performance, a clock driver with very low output

impedance and fast edge rates such as the 74AC04,

should be placed as close as possible to the CLC949

clock input pin. Additional length in the circuit trace for

the clock will cause an increase in the jitter seen by the

converter. On the CLC949 evaluation board, the

E949PCASM, there is less than 1/16th of an inch

between the 74AC04 that is driving the clock input and

the input to the CLC949. If the system has several

CLC949s, and jitter is liable to generate problems, then

use a separate clock driver for each CLC949. Each

driver should be placed as close to the converter that it is

driving as is practicable.

Timing and CLK Generation

The falling edge of the CLK pulse causes the input sam-

ple-and-hold amplifier to transition into the hold mode.

The sample is taken approximately 3ns after this falling

edge. The digitized data is presented to the output latch-

es 6 1/2 clock cycles later and is held until after the next

rising edge of CLK. This timing is shown in the timing

diagram, Figure 1.

Effective Aperture Delay

Sample 0

Sample 2 Sample 4

Sample 7

Analog

Input

Sample 6

Driving the Differential Input

Sample 1

Sample 3 Sample 5

The CLC949 has a differential input with a common

mode voltage of 2.25V. Since not all applications have a

signal preconditioned in this manner there is often a need

to do a single-ended-to-differential conversion and to add

offset. In systems which do not need to be DC coupled,

the best method for doing this is with an RF transformer

such as the Minicircuits TMO1-1T. This is an RF

transformer with a center tapped secondary which will

operate over a frequency range of 50kHz to 200MHz.

You can offset the input and split the phases simply by

connecting the center tap to the mid scale reference

CLK

Output

Data

Sample

-3 Valid

Sample

-2 Valid

Sample

-1 Valid

Sample

0 Valid

Output Hold Time

Figure 1: Timing Diagram

The CLC949 is designed to operate with a CMOS clock

signal. To obtain the lowest possible noise when

digitizing a high frequency input, more care must be

taken in the generation of this clock than is usually

accorded to CMOS Clocks. To minimize aperture jitter

induced errors, the CLK needs to have as low a

jitter as possible and as fast an edge rate as possible. To

obtain a very low jitter clock from a sinusoidal source, the

circuit shown in Figure 2 is recommended.

output (V

) as shown in Figure 3.

REFMO

This set up can be realized on the CLC949 evaluation

board by enabling option 1. See E949PCASM data

sheet for details. A transformer coupled input will allow

the CLC949 to exhibit the best possible distortion

performance for high frequency input signals.

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V_IN

Reference Generation

The CLC949 has internally generated reference

voltages. To use these references, you must externally

V_INP

15pF

CLC949

V_REFMO

connect the reference inputs by shorting V

50Ω

REFPO

and V

to V .

During the conversion

REFP

REFNO

REFN

V_INN

cycle, the impedance on these four pins varies

dynamically. To maintain stable biases on these pins you

must bypass them with 0.1µF to GND. If you want to pro-

vide an external reference, then you have to be careful

TM01-1T

Figure 3: Transformer Coupled Input

Since the transformer response does not extend to DC it

is not an effective solution for applications which require

DC coupled inputs.

to provide low output impedance drivers to the V

and

REFP

pins. Bypass capacitors on all reference pins are

REFN

recommended for best performance.

To drive the input of the CLC949, and retain DC

information, an amplifier configuration is required.

Comlinear suggests the use of the circuit shown in Figure 4.

This circuit is used on the E949PCASM.

Bias Control

One of the unique features of the CLC949 is that it allows

you to set the internal bias current of the device. When

designing an A/D converter a tradeoff is made between

the amount of power dissipated and the

performance. The CLC949 allows you to make this

tradeoff yourself. The bias current is controlled by the

pins BC0 and BC1. These two pins are digital input pins

from which one of three discrete bias points may be

selected (see truth table on page 4 of this datasheet) or

an external bias may be provided through the analog bias

control pin BIASC. If BC0 and BC1 are left open, they

will drift low and provide the default bias condition which

results in 220mW of dissipation at 20MHz sampling rate.

The actual power dissipated by the device is a function

of both the bias condition and the sample rate. The

relationship between power and speed is shown for the

three discrete bias points in Figure 5.

CLC428

U5A

1.25k

+5V

CLC428

U5B

500Ω

+5V

500Ω

V_REFMO

400Ω

R27

V_INP

CLC409

V_IN

R30

50Ω

15pF

+5V

50Ω

CLC949

R29

400Ω 400Ω

R10

50Ω

400Ω

R26

50Ω

V_INN

CLC409

Power Dissipation vs. Sample Rate

50Ω

400

400Ω

High Bias

300

Figure 4: Amplifier Coupled Input

In this circuit U7 buffers the analog input with a gain of

+1, and U6 buffers the input with a gain of -1. The

circuit has been designed so that U6 and U7 have the

same loop gain, thereby offering the best possible match

of their AC characteristics. U5 is used to generate the

required offset voltages which are summed into the input

signal via U6 and U7. The CLC409 was selected for U6

and U7 due to its current feedback topology which allows

for very low distortion even at high frequencies, and its

excellent phase linearity. Phase match between U6 and

U7 is critical for good pulse response. To generate the

D.C. offsets, the CLC428 dual Op-amp was selected.

The CLC428 is a voltage-feedback op amp with very

good DC characteristics, and the large bandwidth makes

the output impedance low over a wide range of frequen-

cies, allowing good AC performance.

200

Medium Bias

100

Low Bias

100k

10M

40M

Sample Rate (Hz)

Figure 5: Power Dissipation vs. Sample Rate

As the bias is turned up, the ability of the CLC949 to

handle high frequency inputs and the power dissipation

of the CLC949 increases. To use the BIASC pin, attach

a resistor from the pin to V

. The current drawn by this

DDA

resistor is mirrored in the device to set the internal bias

currents. A smaller value resistor will result in higher bias

currents and higher performance.Beyond a certain

point, additional improvement is not seen, although

power continues to increase. For this reason, it is

recommended that bias setting resistors of less than

10K not be used. To generate the graph in Figure 6 a

CLC949 was set to sample a signal 1dB below full scale

Regardless of how the input is driven, a small capacitor

(15pF) should be added from the V

and V

INP

INN

terminals to GND. This will help to reduce the current

transients that are generated by the CLC949 inputs

during sampling.

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with a frequency of 1/2 the sample rate. The bias current

was then turned up until the SNR was better than 65dB

and the SFDR exceeded 72dB. The axis on the left

shows the power that was dissipated by the device as a

function of speed, whereas the other curve uses the axis

on the right to show the resistor value required to obtain

this bias.

the McKenzie #PLCC-44P-T-SMT socket which has low

parasitic impedances. The traces from the clock source

to the CLC949 should be as short as possible, if forced

to put the clock driver more than a couple of

centimeters away from the CLC949, then add a buffer for

the clock right next to the CLC949.

There is an evaluation board available for the CLC949

(E949PCASM) This board can be used to quickly

evaluate the performance of the CLC949 data converter.

Use of this evaluation board as a model for your PCB lay-

out is recommended. The schematic for this evaluation

board is shown in Figure 8 on the following page. The

board layout for the E949PCASM is shown in the

E949PCASM datasheet.

Power Dissipation & Programming

Resistor vs. Sample Rate

200

150

100

Resistor

Power

Power Supplies, Grounding and Bypassing

To obtain the best possible performance from high speed

devices, you must pay close attention to power supplies,

bypassing and grounding. This applies not only to the

A/D converter itself but to the entire system.

Sample Rate (MSPS)

The recommended supply decoupling scheme for the

CLC949 includes:

Figure 6: Power Dissipation & Programming

Resistor vs. Sample Rate

One 0.01 to 0.033µF capacitor between each

power pin and GND.

One 6.8 to 10µF capacitor per board, placed no

more than a few inches from the A/D connected

•

Dynamic Power Down

In systems where you do not use the A/D converter con-

tinually, and low power consumption is a key require-

ment, the power to the CLC949 can be turned down while

it is not being used. This is done through the use of the

BIASC pin, and a programming resistor to the power

supply. When the potential on this resistor is brought low,

the part goes into a sleep mode which saves power. This

can be accomplished by connecting the bias setting

resistor to a CMOS gate as shown in Figure 7. In sleep

mode the CLC949 will draw approximately 8mA, or

40mW on a 5V supply.

between V and GND.

One 0.1µF capacitor from each of the reference

•

inputs (V

, V

) to GND.

REFP

REFN

REFPC

REFNC

If the board has supplies that include excessive

digital switching noise, then ferrite beads in series

with the power feed to the A/D should also be

included.

Proper bypassing of all other integrated circuits

on the board, especially digital logic I.C.s.

•

Package Thermal Resistance

CLC949

Package

θ_JC

θ_JA

BIASC BC0 BC1

Sleep

44-pin PLCC

10°C/W

35°C/W

R_p*

10k

CMOS Inverter

Ordering Information

V_DD

*See Figure 6 above.

Model

Temperature Range

Description

CLC949ACQ

CLC949AJQ

0 C to +70 C

44-pin PLCC

Figure 7: Dynamic Power Savings

PCB Layout

-40 C to +85 C

The keys to

a successful CLC949 layout are

Power Requirements

a substantial low-impedance ground plane, short

connections in and out of the data converter, and proper

power supply decoupling. The use of a socket for the

final design is not recommended but if one must be used

during debug or prototyping, then Comlinear recommends

Typ

Units

V_cc= +5V, 5MSPS, Low Bias

V_cc= +5V, 20MSPS, Med Bias

V_cc= +5V, 30MSPS, High Bias

220

400

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B C 1

C L K

N C

D 2

D 1 ( M S B )

O E \

D D D

M S B I N V

G N D

D D D

G N D

D D A

G N D

D D A

G N D

D D A

G N D

R E F N O

G N D

R E F P O

Figure 8: CLC949 Evaluation Board

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Lit #150949-004

CLC949AJQ [NSC]

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