COP988GD-XXX/V [NSC]
IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44, Microcontroller;
| 型号： | COP988GD-XXX/V |
| 厂家： | 
National Semiconductor |
| 描述： | IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44, Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总42页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1998
COP888GD/COP988GD 8-Bit Microcontroller with A/D
Converter
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semicon-
ductor's M2CMOS™ process technology. The COP888GD
is a member of this expandable 8-bit core processor family
■ Schmitt trigger inputs on ports G and L
■ Package: 44 PLCC with 40 I/O Pins
CPU/Instruction Set Features
■ 1 µs instruction cycle time
■ Twelve multi-source vectored interrupts servicing
— External Interrupt
of microcontrollers.
(continued)
— Idle Timer T0
— Three Timers (Each with 2 Interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
Key Features
■ 8-channel A/D converter with prescaler and both differ-
ential and single ended modes
■ Three 16-bit timers, each with two 16-bit registers sup-
porting
— Default VIS (default inte
■ Versatile and easto use iion se
■ 8-bit Stack Pointer ) - stain RAM
■ Two 8-bit Register Inrect Datmory Pointers (B
and X)
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
■ Quiet design (low radiated emissions)
■ 16k bytes on-board ROM
■ 256 bytes on-board RAM
Fully StaOS
■ Twpower g mods: HALT and IDLE
■ Low rrent ain (typally < 1 µA)
■ Single pply opation: 2.5V to 5.5V
■ peraturanges:0˚C to + 70˚C, –40˚C to +85˚C
Additional Peripheral Features
■ Idle Timer
■ Multi-Input Wake-Up (MIWU) with optional interrupts (8)
■ WATCHDOG and clock monitor logic
■ MICROWIRE/PLUS™ serial I/O
pment Support
n and OTP devices
■ me emulation and full program debug offered by
MetaLink Development System
I/O Features
■ Memory mapped I/O
■ Software selectable I/O options (TRI-STATE® utpu
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
Block Diagram
I/O PORTS
POWER/CONTROL
CLOCK
RD
D
L
C
G
I
Vcc
GND CKI Reset
HALT
IDLE
WAKE UP
A/D
16 BIT
CONVERTER
RESET
16
TIMER
T1
MICRO
WIRE/
PLUS
IDLE
TIMER
T0
WATCHDOG
INTERRUPT
ENAD REG
A
B
X
INSTR
DECODE
LOGIC
16K
BYTES
ROM
256
BYTES
RAM
16 BIT
TIMER TIMER
T2 T3
16 BIT
MULTI
INPUT
WAKEUP
SP
PSW
CNTRL
ICNTRL
S
ALU
ILLEGAL
COND
DETECT
PC
ADDR
REG
CPU REGISTERS
Figure 1. COP888GD Block Diagram
TRI-STATE® is a registered trademarks of National Semiconductor Corporation. iceMASTER™ is a trademark of MetaLink Corporation.
MICROWIRE/PLUS™, M2CMOS™, COPS™ microcontrollers, and MICROWIRE™ are trademarks of National Semiconductor Corporation.
©1998 National Semiconductor Corporation
www.national.com
IDLE Timer with 5 selectable interrupt periods which can be
used to wake the device from the IDLE mode. Each I/O pin
has software selectable configurations. The devices operate
over a voltage range of 2.5V to 5.5V. High throughput is
achieved with an efficient, regular instruction set operating at
a maximum rate of 1 µs per instruction. Low radiated emis-
sions are achieved by gradual turn-on output drivers and in-
ternal ICC smoothing filters on the chip logic and crystal
oscillator.
General Description (Continued)
It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE serial I/O, three
16-bit timer/counters supporting three modes (Processor In-
dependent PWM generation, External Event counter, and In-
put Capture mode capabilities), 8 channel analog to digital
convertor, and two power saving modes (HALT and IDLE),
both with a multi-sourced wakeup/interrupt capability. This
multi-sourced interrupt capability may also be used indepen-
dent of the HALT or IDLE modes. The device includes an
Connection Diagrams
Plastic Lead Chip Ca
44 4344140
6 5 4 3 2
CKI
VCC
I0
I1
I2
I3
I4
I5
7
8
39
G0
38
37
36
35
34
33
32
31
30
29
RESET
GND
D7
D6
D5
D4
D3
D2
D1
9
10
11
12
13
44-PIN
LCC
I7
L0
D0
18
20
21 22 23 24 25 26 27
19
28
Top View
Order Number COP888GD-XXX/V, or COP988GD-XXX/V,
See NS Package Number V44A
Figure 2. Connection Diagrams
www.national.com
2
Connection Diagrams (Continued)
Pinouts for 44-Pin Packages
44-Pin
PLCC
Port
Type
I/O
Alt. Fun
Alt. Fun
L0
L1
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
INT
17
18
19
20
25
26
27
28
39
1
42
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WDOUT
I/O
I/O
I/O
I/O
I
L2
L3
L4
T2A
T2B
T3A
T3B
L5
L6
L7
G0
G1
G2
G3
G4
G5
G6
G7
D0
D1
D2
D3
D4
D5
D6
D7
I0
T1B
T1A
SO
SK
4
SI
5
I/CKO
O
HALT Restart
6
29
30
31
32
33
34
35
36
9
O
O
O
O
O
O
O
H0
1
H2
ACH3
ACH4
ACH5
ACH6
ACH7
I1
I
10
11
12
13
14
15
16
43
44
1
I
I
I7
I
C0
C1
C2
C3
C4
C5
C6
C7
VCC
GND
CKI
RESET
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
21
22
23
24
8
37
7
38
www.national.com
3
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please
contact the National SemiconductorSales Office/Distributors
for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
100 mA
110 mA
–65˚C to +140˚C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
Supply Voltage (VCC
)
7V
Voltage at Any Pin
–0.3V to VCC +0.3V
DC Electrical Characteristics COP988GD: 0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Operating Voltage
COP988GD
2.5
5.5
V
V
Power Supply Ripple (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
Peak-to-Peak
0.1 V
CC
V
V
= 5.5V, t = 1 µs
16
6
mA
mA
CC
c
CKI = 4 MHz
= 4.5V, t = 2.5µs
CC
c
HALT Current (Note 3)
V
V
= 5.5V, CKI = 0 MHz
= 4.5V, CKI = 0 MHz
3
8
5
µA
µA
CC
CC
IDLE Current (Note 2)
CKI = 10 MHz
V
V
= 5.5V, tc = 1µs
1.2
1.0
mA
mA
CC
CKI = 4 MHz
= 5.5V, tc = 2.5 µs
CC
Input Levels
RESET, CKI
Logic High
0.8
V
V
CC
CC
Logic Low
0.2 V
CC
All Other Inputs (L0-L7, G0-G6, C0-C7, I0-I7)
Logic High
0.7 V
–1
V
V
Logic Low
0.2 V
+1
CC
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis (Note 6)
Output Current Levels
D Outputs
V
V
= 5.5V
µA
µA
V
CC
= 5, V =
–40
–250
0.35 V
CC
IN
CC
Source
= 4.5= 3.3V
–0.4
–0.2
10
mA
mA
mA
mA
OH
2.5V, V = 1.8V
OH
Sink
4.5V, V = 1.0V
OL
2.5V, V = 0.4V
2.0
OL
All Others
Source (Weak Pu
V
V
V
V
V
V
V
= 4.5V, V = 2.7V
–10
–2.5
–0.4
–0.2
1.6
–100
–33
µA
µA
CC
CC
CC
CC
CC
CC
CC
OH
= 2.5V, V = 1.8V
OH
Source (Push-Pull M
Sink (Push-Pull Mode)
= 4.5V, V = 3.3V
mA
mA
mA
mA
µA
OH
= 2.5V, V = 1.8V
OH
= 4.5V, V = 0.4V
OL
= 2.5V, V = 0.4V
0.7
OL
TRI-STATE Leakage
Allowable Sink/Source
Current per Pin
= 5.5V
–1
+1
D Outputs (Sink)
15
3
mA
mA
mA
All others
Maximum Input Current
without Latchup (Note 4,6)
RAM Retention Voltage, Vr
Input Capacitance
Room Temp.
±100
500 ns Rise and Fall Time (Min)
2
V
7
pF
pF
Load Capacitance on D2
1000
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4
AC Electrical Characteristics COP988GD: 0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal, Resonator
4.5V ≤ V ≤ 5.5V
1
DC
DC
DC
DC
60
5
µs
µs
µs
µs
%
CC
2.5V ≤ V < 4.5V
2.5
3
CC
R/C Oscillator
4.5V ≤ V ≤ 5.5V
CC
2.5V ≤ V < 4.5V
7.5
40
CC
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Inputs
f = Max
r
f = 10 MHz Ext Clock
ns
ns
r
f = 10 MHz Ext Clock
5
r
t
4.5V ≤ V ≤ 5.5V
200
500
60
ns
ns
ns
ns
SETUP
CC
2.5V ≤ V < 4.5V
CC
t
4.5V ≤ V ≤ 5.5V
HOLD
CC
2.5V ≤ V < 4.5V
150
CC
Output Propagation Delay
, t
R = 2.2k, C = 100 pF
L L
t
PD1 PD0
SO, SK
4.5V ≤ V ≤ 5.5V
0.7
1.75
1
µs
µs
µs
µs
ns
ns
ns
CC
2.5V ≤ V < 4.5V
CC
All Others
4.5V ≤ V ≤ 5.5V
CC
2.5V ≤ V < 4.5V
2.5
CC
MICROWIRE™ Setup Time (t
) (Note 5)
0
56
UWS
MICROWIRE Hold Time (t
) (Note 5)
UWH
MICROWIRE Output Propagation Delay (t
Input Pulse Width (Note 6)
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
)
220
UPD
1
1
1
1
1
t
t
t
t
c
c
c
c
Timer Input Low Time
Reset Pulse Width
µs
t
= Instruction cycle time
c
Note 1: Maximum rate of voltage change must be < 0.5 V/.
Note 2: Supply and IDLE currents are measured with CKI driven with a sqre wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to
VCC and outputs programmed low but not connectad.
Note 3: The HALT mode will stop CKI froosciC and e Crystal configurations. Measurement of IDD HALT is done with device neither sourcing
nor sinking current; with L, C, G0, and G2-G5 w outputs and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G . Part will pull up CKI during HALT in crystal clock mode.
Note 4: Pins G6 and RESEd with a nput network. These pins allow input voltages > VCC and the pins will have sink current to VCC
when biased at voltages > ot have current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical).
These two pins will not lthe pins ust be limited to < 14 Volts. WARNING: Voltages in excess of 14 volts will cause damage to the
pins. This warning exc
Note 5: The output proced to the end of the instruction cycle where the output change occurs.
Note 6: Parameter char.
www.national.com
5
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please
contact the National SemiconductorSales Office/Distributors
for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
100 mA
110 mA
–65˚C to +140˚C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
Supply Voltage (VCC
)
7V
Voltage at Any Pin
–0.3V to VCC +0.3V
DC Electrical Characteristics COP888GD: –40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Operating Voltage
Conditions
Min
Typ
Max
Units
2.5
5.5
V
V
Power Supply Ripple (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
Peak-to-Peak
0.1 V
CC
V
V
V
V
= 5.5V, t = 1 µs
16
6
mA
mA
µA
CC
CC
CC
CC
c
CKI = 4 MHz
= 4.5V, t = 2.5 µs
c
HALT Current (Note 3)
= 5.5V, CKI = 0 MHz
= 4.5V, CKI = 0 MHz
10
7.5
µA
IDLE Current (Note 2)
CKI = 10 MHz
V
V
= 5.5V, t = 1 µs
1.2
1.0
mA
mA
CC
c
CKI = 4 MHz
= 5.5V, t = 2.5 µs
CC
c
Input Levels
RESET, CKI
Logic High
0.8 V
V
V
C
CC
Logic Low
0.2 V
CC
All Other Inputs (L0-L7, G0-G6, C0-C7, I0-I7)
Logic High
0.7 V
V
V
Logic Low
0.2 V
+2
CC
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis (Note 6)
Output Current Levels
D Outputs
V
V
= 5.5V
–2
–40
µA
µA
V
CC
= 5.5V, V
–250
0.35 V
CC
IN
CC
Source
V
= 4.5V, V 3.3V
–0.4
–0.2
10
mA
mA
mA
mA
CC
OH
= 2.5= 1.8V
OH
Sink
4.5V, V = 1.0V
OL
2.5V, V = 0.4V
2.0
OL
All Others
Source (Weak Pull
V
V
V
V
V
V
= 4.5V, V = 2.7V
–10
–2.5
–0.4
–0.2
1.6
–100
–33
µA
µA
CC
CC
CC
CC
CC
CC
CC
OH
= 2.5V, V = 1.8V
OH
Source (Push-Pull
Sink (Push-Pull Mode)
= 4.5V, V = 3.3V
mA
mA
mA
mA
µA
OH
= 2.5V, V = 1.8V
OH
= 4.5V, V = 0.4V
OL
= 2.5V, V = 0.4V
0.7
OL
TRI-STATE Leakage
Allowable Sink/Source
Current per Pin
= 5.5V
–2
+2
D Outputs (Sink)
15
3
mA
mA
mA
All others
Maximum Input Current
without Latchup (Note 4, 6)
RAM Retention Voltage, Vr
Input Capacitance
Room Temp.
±100
500 ns Rise and Fall Time (Min)
2
V
7
pF
pF
Load Capacitance on D2
1000
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6
AC Electrical Characteristics COP888GD: –40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal, Resonator
4.5V ≤ V ≤ 5.5V
1
DC
DC
DC
DC
60
5
µs
µs
µs
µs
%
CC
2.5V ≤ V < 4.5V
2.5
3
CC
R/C Oscillator
4.5V ≤ V ≤ 5.5V
CC
2.5V ≤ V < 4.5V
7.5
40
CC
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
Inputs
f = Max
r
f = 10 MHz Ext Clock
ns
ns
r
f = 10 MHz Ext Clock
5
r
t
4.5V ≤ V ≤ 5.5V
200
500
60
ns
ns
ns
ns
SETUP
CC
2.5V ≤ V < 4.5V
CC
t
4.5V ≤ V ≤ 5.5V
HOLD
CC
2.5V ≤ V < 4.5V
150
CC
Output Propagation Delay
, t
R = 2.2k, C = 100 pF
L L
t
PD1 PD0
SO, SK
4.5V ≤ V ≤ 5.5V
0.7
1.75
1
µs
µs
µs
µs
ns
ns
ns
CC
2.5V ≤ V < 4.5V
CC
All Others
4.5V ≤ V ≤ 5.5V
CC
2.5V ≤ V < 4.5V
2.5
CC
MICROWIRE™ Setup Time (t
)
0
56
UWS
MICROWIRE Hold Time (t
)
UWH
MICROWIRE Output Propagation Delay (t
Input Pulse Width
)
220
UPD
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
1
t
t
t
t
c
c
c
c
Reset Pulse Width
µs
t
= Instruction cycle time
c
Note 1: Maximum rate of voltage change must be < 0.5 V/.
Note 2: Supply and IDLE currents are measured with CKI driven with a sqre wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to
VCC and outputs programmed low but not connectad.
Note 3: The HALT mode will stop CKI froosciC and e Crystal configurations. Measurement of IDD HALT is done with device neither sourcing
nor sinking current; with L, C, G0, and G2-G5 w outputs and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G . Part will pull up CKI during HALT in crystal clock mode.
Note 4: Pins G6 and RESEd with a nput network. These pins allow input voltages > VCC and the pins will have sink current to VCC
when biased at voltages > ot have current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical).
These two pins will not lthe pins ust be limited to < 14 Volts. WARNING: Voltages in excess of 14 volts will cause damage to the
pins. This warning exc
Note 5: The output proced to the end of the instruction cycle where the output change occurs.
Note 6: Parameter char.
www.national.com
7
A/D Converter Specifications VCC = 5V ±10%, (VSS – 0.050V) ≤ Any Input ≤ (VCC + 0.050V)
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
1
Bits
Absolute Accuracy
LSB
Non-Linearity
Deviation from the Best Straight Line
±1
±1
LSB
Differential Non-Linearity
Common Mode Input Range (Note 9)
DC Common Mode Error
Off Channel Leakage Current
On Channel Leakage Current
A/D Clock Frequency (Note 8)
Conversion Time (Note 7)
LSB
GND
0.1
V
V
CC
±1/2
2
LSB
1
1
µA
µA
MHz
2
1.67
17
A/D Clock Cycles
Internal Reference Resistance
Turn-on Time (Note 10)
1
µs
Note 7: Conversion Time includes 7 A/D clock cycle sample and hold time.
Note 8: See Prescaler description.
Note 9: For VIN(-)>=VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog odes will forward conduct for
analog input voltages below ground or above the VCC supply. Be careful, during testing at low VCC levels (4.5V), as nalog inputs (5V) can cause this
input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near ll-scale. Tallows mV forward bias of either
diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mVe utput cwill be coct. To achieve an absolute
0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over teature varns, ial tolerance and loading.
Note 10: Time for internal reference resistance to turn on and settle after coming out of HALT or IDLE mode.
SK
tUWS
tUWH
tUPD
SO
Figure 3. MICROWIRE/PLUS Timing
www.national.com
8
Port L supports Multi-Input Wakeup (MIWU) on all eight pins.
L4, L5, L6 and L7 are used for the timer input functions T2A,
T2B, T3A and T3B.
Pin Descriptions
VCC and GND are the power supply pins.
VCC and GND are the reference voltage pins for the on-board
A/D converter.
Port L has the following alternate features:
L0 MIWU
L1 MIWU
L2 MIWU
L3 MIWU
CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
L4 MIWU or T2A
L5 MIWU or T2B
L6 MIWU or T3A
L7 MIWU or T3B
RESET is the master reset input. See Reset Description sec-
tion.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently con-
figured as an input (Schmitt trigger inputs on ports G and L),
output or TRI-STATE under program control. Three data mem-
ory address locations are allocated for each of these I/O ports.
Each I/O port has two associated 8-bit memory mapped reg-
isters, the CONFIGURATION register and the output DATA
register. A memory mapped address is also reserved for the
input pins of each I/O port. (See the memory map for the var-
ious addresses associated with the I/O ports.) Figure 1 shows
the I/O port configurations. The DATA and CONFIGURATION
registers allow for each port bit to be individually configured
under software control as shown below:
Port G is an 8-bit port with 5 I/O pins (G0, G2--G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2--G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input depending on the oscil-
lator mask option selectehe cystal oscillator option
selected, G7 sees as thicated utput pin for the CKO
clock output. With e singlpin R/C oscillator mask option
selected, G7 serves a general purpose input pin, but is
also used to bring the dece out of HALT mode with a low to
high transG7. Thee are two registers associated
with the a datregister and a configuration register.
Treforeh of th5 I/O bits (G0, G2–G5) can be individ-
uallonfiged undr software control.
CONFIGURATION
Register
DATA
Register
Port Set-Up
Since Gis an input only pin and G7 is the dedicated CKO
outppin or general purpose input (R/C clock configu-
the associated bits in the data and configuration reg-
r G6 and G7 are used for special purpose functions
lined below. Reading the G6 and G7 data bits will re-
turn zeros.
Hi-Z Input (TRI-STATE)
Output
0
0
0
1
1
1
0
1
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One utput
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
PORT L, G, AND C
PIN
DATA
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
RE
I
N
T
E
R
N
A
L
CO
R
Config Reg.
Data Reg.
G7
G6
CLKDLY
HALT
IDLE
PORT D
PIN
PIN
Alternate SK
B
U
S
DATA
REGISTER
Port G has the following alternate features:
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
PORT I
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
Figure 1. I/O Port Configurations
Port G has the following dedicated functions:
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated
output
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
G7 CKO Oscillator dedicated output or general purpose in-
put
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9
The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement reg-
ister and skip if zero) instruction. The memory pointer regis-
ters X, SP, B and S are memory mapped into this space at
address locations 0FC to 0FF Hex respectively, with the oth-
er registers being available for general usage.
Port C is an 8-bit I/O port.
Port I is an 8-bit Hi-Z input port, and also provides the analog
inputs to the A/D converter. If unterminated, Port I pins will
draw power only when addressed.
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (except
D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At
RESET, the external loads on this pin must ensure that the
output voltages stay above 0.9 VCC to prevent the chip from
entering special modes. Also, keep the external loading on
D2 to less than 1000 pF.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are memo-
ry mapped; therefore, I/O bits and register bits can be directly
and individually set, reset and tested. The accumulator (A)
bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Functional Description
The architecture of the device is modified Harvard architec-
ture. With the Harvard architecture, the program memory
(ROM) is separated from the data memory (RAM). Both
ROM and RAM have their own separate address space with
separate address buses. The architecture, though based on
Harvard architecture, permits transfer of data from ROM to
RAM.
Data Memory Segment RAM Extension
Data memory address 0FF s a memory mapped lo-
cation for the Data Segmess egister (S).
The data store mmry is er addrssed directly by a sin-
gle byte address witn the inuctin, or indirectly relative to
the reference of the B, or SP pointers (each contains a sin-
gle-byte adThis gl-byte address allows an ad-
dressing 56 locations from 00 to FF hex. The upper
t of this byte ddress divides the data store memory
inttwo srate setions as outlined previously. With the
exceon of M register memory from address loca-
tions 00to 00FF, all RAM memory is memory mapped with
pper of the single-byte address being equal to zero.
ows the upper bit of the single-byte address to deter-
hether or not the base address range (from 0000 to
is extended. If this upper bit equals one (representing
address range 0080 to 00FF), then address extension does
not take place. Alternatively, if this upper bit equals zero, then
the data segment extension register S is used to extend the
base address range (from 0000 to 007F) from XX00 to XX7F,
where XX represents the 8 bits from the S register. Thus the
128-byte data segment extensions are located from address-
es 0100 to 017F for data segment 1, 0200 to 027F for data
segment 2, etc., up to FF00 to FF7F for data segment 255.
The base address range from 0000 to 007F represents data
segment 0.
CPU REGISTERS
The CPU can perform an 8-bit addition, subtraction, logical or
shift operation in one instruction (tc) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter PC)
B is an 8-bit RAM address pointer, which can bopnally
post auto incremented or decremented.
X is an 8-bit alternate RAM addrepoican bop-
tionally post auto incremented or de
SP is the 8-bit stack phich psubrou-
tine/interrupt stack (in is initid to RAM ad-
dress 06F with rese
All the CPU registered with the exception
of the Accumulator (Am Counter (PC).
Figure 2 illustrates how the S register data memory exten-
sion is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data seg-
ments of 128 bytes each with an additional upper base seg-
ment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data seg-
ment (128 bytes) to another. However, the upper base seg-
ment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment (ad-
dress range 0080 to 00FF) is independent of data segment
extension.
PROGRAM MEMORY
The program memory consists of 16,384 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the JID
instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program counter
(PC). All interrupts in the devices vector to program memory
location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, SP pointers and S register.
The instructions that utilize the stack pointer (SP) always ref-
erence the stack as part of the base segment (Segment 0),
regardless of the contents of the S register. The S register is
not changed by these instructions. Consequently, the stack
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10
(used with subroutine linkage and interrupts) is always locat-
ed in the base segment. The stack pointer will be initialized
to point at data memory location 006F as a result of reset.
trol registers are cleared. The Multi-Input Wakeup registers
WKEN, WKEDG, and WKPND are cleared. The Stack Point-
er, SP, is initialized to 06F Hex.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad-
dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock Mon-
itor bit set. The WATCHDOG and Clock Monitor detector cir-
cuits are inhibited during reset. The WATCHDOG service
window bits are initialized to the maximum WATCHDOG ser-
vice window of 64k tc clock cycles. The Clock Monitor bit is
initialized high, and will cause a Clock Monitor error following
reset if the clock has not reached the minimum specified fre-
quency at the termination of reset. A Clock Monitor error will
cause an active low error output on pin G1. This error output
will continue until 16–32 tc clock cycles following the clock
frequency reaching the minimum specified value, at which
time the G1 output will enter tRI-STATE mode.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F hex.
Reset
The external RC network Figure 3 should be used
to ensure that the RESET held lw until the power sup-
ply to the chip staes.
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration reg-
isters for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is ded-
icated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is initialized high with RESET. The PC, PSW, CN-
TRL, ITMR, ENAD, ICNTRL, T2CNTRL and T3CNTRL con-
P
VCC
COP
S
U
P
P
L
RESET
XXFF
RAM REGISTERS
(16 BYTES)
INCLUDES
B, X, SP, S
Y
GND
XXF0
XXEF
RC > 5 x POWER SUPPLY RISE TIME
TIMERS, I/O, MW
CNTRL, PSW,
ICNTRL, MWU,
A
Figure 3. Recommended Reset Circuit
XX90
XX8F
Oscillator Circuits
(R
UNDE
DATA)
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction cycle
clock (1/tc).
XX80
007F
017F
UNUSED*
0070
006F
Note: External clocks with frequencies above about 4 MHz
require the user to drive the CKO (G7) pin with a signal 180
degrees out of phase with CKI.
SP INITIALIZED
TO 6F
ON-CHIP RAM
(128 BYTES)
Figure 4 shows the Crystal and R/C diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.
ON-CHIP RAM
(112 BYTES)
0000
0100
* READS AS ALL ONES
Figure 2. RAM Organization
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11
To reduce the total current drain, each of the above compo-
nents must be minimum.
The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation,
can be reduced by lowering voltage and frequency. Leakage
current can be reduced by lowering voltage and temperature.
The other two items can be reduced by carefully designing
the end-user's system.
CKO
CKI
CKO
CKI
R2
R
R1
Vcc
C
I2 = C x V x f
C1
C2
where C = equivalent capacitance of the chip
V = operating voltage
Figure 4. Crystal and R/C Oscillator Diagrams
f = CKI frequency
Control Registers
Table 1 shows the component values required for various
standard crystal values.
CNTRL Register (Add0xEE)
Table 1 Crystal Oscillator Configuration, TA = 25˚C
The Timer1 (T1and MIWIRE/LUS control register
contains the followbits:
R1
R2
C1
C2
(pF)
CKI Freq
(MHz)
Conditions
CC = 5V
SL1 & SL0 Select thMICROWIRE/PLUS clock divide by
2, 01 4, x = 8)
(kΩ) (MΩ) (pF)
0
0
0
1
1
1
30
30
30--36
30--36
10
4
V
IEDG
nal interrupt edge polarity select
= Risg edge, 1 = Falling edge)
Selects G5 and G4 as MICROWIRE/PLUS sig-
s
VCC = 5V
VCC = 5V
ML
200 100--150
0.455
SK and SO respectively
R/C OSCILLATOR
Timer T1 Start/Stop control in timer
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
Timer T1 mode control bit
Timer T1 mode control bit
By selecting CKI as a single pin oscillator input, a single p
R/C oscillator circuit can be connected to it. CKO is availab
as a general purpose input, and/or HALT restart input.
T1C2
T1C3
Table 2 shows the variation in the oscillator freqencies as
functions of the component (R and C) values.
Timer T1 mode control bit
Table 2 R/C Oscillator Configuration, TA = 25˚C
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7
Bit 0
R
C
CKI Freq
(MHz)
Instr. y
( s)
itions
(kΩ) (pF)
PSW Register (Address X'0xEF)
3.3
5.6
6.8
82
2.2 to
1.1 t
0.9 t
4.6
0
8
CC = 5V
VCC = 5V
VCC = 5V
The PSW register contains the following select bits:
100
100
GIE
EXEN
BUSY
Global interrupt enable (enables interrupts)
Enable external interrupt
MICROWIRE/PLUS busy shifting flag
Note: 3k ≤ R ≤ 200k
50 pF ≤ C ≤ 200 pF
EXPND External interrupt pending
T1ENA
Timer T1 Interrupt Enable for Timer Underflow or
T1A Input capture edge
Current Drain
The total current drain of the chip depends on:
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
1. Oscillator operation mode—I1
2. Internal switching current—I2
3. Internal leakage current—I3
4. Output source current—I4
C
Carry Flag
HC
Half Carry Flag
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
5. DC current caused by external input not at VCC or
GND—I5
6. DC reference current contribution from the A/D convert-
er—I6
7. Clock Monitor current when enabled—I7
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset Car-
ry) instructions will respectively set or clear both the carry
flags. In addition to the SC and RC instructions, ADC, SUBC,
RRC and RLC instructions affect the carry and Half Carry
flags.
Thus the total current drain, It, is given as
It = I1 + I2 + I3 + I4 + I5 + I6 + I7
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12
ICNTRL Register (Address X'0xE8)
Timers
The ICNTRL register contains the following bits:
The device contains a very versatile set of timers (T0, T1, T2
and T3). All timers and associated autoreload/capture regis-
ters power up containing random data.
T1ENB
Timer T1 Interrupt Enable for T1B Input capture
edge
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
edge
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE mode
support is furnished by the IDLE timer T0, which is a 16-bit
timer. The Timer T0 runs continuously at the fixed rate of the
instruction cycle clock, tc. The user cannot read or write to
the IDLE Timer T0, which is a count down timer.
WEN
Enable MICROWIRE/PLUS interrupt
WPND MICROWIRE/PLUS interrupt pending
T0EN
T0PND
Timer T0 Interrupt Enable (Bit 12 toggle)
Timer T0 Interrupt pending
LPEN L Port Interrupt Enable (Multi-Input Wakeup/Inter-
rupt)
Bit 7 could be used as a flag
The Timer T0 supports the following functions:
■ Exit out of the Idle Mode (See Idle Mode description)
■ WATCHDOG logic (See WATCHDOG description)
■ Start up delay out of the ode
Unused LPEN T0PND T0EN µWPND WEN T1PNDB T1ENB
Bit 7
Bit 0
T2CNTRL Register (Address X'0xC6)
Figure 5 is a functional bram showing the structure
of the IDLE Timand its ciated errupt logic.
The T2CNTRL register contains the following bits:
Bits 11 through 1the ITregter can be selected for
triggering the IDLE Tier interrupt. Each time the selected
bit underfloery 4k, k, 6k, 32k or 64k instruction cy-
cles), the er interrupt pending bit T0PND is set, thus
eneratinterru(if enabled), and bit 6 of the Port G
daregisis resethus causing an exit from the IDLE
modf the dice in that mode.
T2ENB
Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture
edge
T2ENA
Timer T2 Interrupt Enable for Timer Underflow or
T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture
edge in mode 3)
order r an interrupt to be generated, the IDLE Timer in-
t enae bit T0EN must be set, and the GIE (Global In-
Enable) bit must also be set. The T0PND flag and
it are bits 5 and 4 of the ICNTRL register, respective-
e interrupt can be used for any purpose. Typically, it is
used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to the Power Save
Modes section.
T2C0
Timer T2 Start/Stop control in timer modes 1 an
2 Timer T2 Underflow Interrupt Pending Flag i
timer mode 3
Timer T2 mode control bit
Timer T2 mode control bit
T2C1
T2C2
T2C3
Timer T2 mode control bit
The Idle Timer period is selected by bits 0-2 of the ITMR reg-
ister Bits 3-7 of the ITMR Register are reserved and should
not be used as software flags.
T2C3 T2C2 T2C1 T2C0 T2PNDA T2EB T2ENB
Bit 7
Bit 0
T3CNTRL Register '0xB
Table 3 Idle Timer Window Length
The T3CNTRL regislowing bits:
T3ENB
Timer T3 or T3B Input capture
edge
Idle Timer Period
ITSEL2 ITSEL1 ITSEL0
(Instruction Cycles)
T3PNDB Timer T3 Inteng Flag for T3B capture
edge
T3ENA
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
4,096
8,192
Timer T3 Interrupt Enable for Timer Underflow or
T3A Input capture edge
T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA
in mode 1, T3 Underflow in mode 2, T3A capture
edge in mode 3)
16,384
32,768
65,536
T3C0
Timer T3 Start/Stop control in timer modes 1 and
2 Timer T3 Underflow Interrupt Pending Flag in
timer mode 3
T3C1
T3C2
T3C3
Timer T3 mode control bit
Timer T3 mode control bit
Timer T3 mode control bit
The ITMR register is cleared on Reset and the Idle Timer pe-
riod is reset to 4,096 instruction cycles.
ITMR Register (Address X'0xCF)
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
Bit 7 Bit 0
Reserved
ITSEL2 ITSEL1 ITSEL0
Bit 0
Bit 7
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13
0
10
15
tC
DOWN COUNTER (T0)
11 12 13 14
15
3
ITMR REGISTER
MUX
/
IDLE
INTERRUPT
(T0 OSCILLATOR CIRCUIT)
7
5
4
0
G6 DATA
REGISTER BIT
....... T0PND T0EN
.......
ICNTRL REGTER
RESET
MULTI-INPUT LO
INTERNBUS
Figure 5. Funtional Block gram for Idle Timer T0
Any time the IDLE Timer period is changed there is the pos-
sibility of generating a spurious IDLE Tirrupt by se
ting the T0PND bit. The user is dvable IDLE
Timer interrupts prior to changing the SEL bits
of the ITMR Register and ar the before at-
tempting to synchronithe IDimer.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to gener-
ate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will con-
tinuously generate the PWM signal completely independent of
the microcontroller. The user software services the timer block
only when the PWM parameters require updating.
TIMER T1, TIMER T3
The device has a setimer/counter blocks,
T1, T2, and T3. The ases and functioning of a
timer block are described ring to the timer block Tx.
Since the three timer blocks, T1, T2 and T3 are identical, all
comments are equally applicable to either of the three timer
blocks.
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from the
register RxA. Subsequent underflows cause the timer to be
reloaded from the registers alternately beginning with the
register RxB.
Each timer block consists of a 16-bit timer, Tx, and two sup-
porting 16-bit autoreload/capture registers, RxA and RxB.
Each timer block has two pins associated with it, TxA and TxB.
The pin TxA supports I/O required by the timer block, while the
pin TxB is an input to the timer block. The powerful and flexible
timer block allows the device to easily perform all timer func-
tions with minimal software overhead. The timer block has
three operating modes: Processor Independent PWM mode,
External Event Counter mode, and Input Capture mode.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 6 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output
pin. The underflows can also be programmed to generate in-
terrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control en-
able flags, TxENA and TxENB, allow the interrupts from the
The control bits TxC3, TxC2, and TxC1 allow selection of the
different modes of operation.
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14
TIMER
UNDERFLOW
INTERRUPT
16 BIT AUTO
RELOAD REGISTER
TIME 1
16 BIT AUTO
RELOAD REGISTER
ON TIME
TIMER
UNDERFLOW
INTERRUPT
EXT
CLK
DATA
LATCH
16 BIT TIMER/
COUNTER
16 BIT TIMER/
COUNTER
TxA
TxA
EDGE SELECTOR
LOGIC
tC
16 BIT AUTO
RELOAD REGISTER
TIME 2
16 BIT AUTO
RELOAD REGISTER
OFF TIME
Figure 6. Timer in PWM Mode
TO INTERRUPONTR
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer un-
derflow causes the RxA register to be reloaded into the timer.
Setting the timer enable flag TxENB will cause an interrupt
when a timer underflow causes the RxB register to be reload-
ed into the timer. Resetting the timer enable flags will disable
the associated interrupts.
TxB
Figumer n External Event Counter Mode
The mer vae gets copied over into the register when a trig-
ger eveoccurs on its corresponding pin. Control bits, TxC3,
2 and xC1, allow the trigger events to be specified ei-
a positive or a negative edge. The trigger condition for
put pin can be specified independently.
Either or both of the timer underflow interrupts may be en
abled. This gives the user the flexibility of interrupting onc
per PWM period on either the rising or falling edge of th
PWM output. Alternatively, the user may choose to ierrupt
on both edges of the PWM output.
igger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag TxE-
NA allows the interrupt on TxA to be either enabled or dis-
abled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts from
the TxB pin.
Mode 2. External Event Counter Mode
This mode is quite similar to the procindependen
PWM mode described above. The aiis that the
timer, Tx, is clocked by the input signpin. The
Tx timer control bits, TxC3and Txe timer to
be clocked either on a ative om the TxA
pin. Underflows from hed ino the TxPNDA
pending flag. Settinflag will cause an in-
terrupt when the tim
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when entering
the Input Capture mode. The timer underflow interrupt is en-
abled with the TxENA control flag. When a TxA interrupt oc-
curs in the Input Capture mode, the user must check both
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
In this mode the input e used as an indepen-
dent positive edge sensitive rupt input if the TxENB con-
trol flag is set. The occurrence of a positive edge on the TxB
input pin is latched into the TxPNDB flag.
Figure 7 shows a block diagram of the timer in External Event
Counter mode.
Note: The PWM output is not available in this mode since
the TxA pin is being used as the counter input clock.
Figure 8 shows a block diagram of the timer in Input Capture
mode.
Mode 3. Input Capture Mode
TIMER CONTROL FLAGS
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the in-
put capture mode.
The timers T1, T2 and T3 have identical control structures.
The control bits and their functions are summarized below.
TxC0
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode
3 (Input Capture)
In this mode, the timer Tx is constantly running at the fixed tc
rate. The two registers, RxA and RxB, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.
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15
tC
16 BIT TIMER
I
N
T
E
R
N
A
L
INT A
INPUT CAPTURE
REG RA
D
A
T
A
TxA
EDGE SELECTOR
LOGIC
B
U
S
INT B
INPUT CAPTURE
REG RB
TxB
EDECTO
IC
Figure 8. Timer in InpuCaptuMode
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
mer mode control
Timer mode control
Timer mode control
TxENA
TxENB
Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (TxC3, TxC2 and TxC1) are de-
tailed below:
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
TxC3 TxC2 TxC1
Ti
0
0
1
1
0
0
0
0
0
1
1
0
nal Event Counter)
nal Event Counter)
M) TxA Toggle
Timer Underflow
Timer Underflow
Autoreload RA
Autoreload RA
Pos. TxB Edge
Pos. TxB Edge
Autoreload RB
Autoreload RB
Pos. TxB Edge
TxA Pos. Edge
TxA Neg. Edge
tc
tc
tc
MO(PWM) No TxA Toggle
MODE 3 (Capture) Captures:
TxA Pos. Edge
TxB Pos. Edge
Pos. TxA Edge or
Timer Underflow
0
1
0
1
1
1
1
1
0
0
1
1
MODE 3 (Capture) Captures:
TxA Pos. Edge
TxB Neg. Edge
Pos. TxA Edge or
Timer Underflow
Neg. TxB Edge
Pos. TxB Edge
Neg. TxB Edge
tc
tc
tc
MODE 3 (Capture) Captures:
TxA Neg. Edge
TxB Pos. Edge
Neg. TxB Edge or
Timer Underflow
MODE 3 (Capture) Captures:
TxA Neg. Edge
Neg. TxA Edge or
Timer Underflow
TxB Neg. Edge
www.national.com
16
Power Save Modes
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
able mask option, the device cannot be placed in the HALT
mode (writing a “1” to the HALT flag will have no effect).
The WATCHDOG detector circuit is inhibited during the HALT
mode. However, the clock monitor circuit if enabled remains
active during HALT mode in order to ensure a clock monitor
error if the device inadvertently enters the HALT mode as a
result of a runaway program or power glitch.
HALT MODE
IDLE MODE
The device is placed in the HALT mode by writing a “1” to the
HALT flag (G7 data bit). All microcontroller activities, includ-
ing the clock, timers, and A/D converter, are stopped. The
WATCHDOG logic on the device is disabled during the HALT
mode. However, the clock monitor circuitry if enabled re-
mains active and will cause the WATCHDOG output pin (WD-
OUT) to go low. If the HALT mode is used and the user does
not want to activate the WDOUT pin, the Clock Monitor
should be disabled after the device comes out of reset (reset-
ting the Clock Monitor control bit with the first write to the
WDSVR register). In the HALT mode, the power require-
ments of the device are minimal and the applied voltage
(VCC) may be decreased to Vr (Vr = 2.0V) without altering the
state of the machine.
The device is placed in the IDLE mode by writing a “1” to the
IDLE flag (G6 data bit). In this mode, all activity, except the
associated on-board oscillator circuitry, the WATCHDOG log-
ic, the clock monitor and the IDLE Timer T0, is stopped. The
power supply requirements of the microcontroller in this
mode of operation are typically round 30% of normal power
requirement of the microc
As with the HALT mode, thce cabe returned to normal
operation with a rt, or wa Multi-put Wakeup from the
L Port.
The microcontroller maalso be awakened from the IDLE
mode afteble amnt of time up to 65,536 instruc-
tion cycle.536 milliseconds with a 1 MHz instruction
cck freqy.
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port. The second meth-
od is with a low to high transition on the CKO (G7) pin. This
method precludes the use of the crystal clock configuratio
(since CKO becomes a dedicated output), and so may b
used with an RC clock configuration. The third method of ex-
iting the HALT mode is by pulling the RESET pin w.
The LE timr peod is selectable from one of five values,
4k, 8k, 6k, 32k or 64k instruction cycles. Selection of this
e is me through the ITMR register.
er has the option of being interrupted with an under-
the selected bit of the IDLE Timer T0. This condition
hed into the T0PND pending flag. The interrupt can be
enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
Since a crystal or ceramic resonator may be selcted the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crysal oscand ceramc
resonators have a delayed start uimfull ampli-
tude and frequency stability. The IDLd to gen-
erate a fixed delay to et the os indeed
stabilized before alloexecu. In this case,
upon detecting a vaonly the oscillator cir-
cuitry is enabled. Taded with a value of
256 and is clocked won cycle clock. The tc
clock is derived by dividtor clock down by a fac-
tor of 10. The Schmitt triggewing the CKI inverter on the
chip ensures that the IDLE timer is clocked only when the os-
cillator has a sufficiently large amplitude to meet the Schmitt
trigger specifications. This Schmitt trigger is not part of the
oscillator closed loop. The start-up time-out from the IDLE
timer enables the clock signals to be routed to the rest of the
chip.
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the “Enter Idle
Mode” instruction.
Alternatively, the user can enter the IDLE mode with the IDLE
Timer T0 interrupt disabled. In this case, the device will re-
sume normal operation with the instruction immediately fol-
lowing the “Enter IDLE Mode” instruction.
The IDLE timer cannot be started or stopped under software
control, and it is not memory mapped, so it cannot be read or
written by the software. Its state upon Reset is unknown.
Therefore, if the device is put into the IDLE mode at an arbi-
trary time, it will stay in the IDLE mode for somewhere be-
tween 1 and the selected number of instruction cycles.
Upon reset the ITMR register is cleared and selects the
4,096 instruction cycle tap of the Idle Timer.
If an RC clock option is being used, the fixed delay is intro-
duced optionally. A control bit, CLKDLY, mapped as configu-
ration bit G7, controls whether the delay is to be introduced
or not. The delay is included if CLKDLY is set, and excluded
if CLKDLY is reset. The CLKDLY bit is cleared on reset.
Note: It is necessary to program two NOP instructions fol-
lowing both the set HALT mode and set IDLE mode instruc-
tions. These NOP instructions are necessary to allow clock
resynchronization following the HALT or IDLE modes.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature,
while the second mask option disables the HALT mode. With
the HALT mode enable mask option, the device will enter and
exit the HALT mode as described above. With the HALT dis-
For more information on the IDLE Timer and its associated
interrupt, see the description in the Timers Section.
www.national.com
17
to negative (high going low) for L Port bit 5, where bit 5 has
previously been enabled for an input interrupt. The program
would be as follows:
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
RBIT 5, WKEN
SBIT 5, WKEDG
RBIT 5, WKPND
SBIT 5, WKEN
Figure 9 shows the Multi-Input Wakeup logic.The Multi-Input
Wakeup feature utilizes the L Port. The user selects which
particular L port bit (or combination of L Port bits) will cause
the device to exit the HALT or IDLE modes. The selection is
done through the Reg: WKEN. The Reg: WKEN is an 8-bit
read/write register, which contains a control bit for every L
port bit. Setting a particular WKEN bit enables a Wakeup
from the associated L port pin.
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety
procedure should also be followed to avoid inherited pseudo
wakeup conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared.
The user can select whether the trigger condition on the se-
lected L Port pin is going to be either a positive edge (low to
high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a pseu-
do Wakeup condition as a result of the edge change. First,
the associated WKEN bit should be reset, followed by the
edge select change in WKEDG. Next, the associated WKP-
ND bit should be cleared, followed by the associated WKEN
bit being re-enabled.
This same procedure should be used following reset, since
the L port inputs are left floatis a result of reset.
The occurrence of the seger condition for Multi-In-
put Wakeup is lached into ding rgister called WKPND.
The respective bitf the WPND rester will be set on the
occurrence of the selcted triggdge on the corresponding
Port L pin. The user hathe responsibility of clearing these
pending flae WKPs a pending register for the oc-
currence ed wakeup conditions, the device will not
ter the mode any Wakeup bit is both enabled and
peing. Csequely, the user has the responsibility of
clearithe ping flags before attempting to enter the
ALT me.
An example may serve to clarify this procedure. Suppose w
wish to change the edge select from positive (low going hig
, WKPND and WKEDG are all read/write registers,
cleared at reset.
TERNL DATA BUS
TO
INTERRUPT
LOGIC
S
IDLE
S
..........................
WKEN
7
0
HALT
R
Q
R
Q
LPEN
BIT
L0
0
STOP
L7
7
CKI
CKT
OSC
CK0
0 = low going high
1 = high going low
↑
↓
WKPND
CHIP CLOCK
WKEDG
R
S
IDLE
Q
TIMER
STOP
Figure 9. Multi-Input Wake Up Logic
www.national.com
18
A/D Converter
Bit 7
Bit 6
Bit 5
Channel No.
The device contains an 8-channel, multiplexed input, succes-
sive approximation, Analog-to-Digital convertor. The device’s
VCC and GND pins are used for voltage reference.
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
3
4
5
6
7
OPERATING MODES
The A/D convertor supports ratiometric measurements. It
supports both Single Ended and Differential modes of oper-
ation.
Differential mode:
Bit 7
Bit 6
Bit 5
Channel Pairs (+. -)
Four specific analog channel selection modes are supported.
These are as follows:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0, 1
1, 0
2, 3
3, 2
4, 5
5, 4
6, 7
7, 6
Allow any specific channel to be selected at one time. The
A/D convertor performs the specific conversion requested
and stops.
Allow any specific channel to be scanned continuously. In
other words, the user specifies the channel and the A/D con-
vertor scans it continuously. At any arbitrary time the user
can immediately read the result of the last conversion. The
user must wait for only the first conversion to complete.
MODE SELECT
Allow any differential channel pair to be selected at one time.
The A/D convertor performs the specific differential conver-
sion requested and stops.
This 2-bit field is used to elect the mode of operation (single
conversioous conersions, differential, single end-
ed) as shhe folowing table.
Allow any differential channel pair to be scanned continuous-
ly. In other words, the user specifies the differential channel
pair and the A/D convertor scans it continuously. At any arbi-
trary time the user can immediately read the result of the last
differential conversion. The user must wait for only the firs
conversion to complete.
it 4
Bit 3
Mode
0
0
Single Ended mode, single conver-
sion
1
Single Ended mode, continuous scan
of a single channel into the result reg-
ister
The A/D convertor is supported by two memory mapped reg
isters, the result register and the mode control regier. When
the device is reset, the mode control registe(ENAD)
cleared, the A/D is powered down and the A/D relgister
has unknown data.
1
1
0
1
Differential mode, single conversion
Differential mode, continuous scan of
a channel pair into the result register
PRESCALER SELECT
A/D Control Register
This 2-bit field is used to select one of the four prescaler
clocks for the A/D converter. The following table shows the
various prescaler options.
The ENAD control register contains 3 el selec-
tion, 2 bits for prescale2 bits selection
and a Busy bit. An Ainitiatby setting the
ADBSY bit in the Eer. The result of the
conversion is availae A/D result register,
ADRSLT, when ADBShe hardware on com-
pletion of the conversio
A/D Convertor Clock Prescale
Bit 2
Bit 1
Clock Select
0
0
1
1
0
1
0
1
Divide by 2
Divide by 4
Divide by 6
Divide by 12
ENAD (Address 0xCB)
CHANNEL
SELECT
MODE
SELECT
PRESCALER BUSY
SELECT
ADCH2 ADCH1 ADCH0 ADMOD1 ADMOD0 PSC1 PSC0 ADBSY
BUSY BIT
Bit 7
Bit 0
The ADBSY bit of the ENAD register is used to control start-
ing and stopping of the A/D conversion. When ADBSY is
cleared, the prescale logic is disabled and the A/D clock is
turned off. Setting the ADBSY bit starts the A/D clock and ini-
tiates a conversion based on the mode select value currently
in the ENAD register. Normal completion of an A/D conver-
sion clears the ADBSY bit and turns off the A/D convertor.
CHANNEL SELECT
This 3-bit field selects one of eight channels to be the VIN+
The mode selection determines the VIN- input.
.
Single Ended mode:
Bit 7
Bit 6
Bit 5
Channel No.
The ADBSY bit remains a one during continuous conversion.
The user can stop continuous conversion by writing a zero to
the ADBSY bit.
0
0
0
0
0
1
0
1
0
0
1
2
www.national.com
19
within the specified range. The maximum A/D frequency is
1.67 MHz. This equates to a 600 ns A/D clock cycle.
If the user wishes to restart a conversion which is already in
progress, this can be accomplished only by writing a zero to
the ADBSY bit to stop the current conversion and then by
writing a one to ADBSY to start a new conversion. This can
be done in two consecutive instructions.
The A/D convertor takes 17 A/D clock cycles to complete a
conversion. Thus the minimum A/D conversion time for the
device is 10.2 µs when a prescaler of 6 has been selected.
The 17 A/D clock cycles needed for conversion consist of 1
cycle at the beginning for reset, 7 cycles for sampling, 8 cy-
cles for converting, and 1 cycle for loading the result into the
A/D result register (ADRSLT). This A/D result register is a
read-only register. The user cannot write into ADRSLT.
ADC Operation
The A/D convertor interface works as follows. Setting the
ADBSY bit in the A/D control register ENAD initiates an A/D
conversion. The conversion sequence starts at the beginning
of the write to ENAD operation which sets ADBSY, thus pow-
ering up the A/D. At the first falling edge of the convertor
clock following the write operation, the sample signal turns
on for seven clock cycles. If the A/D is in single conversion
mode, the conversion complete signal from the A/D will gen-
erate a power down for the A/D convertor and will clear the
ADBSY bit in the ENAD register at the next instruction cycle
boundary. If the A/D is in continuous mode, the conversion
complete signal will restart the conversion sequence by de-
selecting the A/D for one convertor clock cycle before start-
ing the next sample. The A/D 8-bit result is immediately
loaded into the A/D result register (ADRSLT) upon comple-
tion. Internal logic prevents transient data (resulting from the
A/D writing a new result over an old one) being read from
ADRSLT.
The ADBSY flag provides an A/D clock inhibit function, which
saves power by powering down the A/D when it is not in use.
Note: The A/D convertor is also powered down when the de-
vice is in either the HALT or IDLE modes. If the A/D is running
when the device enters the HALT or IDLE modes, the A/D
powers down and then restarts the conversion with a corrupt-
ed sampled voltage (and thalid result) when the de-
vice comes out of the HAE modes.
Analog Input anSurce sistanConsiderations
Figure 10 shows the /D pin mel in single ended mode.
The differential mode haa similar A/D pin model. The leads
to the analshould kept as short as possible. Both
noise and ock coupling to an A/D input can cause con-
vsion eThe clck lead should be kept away from the
anag inpuine to duce coupling. The A/D channel input
pins dnot have any internal output driver circuitry connected
hem bause this circuitry would load the analog input sig-
ue to utput buffer leakage current.
Inadvertent changes to the ENAD register during conversion
are prevented by the control logic of the A/D. Any attempt to
write any bit of the ENAD Register except ADBSY, while
ADBSY is a one, is ignored. ADBSY must be cleared either
by completion of an A/D conversion or by the user before th
prescaler, conversion mode or channel select values can b
changed. After stopping the current conversion, the user can
load different values for the prescaler, conversiomode or
channel select and start a new conversion in onnstruc
impedances greater than 3 kΩ on the analog input
ill adversely affect the internal RC charging time during
ut sampling. As shown in Figure 10, the analog switch to
the DAC array is closed only during the 7 A/D cycle sample
time. Large source impedances on the analog inputs may re-
sult in the DAC array not being charged to the correct voltage
levels, causing scale errors.
It is important for the user to realize that, when used in differ-
ential mode, only the positive inut to tconverter
sampled and held. The negative inut connect-
ed and should be held stable for the conver-
sion. Failure to maintain negatil result in
incorrect conversion.
If large source resistance is necessary, the recommended so-
lution is to slow down the A/D clock speed in proportion to the
source resistance. The A/D convertor may be operated at the
maximum speed for RS less than 3 kΩ . For RS greater than 3
kΩ , A/D clock speed needs to be reduced. For example, with
RS = 6 kΩ , the A/D convertor may be operated at half the
maximum speed. A/D convertor clock speed may be slowed
down by either increasing the A/D prescaler divide-by or de-
creasing the CKI clock frequency. The A/D minimum clock
speed is 100 kHz.
PRESCALER
The A/D Convertor (scaler option that al-
lows four different cloce A/D clock frequency
is equal to CKI divided bcaler value. Note that the
prescaler value must be chosen such that the A/D clock falls
V
V
CC
CC
<2 µA
JUNCTION
LEAKAGE
V
- 15V
+ 0.5V
CC
V
ANALOG
INPUT
PIN
CC
+15V - GND
GND - 0.5V
*
<25 pF
DAC
ARRAY
4.5k
<2 µA
JUNCTION
LEAKAGE
7 pf
INPUT
PROTECTION
DEVICE
AGND
GND
*The analog switch is closed only during the sample time.
Figure 10. A/D Pin Model (Single Ended Mode)
www.national.com
20
Interrupts
Figure 11 shows the Interrupt block diagram.
Introduction
The device supports fourteen vectored interrupts. Interrupt
sources include Timer 1, Timer 2, Timer 3, Timer T0, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, UART and Ex-
ternal Input.
Maskable Interrupts
All interrupts other than the Software Trap are maskable.
Each maskable interrupt has an associated enable bit and
pending flag bit. The pending bit is set to 1 when the interrupt
condition occurs. The state of the interrupt enable bit, com-
bined with the GIE bit determines whether an active pending
flag actually triggers an interrupt. All of the maskable inter-
rupt pending and enable bits are contained in mapped con-
trol registers, and thus can be controlled by the software.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the ap-
propriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 13 maskable inputs has a fixed arbitration rank-
ing and vector.
SOFTWARE TRAP
PEDING FLG
EXTERNAL
IDLE TIMER
TIMER T1
MICROWIRE/PLUS
FUTURE
TIMER T2 AND T3
MULTI-INPUT WAKE UP
INTERRUPT ENABLE
GIE
Figure 11. COP888GD Interrupt Block Diagram
www.national.com
21
A maskable interrupt condition triggers an interrupt under the
following conditions:
Within a specific interrupt service routine, the associated
pending bit should be cleared. This is typically done as early
as possible in the service routine in order to avoid missing the
next occurrence of the same type of interrupt event. Thus, if
the same event occurs a second time, even while the first oc-
currence is still being serviced, the second occurrence will be
serviced immediately upon return from the current interrupt
routine.
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt.
(If a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is
completed.)
An interrupt service routine typically ends with an RETI in-
struction. This instruction set the GIE bit back to 1, pops the
address stored on the stack, and restores that address to the
program counter. Program execution then proceeds with the
next instruction that would have been executed had there
been no interrupt. If there are any valid interrupts pending,
the highest-priority interrupt is serviced immediately upon re-
turn from the previous interrupt.
An interrupt is triggered only when all of these conditions are
met at the beginning of an instruction. If different maskable
interrupts meet these conditions simultaneously, the high-
est-priority interrupt will be serviced first, and the other pend-
ing interrupts must wait.
Upon Reset, all pending bits, individual enable bits, and the
GIE bit are reset to zero. Thus, a maskable interrupt condi-
tion cannot trigger an interrupt until the program enables it by
setting both the GIE bit and the individual enable bit. When
enabling an interrupt, the user should consider whether or
not a previously activated (set) pending bit should be ac-
knowledged. If, at the time an interrupt is enabled, any previ-
ous occurrences of the interrupt should be ignored, the
associated pending bit must be reset to zero prior to enabling
the interrupt. Otherwise, the interrupt may be simply enabled;
if the pending bit is already set, it will immediately trigger an
interrupt. A maskable interrupt is active if its associated en-
able and pending bits are set.
VIS Instruction
The general interrupt servtine, hich starts at address
00FF Hex, must bcpable handlinall types of interrupts.
The VIS instruction, ogether h n interrupt vector table,
directs the device to tspecific interrupt handling routine
based on the of the ntrrupt.
VIS is a ste intruction, typically used at the very be-
gning ogenerinterrupt service routine at address
00FHex, shortly after that point, just after the code used
for conxt switching. The VIS instruction determines which
bled d pending interrupt has the highest priority, and
s an indirect jump to the address corresponding to that
t source. The jump addresses (vectors) for all possi-
rrupts sources are stored in a vector table.
An interrupt is an asychronous event which may occur be-
fore, during, or after an instruction cycle. Any interrupt whic
occurs during the execution of an instruction is not acknow
edged until the start of the next normally executed instructio
is to be skipped, the skip is performed before the pedng in-
terrupt is acknowledged.
e vector table may be as long as 32 bytes (maximum of 16
vectors) and resides at the top of the 256-byte block contain-
ing the VIS instruction. However, if the VIS instruction is at
the very top of a 256-byte block (such as at 00FF Hex), the
vector table resides at the top of the next 256-byte block.
Thus, if the VIS instruction is located somewhere between
00FF and 01DF Hex (the usual case), the vector table is lo-
cated between addresses 01E0 and 01FF Hex. If the VIS in-
struction is located between 01FF and 02DF Hex, then the
vector table is located between addresses 02E0 and 02FF
Hex, and so on.
At the start of interrupt acknowledgment, the fong ac-
tions occur:
1. The GIE bit is automatically ret tenting any
subsequent maskable interrupt frg the cur-
rent service routine.ure premaskable
interrupt from inter one g serviced.
2. The address of out to be executed is
pushed onto th
3. The program cded with 00FF Hex,
causing a jump to emory location.
Each vector is 15 bits long and points to the beginning of a
specific interrupt service routine somewhere in the 32-Kbyte
memory space. Each vector occupies two bytes of the vector
table, with the higher-order byte at the lower address. The
vectors are arranged in order of interrupt priority. The vector
of the maskable interrupt with the lowest rank is located to
0yE0 (higher-order byte) and 0yE1 (lower-order byte). The
next priority interrupt is located at 0yE2 and 0yE3, and so
forth in increasing rank. The Software Trap has the highest
rand and its vector is always located at 0yFE and 0yFF. The
number of interrupts which can become active defines the
size of the table.
The device requires seven instruction cycles to perform the
actions listed above.
If the user wishes to allow nested interrupts, the interrupts
service routine may set the GIE bit to 1 by writing to the PSW
register, and thus allow other maskable interrupts to interrupt
the current service routine. If nested interrupts are allowed,
caution must be exercised. The user must write the program
in such a was as to prevent stack overflow, loss of saved con-
text information, and other unwanted conditions.
The interrupt service routine stored at location 00FF Hex
should use the VIS instruction to determine the cause of the
interrupt, and jump to the interrupt handling routine corre-
sponding to the highest priority enabled and active interrupt.
Alternately, the user may choose to poll all interrupt pending
and enable bits to determine the source(s) of the interrupt. If
more than one interrupt is active, the user’s program must
decide which interrupt to service.
Table 4 shows the types of interrupts, the interrupt arbitration
ranking, and the locations of the corresponding vectors in the
vector table.
The vector table should be filled by the user with the memory
locations of the specific interrupt service routines. For exam-
ple, if the Software Trap routine is located at 0310 Hex, then
www.national.com
22
the vector location 0yFE and -0yFF should contain the data
03 and 10 Hex, respectively. When a Software Trap interrupt
occurs and the VIS instruction is executed, the program
jumps to the address specified in the vector table.
terrupt service routine can be terminated by returning to the
VIS instruction. In this case, interrupts will be serviced in turn
until no further interrupts are pending and the default VIS
routine is started. After testing the GIE bit to ensure that
ex4ecution is not erroneous, the routine should restore the
program context and execute the RETI to return to the inter-
rupted program.
The interrupt sources in the vector table are listed in order of
rank, from highest to lowest priority. If two or more enabled
and pending interrupts are detected at the same time, the
one with the highest priority is serviced first. Upon return
from the interrupt service routine, the next highest-level
pending interrupt is serviced.
This technique can save up to fifty instruction cycles (tc), or
more, (50 s at 10 MHz oscillator) of latency for pending inter-
rupts with a penalty of fewer than ten instruction cycles if no
further interrupts are pending.
If the VIS instruction is executed, but no interrupts are en-
abled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in
the vector table. This is an unusual occurrence and may be
the result of an error. It can legitimately result from a change
in the enable bits or pending flags prior to the execution of the
VIS instruction, such as executing a single cycle instruction
which clears an enable flag at the same time that the pending
flag is set. It can also result, however, from inadvertent exe-
cution of the VIS command outside of the context of an inter-
rupt.
To ensure reliable operation, the user should always use the
VIS instruction to determine the source of an interrupt. Al-
though it is possible to poll the pending bits to detect the
source of an interrupt, this practice is not recommended. The
use of polling allows the standard arbitration ranking to be al-
tered, but the reliability of rrupt system is compro-
mised. The polling routindividually test the enable
and pending bitof each able ierrupt. If a Software
Trap interrupt shd occit will e serviced last, even
though it should havthe highiority. Under certain con-
ditions, a Software Trap ould be triggered but not serviced,
resulting in vertent king out” of all maskable inter-
rupts by are Trap pending flag. Problems such as
ts can bided busing VIS instruction.
The default VIS interrupt vector can be useful for applications
in which time critical interrupts can occur during the servicing
of another interrupt. Rather than restoring the program con-
text (A, B, X, etc.) and executing the RETI instruction, an in-
Table 4 Intr Table
ARBITRATION
RANKING
VECTOR* ADDRESS
PTION
SOURCE
Software
(Hi-Low Byte)
(1) Highest
(2)
INR Instruction
0yFE - 0yFF
0yFC - 0yFD
0yFA - 0yFB
0yF8 - 0yF9
0yF6 - 0yF7
0yF4 - 0yF5
0yF2 - 0yF3
0yF0 - 0yF1
0yEE - 0yEF
0yEC - 0yED
0yEA - 0yEB
0yE8 - 0yE9
0yE6 - 0yE7
0yE4 - 0yE5
0yE2 - 0yE3
0yE0 - 0yE1
Reserved
xte
Tim
imer
er T1
(3)
Pin G0 Edge
Underflow
T1A/Underflow
T1B
(4)
(5)
(6)
(7)
ROWIRE/PLUS Busy Low
erved
(8)
(9)
Reserved
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
Reserved
Timer T2
Timer T2
Timer T3
Timer T3
Port L/Wakeup
Default
T2A/Underflow
T2B
T3A/Underflow
T3B
Port L Edge
VIS instr. Execution
without Any Interrupts
* The location of the vector table depends on the location of the VIS instruction. Vector addresses shown in
the table assume a VIS instruction between 00FF and 01DF Hex
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23
VIS Execution
the active interrupt with the highest arbitration ranking. This
vector is read from program memory and placed into the PC
which is now pointed to the 1st instruction of the service rou-
tine of the active interrupt with the highest arbitration ranking.
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the ex-
ternal interrupt is active and the software trap interrupt is not,
then FA is generated and so forth. If the only active interrupt
is software trap, than E0 is generated. This number replaces
the lower byte of the PC. The upper byte of the PC remains
unchanged. The new PC is therefore pointing to the vector of
Figure 12 illustrates the different steps performed by the VIS
instruction. Figure 13 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
0FF
VIS
INTERRUPT
Vector taocatein the
me 256 te page
aC
after an interrupt
ABRITRATION LOGIC
(generates an even number
between E0 and FE)
Interrupt
Vector
Table
VIS
PC
HIG
OW
STARTING
ADDRESS
BIT 7:0
PC
STARTING ADDRESS
INTEVICE
LOW
HIGH
RORAM MEMORY
Figure 12. VIS Operation
JUMP TO VECTOR AT 0yFE/0yFF
EXTERNAL
INTERRUPT
ACTIVE?
JUMP TO VECTOR AT 0yFA/0yFB
JUMP TO VECTOR AT 0yE2/0yE3
PORT L/
WAKEUP
INTERRUPT
ACTIVE?
JUMP TO VECTOR AT 0yE0/0yE1
END
Figure 13. VIS Flow Chart
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24
Programming Example: External Interrupt
PSW
CNTRL
RBIT
RBIT
SBIT
SBIT
SBIT
JP
=00EF
=00EE
0,PORTGC
0,PORTGD
; G0 pin configured Hi-Z
IEDG, CNTRL ; Ext interrupt polarity: falling edge
GIE, PSW
EXEN, PSW
WAIT
; Set the GIE bit
; Enable the external interrupt
; Wait for external interrupt
WAIT:
.
.
.
.=0FF
VIS
; The interrupt auses a
; bddresFF
; S caues a branch to
; intept vctor table
.
.
.
.=01FA
; Vector table (within 256 byte
; of VIS inst.) containing the ext
; interrupt service routine
.ADDRW SERVIE
.
.
S
; Interrupt Service Routine
; Reset ext interrupt pend. bit
XPND, PSW
.
.
RET
; Return, set the GIE bit
www.national.com
25
Non-maskable Interrupt
Pending Flag
wrong state. This will allow maskable interrupts to be acknowl-
edged during the servicing of the first Software Trap. To avoid
problems such as this, the user program should contain the
Software Trap routine to perform a recovery procedure rather
than a return to normal execution.
There is a pending flag bit associated with the non-maskable in-
terrupt, called STPND. This pending flag is not memo-
ry-mapped and cannot be accessed directly by the software.
Under normal conditions, the STPND flag is reset by a RPND
instruction in the Software Trap service routine. If a program-
ming error or hardware condition (brownout, power supply
glitch, etc.) sets the STPND flag without providing a way for it to
be cleared, all other interrupts will be locked out. To alleviate this
condition, the user can use extra RPND instructions in the main
program and in the Watchdog service routine (if present). There
is no harm in executing extra RPND instructions in these parts
of the program.
The pending flag is reset to zero when a device Reset occurs.
When the non-maskable interrupt occurs, the associated pend-
ing bit is set to 1. The interrupt service routine should contain an
RPND instruction to reset the pending flag to zero. The RPND
instruction always resets the STPND flag
Software Trap
The Software Trap is a special kind of non-maskable interrupt
which occurs when the INTR instruction (used to acknowledge
interrupts) is fetched from program memory and placed in the
instruction register. This can happen in a variety of ways, usually
because of an error condition. Some examples of causes are
listed below.
Port L Interrupts
Port L provides the user with an ditional eight fully selectable,
edge sensitive interrupts wll vectored into the same
service subroutine.
If the program counter incorrectly points to a memory location
beyond the available program memory space, the non-existent
or unused memory location returns zeros which is interpreted
as the INTR instruction.
The interrupt from t L shalogic wh the wake up circuitry.
The register WKEN aws interfrom Port L to be individu-
ally enabled or disabled. he register WKEDG specifies the trig-
ger conditioither a tive or a negative edge. Finally,
the registD latches in the pending trigger conditions.
If the stack is popped beyond the allowed limit (address 02F or
06F Hex), a Software Trap is triggered.
TGIE (al Interrpt Enable) bit enables the interrupt func-
tion.
A Software Trap can be triggered by a temporary hardware con-
dition such as a brownout or power supply glitch.
A controflag, LPEN, functions as a global interrupt enable for
L intepts. Setting the LPEN flag will enable interrupts
e versa. A separate global pending flag is not needed
e register WKPND is adequate.
The Software Trap has the highest priority of all interrupts
When a Software Trap occurs, the STPND bit is set. The GIE
is not affected and the pending bit (not accessible by the use
is used to inhibit other interrupts and to direct the progrto the
ST service routine with the VIS instruction. Nothincan inter-
rupt a Software Trap service routine except for anoter Sware
Trap. The STPND can be reset only by the RPND instruction or
a chip Reset.
Port L is also used for waking the device out of the HALT
or IDLE modes, the user can elect to exit the HALT or IDLE
modes either with or without the interrupt enabled. If he elects
to disable the interrupt, then the device will restart execution
from the instruction immediately following the instruction that
placed the microcontroller in the HALT or IDLE modes. In the
other case, the device will first execute the interrupt service rou-
tine and then revert to normal operation. (See HALT MODE for
clock option wakeup information.)
The Software Trap indicates an unusl error con-
dition. Generally, returning to normal the point
where the Software Trcannone reliably.
Therefore, the Softwautine suld re-initialize
the stack pointer aovery procedure that
re-starts the software nt, similar to a device
Reset, but not necessathe same functions as
a device Reset. The rouo execute the RPND in-
struction to reset the STPND flag. Otherwise, all other interrupts
will be locked out. To the extent possible, the interrupt routine
should record or indicate the context of the device so that the
cause of the Software Trap can be determined.
Interrupt Summary
The device uses the following types of interrupts, listed below in
order of priority:
1. The Software Trap non-maskable interrupt, triggered by
the INTR (00 opcode) instruction. The Software Trap is ac-
knowledged immediately. This interrupt service routine can
be interrupted only by another Software Trap. The Software
Trap should end with two RPND instructions followed by a
re-start procedure.
2. Maskable interrupts, triggered by an on-chip peripheral
block or an external device connected to the device. Under
ordinary conditions, a maskable interrupt will not interrupt
any other interrupt routine in progress. A maskable inter-
rupt routine in progress can be interrupted by the
non-maskable interrupt request. A maskable interrupt rou-
tine should end with an RETI instruction or should return to
execute the VIS instruction. This is particularly useful when
exiting long interrupt service routines if the time between
interrupts is short. In this case the RETI instruction would
only be executed when the default VIS routine is reached.
If the user wishes to return to normal execution from the point at
which the Software Trap was triggered, the user must first exe-
cute RPND, followed by RETSK rather tan RETI or RET. This is
because the return address stored on the stack is the address
of the INTR instruction that triggered the interrupt. The program
must skip that instruction in order to proceed with the next one.
Otherwise, an infinite loop of Software Traps and returns will oc-
cur.
Programming a return to normal execution requires careful con-
sideration. If the Software Trap routine is interrupted by another
Software Trap, the RPND instruction in the service routine for
the second Software Trap will reset the STPND flag; upon return
to the first Software Trap routine, the STPND flag will have the
www.national.com
26
not to reject the clock if the instruction cycle clock (1/tc) is greater
or equal to 10 kHz. This equates to a clock input rate on CKI of
greater or equal to 100 kHz.
WATCHDOG/Clock Monitor
The devices contain a user selectable WATCHDOG and clock
monitor. The following section is applicable only if WATCHDOG
feature has been selected in the ECON register. The WATCH-
DOG is designed to detect the user program getting stuck in in-
finite loops resulting in loss of program control or “runaway”
programs.
WATCHDOG/Clock Monitor Operation
The WATCHDOG is enabled by bit 2 of the ECON register.
When this ECON bit is 0, the WATCHDOG is enabled and pin
G1 becomes the WATCHDOG output with a weak pullup.
The WATCHDOG logic contains two separate service windows.
While the user programmable upper window selects the Watch-
dog service time, the lower widow provides protection against
an infinite program loop that contains the watchdog service in-
struction.
The WATCHDOG and Clock Monitor are disabled during reset.
The device comes out of reset with the WATCHDOG armed, the
WATCHDOG Window Select bits (bits 6, 7 of the WDSVR
Register) set, and the Clock Monitor bit (bit 0 of the WDSVR
Register) enabled. Thus, a Clock Monitor error will occur after
coming out of reset, if the instruction cycle clock frequency has
not reached a minimum specified value, including the case
where the oscillator fails to start.
The COP8SGR7 devices provide the added feature of a soft-
ware trap that provides protection against stack overpops and
addressing locations outside valid user program space.
The WDSVR register can be only once after reset and
the key data (bits 5 throuhe WDSVR Register) must
match to be a vad write. Trite to e WDSVR register in-
volves two irrevocachoice(i) the election of the WATCH-
DOG service window ii) enabling or disabling of the Clock
Monitor. Hence, the first ite to WDSVR Register involves se-
lecting or g the Cck Monitor, select the WATCH-
DOG serdow and match the WATCHDOG key data.
Sbsequeites to te WDSVR register will compare the val-
ue bng wrin by thuser to the WATCHDOG service window
value ad the key data (bits 7 through 1) in the WDSVR Regis-
Table shows the sequence of events that can occur.
The Clock Monitor is used to detect the absence of a clock or a
very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks: WD
UPPER and WD LOWER. WD UPPER establishes the upper
limit on the service window and WD LOWER defines the lower
limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to
a WATCHDOG Service Register named WDSVR which is
memory mapped in the RAM. This value is composed of three
fields, consisting of a 2-bit Window Select, a 5-bit Key Data field,
and the 1-bit Clock Monitor Select field. Table 5 shows the
WDSVR register.
er must service the WATCHDOG at least once before the
mit of the service window expires. The WATCHDOG
ot be serviced more than once in every lower limit of the
srvice window.
Table 5 WATCHDOG Service Register
Window
Select
lock
Monito
Key Data
The WATCHDOG has an output pin associated with it. This is
the WDOUT pin, on pin 1 of the port G. WDOUT is active low.
The WDOUT pin has a weak pullup in the inactive state. Upon
triggering the WATCHDOG, the logic will pull the WDOUT (G1)
pin low for an additional 16 tc–32 tc cycles after the signal level
on WDOUT pin goes below the lower Schmitt trigger threshold.
After this delay, the device will stop forcing the WDOUT output
low.The WATCHDOG service window will restart when the WD-
OUT pin goes high.
X
X
6
0
5
1
1
3
0
0
Y
0
7
4
2
The lower limit of the service window is struction
cycles. Bits 7 and 6 of the gister ser to pick
an upper limit of the s
Table 6 shows the fotions of lower and up-
per limits for the WATndow. This flexibility in
choosing the WATCHDow prevents any undue
burden on the user softwa
A WATCHDOG service while the WDOUT signal is active will be
ignored. The state of the WDOUT pin is not guaranteed on re-
set, but if it powers up low then the WATCHDOG will time out
and WDOUT will go high.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit
Key Data field. The key data is fixed at 01100. Bit 0 of the WDS-
VR Register is the Clock Monitor Select bit.
The Clock Monitor forces the G1 pin low upon detecting a clock
frequency error. The Clock Monitor error will continue until the
clock frequency has reached the minimum specified value, after
which the G1 output will go high following 16 tc–32 tc clock cy-
cles. The Clock Monitor generates a continual Clock Monitor er-
ror if the oscillator fails to start, or fails to reach the minimum
specified frequency. The specification for the Clock Monitor is as
follows:
Table 6 WATCHDOG Service Window Select
WDSVR
Bit 7
WDSVR
Bit 6
Service Window
(Lower-Upper Limits)
0
0
1
1
0
1
0
1
2048–8k tc Cycles
2048–16k tc Cycles
2048–32k tc Cycles
2048–64k tc Cycles
1/tc > 10 kHz—No clock rejection.
1/tc < 10 Hz—Guaranteed clock rejection.
WATCHDOG And Clock Monitor Summary
Clock Monitor
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
The Clock Monitor aboard the device can be selected or dese-
lected under program control. The Clock Monitor is guaranteed
www.national.com
27
■ Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.
■ Following RESET, the WATCHDOG and CLOCK MONI-
TOR are both enabled, with the WATCHDOG having he
maximum service window selected.
■ A hardware WATCHDOG service occurs just as the de-
vice exits the IDLE mode. Consequently, the WATCHDOG
should not be serviced for at least 2048 instruction cycles
following IDLE, but must be serviced within the selected
window to avoid a WATCHDOG error.
■ The WATCHDOG service window and CLOCK MONITOR
enable/disable option can only be changed once, during
the initial WATCHDOG service following RESET.
■ The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in or-
der to avoid a WATCHDOG error.
■ Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG er-
rors.
■ The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0's.
■ Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR en-
able/disable must be selected) may be programmed any-
where within the maximum service window (65,536
instruction cycles) initialized by RESET. Note that this ini-
tial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a WATCH-
DOG error.
Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs,
■ The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
Reading of undefined ROzeroThe opcode for soft-
ware interrupt is 0. f the gram fehes instructions from
undefined ROM, tiwill forca sofware interrupt, thus sig-
naling that an illegal cdition has occurred.
■ The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode will be detected as
a CLOCK MONITOR error (provided that the CLOCK
MONITOR enable option has been selected by the pro-
gram).
■ With the single-pin R/C oscillator option selected and the
CLKDLY bit reset, the WATCHDOG service window will
resume following HALT mode from where it left off before
entering the HALT mode.
■ With the crystal oscillator option selected, or with the si
gle-pin R/C oscillator option selected and the CLKDLY bi
set, the WATCHDOG service window will be seto its se-
lected value from WDSVR following HALT. Cnseque
the WATCHDOG should not be serviced for at 2048
instruction cycles following HALT, but must be serviced
within the selected window to oid DOG or.
■ The IDLE timer T0 is not initializeRESET.
■ The user can sync in to the IDLE with an
IDLE counter (T0) iy monhe T0PND
flag. The T0PND er the elfth bit of the
IDLE counter togstruction cycles). The
user is responsibT0PND flag.
The subrok growwn for each call (jump to sub-
routine), or PUSH, and grows up for each return or
OP. The pointis initialized to RAM location 06F Hex
durg resConseuently, if there are more returns than
calls, e stack inter will point to addresses 070 and 071
ex (whh are undefined RAM). Undefined RAM from ad-
es 07to 07F (Segment 0), and all other segments
gments 4... etc.) is read as all 1's, which in turn will
he program to return to address 7FFF Hex. This is an
fined ROM location and the instruction fetched (all 0's)
from this location will generate a software interrupt signaling
an illegal condition.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM
2. Over “POP”ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restart-
ing (this recovery program is probably similar to that following
reset, but might not contain the same program initialization
procedures). The recovery program should reset the soft-
ware interrupt pending bit using the RPND instruction.
Table 7 WATCHDOG Service Actions
Window Data Clock Monitor
Key Data
Action
Match
Match
Match
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Don't Care
Mismatch
Don't Care
Mismatch
Don't Care
Don't Care
Don't Care
Don't Care
Mismatch
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28
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the de-
vice to interface with any of National Semiconductor's MI-
CROWIRE peripherals (i.e. A/D converters, display drivers,
E2PROMs etc.) and with other microcontrollers which sup-
port the MICROWIRE interface. It consists of an 8-bit serial
shift register (SIO) with serial data input (SI), serial data out-
put (SO) and serial shift clock (SK). Figure 14 shows a block
diagram of the MICROWIRE/PLUS logic.
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 15 shows how
two microcontroller devices and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
Warning:
The SIO register should only be loaded when the SK clock is
low. Loading the SIO register while the SK clock is high will
result in undefined data in the SIO register. SK clock is nor-
mally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.
I
BUSY
FLAG
INTERRUPT
SO
N
T
E
R
N
A
L
MICROWIRE/PLUS Mastode Operation
MSB
LSB
In the MICROWIRE/PLUS mode of operation the shift
clock (SK) is geerated inlly. ThMICROWIRE Master
always initiates alta excnges. Te MSEL bit in the CN-
TRL register must be et to enable the SO and SK functions
onto the G Port. The SO and SK pins must also be selected
as outputs approate bits in the Port G configura-
tion regise 9 summarizes the bit settings required for
Mster mf operon.
8 BIT SIO
REGISTER
SI
SHIFT CLOCK
D
A
T
A
CLOCK
SELECT
tC
SK
B
U
S
CNTRL
MICOWIRPUS Slave Mode Operation
he MIROWIRE/PLUS Slave mode of operation the SK
s genrated by an external source. Setting the MSEL
e CNTRL register enables the SO and SK functions
e G Port. The SK pin must be selected as an input and
O pin is selected as an output pin by setting and reset-
ting the appropriate bit in the Port G configuration register.
Table V summarizes the settings required to enter the Slave
mode of operation.
Figure 14. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal sourc
or an external source. Operating the MICROWIRE/S ar-
rangement with the internal clock source is called the Master
mode of operation. Similarly, operating the MICOW-
IRE/PLUS arrangement with an external shift clock is called
the Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be repeated.
The CNTRL register is used to confiol the MI-
CROWIRE/PLUS mode. To use the MILUS, the
MSEL bit in the CNTRset to he master
mode the SK clock rthe tbits, SL0 and
SL1, in the CNTRL rails the different clock
rates that may be se
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock in
the normal mode. In the alternate SK phase mode the SIO
register is shifted on the rising edge of the SK clock.
Table 8 MICROster Mode Clock
SL1
SL0
SK
0
0
1
0
1
x
2 X tc
4 X tc
8 X tc
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configura-
tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
Where tc is the instruction cycle clock
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MI-
CROWIRE/PLUS to start shifting the data. It gets reset when
eight data bits have been shifted. The user may reset the
BUSY bit by software to allow less than 8 bits to shift. If en-
abled, an interrupt is generated when eight data bits have
www.national.com
29
Table 9 MICROWIRE/PLUS Mode Settings
G4 (SO)
Config. Bit Config. Bit
G5 (SK)
G4
Fun.
G5
Fun.
Operation
1
0
1
0
1
1
0
0
SO
Int. SK
Int. SK
MICROWIRE/PLUS Master
MICROWIRE/PLUS Master
TRI-STATE
SO
Ext. SK MICROWIRE/PLUS Slave
Ext. SK MICROWIRE/PLUS Slave
TRI-STATE
This table assumes that the control flag MSEL is set.
4
CHIP SELECT LINES
LCD
I/O
LINES
I/O
LINES
DISPLY
DRIVER
DISPLAY
DRIVER
COP472
EEPROM
COP888GD
(MASTER)
COP8
(SLAVE)
D0 SK DI
SK D
SK DI
SI
SO
SK
SO
SI
SK
Figure 15MICROIRE/PLUS Application
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30
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
S/ADD REG
Contents
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Address
Contents
S/ADD REG
0000 to 006F On-Chip RAM bytes (112 bytes)
0070 to 007F Unused RAM Address Space (Reads As All
Ones)
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
xx80 to xxAF Unused RAM Address Space (Reads
Undefined Data)
Port D
xxB0
XXB1
xxB2
xxB3
xxB4
xxB5
xxB6
Timer T3 Lower Byte
xxDD to DF Reserved for Port D
xxE0 to xxE5 Reserved
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA Lower Byte
Timer T3 Autoload Register T3RA Upper Byte
Timer T3 Autoload Register T3RB Lower Byte
Timer T3 Autoload Register T3RB Upper Byte
Timer T3 Control Register
xxE6
Timer T1 AuRegister T1RB Lower
Byte
xxE7
mer T1 oad Rester T1RB Upper
By
xxE8
xxE9
xxE
xxEB
xC
ICNTRRegister
xxB7 to xxBF Reserved
ROWIPLUS Shift Register
imer 1 Lower Byte
xxC0
xxC1
xxC2
Timer T2 Lower Byte
Timer T2 Upper Byte
TimeT1 Upper Byte
Timer T2 Autoload Register T2RA Lower
Byte
Timer T1 Autoload Register T1RA Lower
Byte
xxC3
xxC4
xxC5
Timer T2 Autoload Register T2RA Upper
Byte
ED
Timer T1 Autoload Register T1RA Upper
Byte
Timer T2 Autoload Register T2RB Lr
Byte
xEE
xxEF
CNTRL Control Register
PSW Register
Timer T2 Autoload Register T2Rer
Byte
xxF0 to FB On-Chip RAM Mapped as Registers
xxFC
xxFD
xxFE
xxFF
X Register
SP Register
B Register
S Register
xxC6
xxC7
Timer T2 Control Rgis
WATCHDOG Service
(Reg:W
xxC8
xxC9
xxCA
xxCB
MIWgister eg:WKEDG)
MIW(Reg:WKEN)
MIWU r (Reg:WKPND)
0100–017F On-Chip 128 RAM Bytes
Reading memory locations 0070H–007FH (Segment 0) will
return all ones. Reading unused memory locations
0080H–00AFH (Segment 0) will return undefined data.
Reading memory locations from other Segments (i.e., Seg-
ment 2, Segment 3, ... etc.) will return all ones.
A/D Convrol Register (Reg:
ENAD)
xxCC
A/D Convertor Result Register (Reg:
ADRSLT)
xxCD to
xxCE
Reserved
xxCF
xxD0
xxD1
xxD2
xxD3
xxD4
IDLE Timer Control Register (Reg: ITMR)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
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Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
Instructions Using A & C
Transfer of Control Instructions
[B]
Direct
Immed.
CLRA
INCA
DECA
LAID
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1
1/1
1/1
1/3
1/3
2/2
JMPL
JMP
JP
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
ADD
ADC
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
SUBC
AND
DCORA
RRCA
RLCA
SWAPA
SC
OR
ID
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
VIS
ET
RETSK
RETI
INTR
NOP
RC
1/3
3/4
3/4
3/4
IFC
1/1
1/1
1/1
IFNC
PU
PO
ANDSZ
RPND
1/1
ory Transfer Instructions
Register
ndirect
Register Indirect
Auto Incr & Decr
Direct Immed.
[B] [X]
[B+, B-] [X+, X-]
X A,*
1/1 1/3
1/1 1/3
2/3
1/2
1/2
1/3
1/3
LD A,*
2/3
2/2
1/1
2/2
LD B,Imm
(If B < 16)
(If B > 15)
LD B,Imm
LD Mem,Imm
LD Reg,Imm
IFEQ MD,Imm
2/2
3/3
2/3
3/3
2/2
* => Memory location addressed by B or X or directly.
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Indirect
Addressing Modes
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Note: The VIS is a special case of the Indirect Transfer of
Control addressing mode, where the double byte vector as-
sociated with the interrupt is transferred from adjacent ad-
dresses in the program memory into the program counter
(PC) in order to jump to the associated interrupt service rou-
tine.
Register Indirect (with auto post increment or decrement
of pointer)
This addressing mode is used with the LD and X instructions.
The operand is the data memory addressed by the B pointer
or X pointer. This is a register indirect mode that automatical-
ly post increments or decrements the B or X register after ex-
ecuting the instruction.
Instruction Set
Register and Symbol Deion
s
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
A
8-Bit Accuutor Rer
8-Bit Addrs egister
B
X
8-Bit Address Rster
Immediate
S
8-Bnt Regi
The instruction contains an 8-bit immediate field as the oper-
and.
SP
C
PU
PL
8Pointer Register
1rogram ounter Register
Up7 Bits oPC
Short Immediate
Lower 8 ts of PC
This addressing mode is used with the Load B Immediate in-
struction. The instruction contains a 4-bit immediate field as
the operand.
1 it of PSW Register for Carry
1 Biof PSW Register for Half Carry
1 Bit of PSW Register for Global Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
Indirect
This addressing mode is used with the LAID instruion. The
contents of the accumulator are used as a paral address
(lower 8 bits of PC) for accessing a data operad fm the
program memory.
Symbols
[B]
[X]
MD
Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
TRANSFER OF CONTROL ADRMODES
Relative
Mem Direct Addressed Memory or [B]
Meml Direct Addressed Memory or [B] or Immediate Data
This mode is used for tion, we instruction
field being added to er to gt the new pro-
gram location. JP h31 to +32 to allow a
1-byte relative jump ented by a NOP in-
struction). There are nusing JP, since all 15
bits of PC are used.
Imm
Reg
8-Bit Immediate Data
Register Memory: Addresses F0 to FF (Includes B, X and
SP)
Bit
←
↔
Bit Number (0 to 7)
Loaded with
Exchanged with
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions, with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory space.
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INSTRUCTION SET
ADD
ADC
SUBC
AND
ANDSZ
OR
A,Meml
A,Meml
A,Meml
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
ADD
A ← A + Meml
ADD with Carry
A ← A + Meml + C, C ← Carry, HC ← Half Carry
A ← A - MemI + C, C ← Carry, HC ← Half Carry
A ← A and Meml
Subtract with Carry
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Skip next if (A and Imm) = 0
A ← A or Meml
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
X
Logical EXclusive OR
IF EQual
A ← A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B Imm
Reg ← Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
0 to bit, Mem
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Reg
Decrement Reg., Skip if Zero
Set BIT
#,Mem
#,Mem
#,Mem
Reset BIT
IF BIT
If bit in A or Mem iext instruction
Reset Stware IntPendinFlag
A ↔ Mem
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Imed.
CLeaR A
A,Mem
A,[X]
X
A ↔ [X]
LD
A,Meml
A,[X]
A ← l
LD
A
LD
B,Imm
Mem,Imm
Reg,Imm
A, [B ]
A, [X ]
A, [B ]
A, [X ]
[B ],Imm
A
LD
M← Imm
LD
Reg
X
↔ [B], (B ← B 1)
X
A ↔ [X], (X ← X 1)
LD
A ← [B], (B ← B 1)
LD
A ← [X], (X ← X 1)
LD
[B] ← Imm, (B ← B 1)
CLR
INC
A ← 0
A
INCrement A
A ← A + 1
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
A
DECrem
A ← A - 1
Ld A m ROM
Deci
otate A C
e A Leru C
nibbles of A
A ← ROM (PU,A)
A
A
A
A
A ← BCD correction of A (follows ADC, SUBC)
C → A7 → ... → A0 → C
C ← A7 ←... ← A0 ← C
A7...A4 ↔ A3...A0
C ← 1, HC ← 1
RC
C
C ← 0, HC ← 0
IFC
IF C is true, do next instruction
If C is not true, do next instruction
SP ← SP + 1, A ← [SP]
[SP] ← A, SP ← SP - 1
PU ← [VU], PL←[VL]
IFNC
POP
PUSH
VIS
IF Not C
A
A
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
JMPL
JMP
JP
Addr.
Addr.
Disp.
Addr.
Addr
PC ← ii (ii = 15 bits, 0 to 32k)
PC9...0 ← i (i = 12 bits)
PC ← PC + r (r is -31 to +32, except 1)
[SP]←PL, [SP-1] ← PU,SP-2, PC ← ii
[SP]←PL, [SP-1] ← PU,SP-2, PC9...0 ← i
PL←ROM (PU,A)
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
SP + 2, PL← [SP], PU← [SP-1]
SP + 2, PL← [SP],PU← [SP-1]
SP + 2, PL ← [SP],PU← [SP-1],GIE←1
[SP]← PL, [SP-1]← PU, SP-2, PC← 0FF
PC← PC + 1
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Opcode TableMask Options
LOWER NIBBLE
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35
The mask programmable options are shown below. The op-
tions are programmed at the same time as the ROM pattern
submission.
— Bytecraft’s COP8C is a C language Software Develop-
ment Kit that provides a DOS based IDE, editor, C
compiler, linker and utility functions for COP8 software
cross development on a PC platform.
OPTION 1: CLOCK CONFIGURATION
■ COP8 Emulation & Simulation Tools:
=1
Crystal Oscillator (CKI/10)
— MetaLink’s iceMASTER™: IM-COP8/400 -- Full fea-
tured in-circuit emulation system for all COP8 prod-
ucts. A full set of COP888GD package specific probes
and surface mount adaptors are available to emulate
the COP888GD part family directly on application
hardware.
G7 (CKO) is clock generator output
to crystal/resonator CKI is the
clock input
=2
Single-pin RC controlled oscillator
(CKI/10)
— COP8 Debug Module: COP8-DM/888GD -- Moderate
cost in-circuit emulation and development program-
ming unit.
G7 is available as a HALT restart
and/or general purpose input
OPTION 2: HALT
— COP8
Evaluation
&
Programming
Unit:
=1
=2
Enable HALT mode
Disable HALT mode
EPU-COP888GG-1/2 -- A low cost In-circuit simulation
and development programming unit, not fully compat-
able to the COP888
OPTION 3: BONDING OPTIONS
=1 44-Pin PLCC
— COP8 Instruction Lmulator -- a non-hardware
platform foevaluatid testinsoftware algorithms.
■ OTP/EPROM grammSuppo: Covering needs from
engineering prototpe, pilot production to full production
environments.
Development Support
Overview
■ In-factomming upport: Covering high volume
produP prgramming.
National is engaged with an international community of inde-
pendent 3rd party vendors who provide hardware and soft-
ware development tool support. Each vendor brings an
individual expertise to create a precision development tool.
Through National’s interaction and guidance, these tools co-
operate to form a usable tool suite that fits the developer’s
needs.
DreWaOP8 Device Driver Design
EnvirnmenDE).
s Corration is a company dedicated to Window based
pment tools that are intuitive, easy to use and remove
f the burden to acquire detail component knowledge
r to create working, production worthy, control firm-
e for an application. DriveWay-COP8 provides a quick
and dependable method to develop efficient software func-
tions that correctly initialize the COP8 hardware and provide
callable functions to access and control the hardware. Docu-
mented and pretested source code modules are generated
automatically after the user makes a modest set of selections
from the menus presented. DriveWay-COP8 has a built in
Knowledge Base that provides the processor and peripheral
definition details to the software that enables the first time
generation of working code. Included with the code genera-
tion functionality is an extensive on-line help facility that pro-
vides the guidance necessary in making choices and also
provides an interactive context linked copy of the COP888EG
data sheet for on-line reference. Not only does the software
generate end-application code modules but there are options
to generate test driver software as well. The mysteries of
proper initialization to obtain the exact functional behavior
are avoided. In a short interactive session, functional proto-
typing of control software can be accomplished quickly and
accurately.
This section provides a summary of the tool suite. Tools ar
added and improved continuously. By utilizing thn-line
World Wide Web for information, every user cakeep cur-
rent. Search at www.cop8.com.
Following sections will provide a feature summary of tools
available at publication, order infmatih toond
finally provide the URL link paths to ser to re-
main current.
Summary of Tools
■ Project Definition Tools:
— Aisys CorporOP8 is a Windows
based project hat will automatically
generate documssembly source code
modules containing cmized I/O drivers, interrupt
handlers and main program shell to meet application
requirements. Application specific code can be insert-
ed using the integrated editor. Language and emula-
tion tools can be launched directly from
DriveWay-COP8.
— K&K Development’s WCOP8 IDE is a Windows based
integrated development tool that can be used to define
and edit source language modules associated to the
project. Code language development and emulation
tools can be launched directly from the project window
framework.
Starting from a design concept or block diagram sketch, a
firmware engineer makes simple choices:
■ Select the COP888EG model and package, EG is not fully
compatible.
■ Define the oscillator frequency and other configuration
parameters, such as WATCHDOG enable, to configure
the core chip elements.
■ Language Tools:
— COP8 Assembly Language Development Software Kit
provides DOS based macro assembler, linker, libraries
and utility functions for COP8 software cross develop-
ment on a PC platform.
■ Using the interactive data sheet’s (IDS) chip block dia-
gram, select the I/O port and alternate peripheral func-
www.national.com
36
tions to be enabled and to define application functional pin
usage.
from the WEB. Current product release status, product and
ordering information are all available at the one URL.
■ For each function, select and define the parameters for
correct initialization. The IDS may be consulted for a def-
inition of parameters, and provides guidance to make
good choices. As an example, a PWM timer’s characteris-
tics are defined by its frequency and duty cycle in user
friendly units. The hardware setup values are then gener-
ated automatically based on the oscillator frequency.
Change the global oscillator frequency and all of the code
objects will have the parameters adjusted correctly with-
out requiring redefinition. The function to initialize the tim-
er will be generated automatically and linked to the
initialization start-up code.
K&K Development
URL
www.kkd.dk
email
kkd@dk-online.dk
COP8 Assembler/linker Software Development
Tool Kit
National offers a relocatable COP8 macro cross assembler,
linker, librarian and utility software development tool kit. Fea-
tures are summarized as follows:
■ Select language tool: Assembly or C. DriveWay-COP8 will
generate proper syntax for this selection.
■ Basic and Feature Family instruction set by "device" type.
■ Nested macro capability.
■ Select or disable optional test code generation.
■ At click of the mouse button, generate include files and
source code files.
■ Display the source lines in the integrated EDIT window
and add the application specific code statements to link
input stimulus to output actions. Code lines edited within
well marked ‘save’ points are preserved from generation
to generation within the project.
■ The entire application, or early-on application segment, is
ready for compile, link and test using the language and
emulation tools.
■ Generated code is well documented, automatically as
well. A TEXT file documenting the project is likewise auto-
matically generated. All generated code has been exte
sively pre-tested by Aisys on COP8 emulation tools.
■ Extensive set of assembler directives.
■ Supported on PC/DOS
■ Generates National stOFF output files.
■ Integrated Lier & Libn.
■ Integrated utilitto genate ROM code file outputs.
■ DUMPCOFF utility
This producegrated witMetaLink tools as a develop-
ment kit, orted by the MetaLink debugger. The as-
embler wise upported by DriveWay-COP8 and
WOP8 IThe asembler may be downloaded from the
WEB r may mbe ordered separately. It is bundled with
MetaLinproducts at no additional cost.
Assembler/Linker Order Information
bler SDK:
DriveWay-COP8 Order Information
P8-DEV-IBMA Assembler SDK on installable 3.5”
PC®/DOS Floppy Disk Drive format.
Periodic upgrades and most recent
version is available on National’s Web
site.
Additional information about Aisys is available n the W
and DriveWay-COP8 may be ordered directly oAisys
Corporation. Demo software is available for download.
Aisys Corporation
URL for latest
information.
www.national.com/cop8
Phone
s.co.il/ducts/cop8.html
.co.il
Santa Clara: 408-32
Boston: 617-270-74
Israel: 972-3-92268
COP8 C Compiler Software Development Tool
A C Compiler is developed and marketed by Byte Craft Lim-
ited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embedded
configuration of the COP8 family of products.
WCOP8 IDE Integrament Environment
WCOP8 IDE is a Windows based COP8 Integrated Develop-
ment Environment that serves as an interface to the COP8
Language and Emulation development tools. The edit func-
tion for code and documentation development is integrated.
Also available is a “Project Wizard” that provides a simple
means to link the development tools into a project file, which
contains pointers to source files, and locates/defines the de-
velopment tool usage. The Build and Make functions are au-
tomatically invoked by the point and click method. Compiler /
assembler errors are linked to the editor for correction. The
emulation tools are also invoked by the simple point and click
method for start-up. The DOS environment used by these
tools is transparent.
Features are summarized as follows:
■ DOS based IDE with editor for on-line development
■ COP8 header include files and libraries
■ Byte Craft linker; links objects C source or Assembly
source, compiled by COP8C
■ ANSI C with some restrictions and extensions that opti-
mize development for the COP8 embedded application.
■ BITS data type extension. Register declaration #pragma
with direct bit level definitions.
■ C language support for interrupt routines.
■ Expert system, rule based code generation and optimiza-
tion.
WCOP8 IDE Order Information
■ Performs consistency checks against the architectural
definitions of the target COP8 device.
■ Generates program memory code.
Additional information about K&K Development is available
on the WEB. User documentation and a zero cost 30 day
evaluation copy of WCOP8 IDE may be downloaded directly
■ Global optimization of linked code.
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37
■ Symbolic debug load format fully source level supported
by the MetaLink debugger software
■ Tested source generated by Aisys’ DriveWay-COP8.
■ Tool set integrated interactive symbolic debugger - sup-
ports both assembler (COFF) and C Compiler (.COD)
linked object formats.
■ Real time performance profiling analysis; selectable buck-
et definition.
■ Watch windows, content updated automatically at each
execution break.
COP8C Order Information
Byte Craft Limited
Phone
URL
■ Instruction by instruction memory/register changes dis-
played on source window when in single step operation.
■ Single base unit & debugger software reconfigurable to
support the entire COP8 family; only the probe personality
needs to change. Debugger software is processor cus-
tomized, and reconfigured from a master model file.
■ Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
■ Halt/Idle mode notification.
Canada: 519-888-6911
www.bytecraft.com/cop8c.html
IceMASTER (IM) In-circuit Emulation
The iceMASTER IM-COP8/400 is a PC DOS based full fea-
ture in-circuit emulation tool developed and marketed by Met-
aLink Corporation to support the whole COP8 family of
products. National and it’s Authorized Distributors are resale
vendors for these products.
■ On-line HELP.
■ Includes a copy of COBMA assembler & linker
SDK.
See Figure 16 for configuration.
The iceMASTER IM-COP8/400 with its device specific COP8
Probe and provides a rich feature set for developing, testing
and maintaining product:
IceMASTER Ordr nformon
MetaLink Corporatn
■ Real-time in-circuit emulation; full 2.5-5.5V operation
range, full DC-10 MHz clock. Chip options are program-
mable or jumper selectable.
■ Direct connection to application board by package com-
patible socket or surface mount assembly.
Ph
Chandle
0-6383
60226-077
URL/email
www.metaice.com
sales@metaice.com
■ Full 32K byte of loadable programming space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on th
probe as necessary.
Nations NSID
Description
OP8/400-1
iceMASTER base unit, 110V
Power Supply
■ Full 4k frame synchronous trace memory. Address, in
struction, and eight unspecified, circuit connectble trace
lines. Display can be HLL source (e.g., C soue), asse
bly or mixed.
OP8/400-2
iceMASTER base unit, 220V
Power Supply
iceMASTER Probe Card, COP888GD
■ A full 64k hardware configurable break, trace on, trace of
control, and pass count incrent e
MHW-888GD44PWPC 44 PLCC, 2.5 – 5.5V
Figure 16. COP8 IceMASTER Environment
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38
■ Instruction by instruction memory/register changes dis-
played when in single step operation.
■ Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
■ Halt/Idle mode notification.
■ Programming hardware supports all SOIC, DIP and PLCC
packages.
■ Program menu and algorithm supports full product line of
programmable OTP and EPROM COP8 products. Pro-
gram data is taken directly from the overlay RAM.
■ Includes wall mount power supply
IceMASTER Debug Module (DM)
The iceMASTER Debug Module is a combination in-circuit
emulation and COP8 OTP/EPROM programming tool which
is bundled with MetaLink’s PC based, DOS compatible de-
bugger software and National’s assembler SDK. The DM
products are marketed by MetaLink Corporation to support
the COP8 family of products. National and it’s Authorized
Distributors are resale vendors for these products.
See Figure 17 for configuration.
The iceMASTER Debug Module is a moderate cost develop-
ment tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product fami-
lies. Summary of features is as follows:
■ Includes a copy of COP8-DEV-IBMA assembler & linker
SDK.
Debug Module Order Information
MetaLink Corporation
■ Real-time in-circuit emulation; full operating voltage range
operation, full DC-10MHz clock.
■ All processor I/O pins can be cabled to an application de-
velopment board with package compatible cable to socket
and surface mount assembly.
■ Full 32 kbyte of loadable programming space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as nec-
essary.
Phone
Chandler, AZ
URL/email
w.meice.com
800-638-2423
602-926-0797
ales@mtaice.com
National’s NSID
Description
COP8-D
Debug Module
■ 100 frames of synchronous trace memory. The display
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the trace
memory.
able Ables, quires one for emulation. *The
flaed its are ncluded, 1 each, with a DM; others,
as reired, need to be ordered separately.
■ configured break points; uses INTR instruction which i
modestly intrusive.
-COP44P
44 PLCC
■ software - only supported features are selectable.
■ Tool set integrated interactive symbolic debuggsup-
ports both assembler (COFF) and C Comper (.COD)
SDK linked object formats.
Figure 17. COP8-DM Environment
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39
■ Tool set integrated interactive symbolic debugger - sup-
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
■ Instruction by instruction memory/register changes dis-
played when in single step operation.
■ Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
■ Halt/Idle mode notification. Restart requires special han-
dling.
■ Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Only a 40 ZIF
socket is available on the EPU unit. Adapters are available
for other part package configurations.
IceMASTER Evaluation Programming Unit (EPU)
The iceMASTER EPU-COP888GG is a PC based in-circuit
hardware simulation tool bundled with the MetaLink DOS
based debugger software to support the COP888xG prod-
ucts for evaluation and limited development.The GD is not
pin function compatible.
See Figure 18 for configuration.
The simulation capability is a very low cost means of evalu-
ating the general COP888xG architecture. In addition, the
EPU has programming capability, with added adapters, for
programming the whole COP888xG product family of OTP
and EPROM products. The product includes the following
features:
■ Includes wall mount power supply.
■ Includes a copy of COP8-DEV-IBMA assembler, linker
SDK.
■ Non-real-time in-circuit simulation. Program overlay mem-
ory is PC resident; instructions are downloaded over
RS-232 as executed. Approximate performance is 20KHz.
■ Includes a 40 pin DIP cable adapter for direct connection
to a target with 40-pin DIP socket. Other target packages
are not supported. All processor I/O pins are cabled to the
application development environment.
■ Full 32 kbyte of loadable programming space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as nec-
essary.
■ On-chip timer and watch-dog execution are NOT synchro-
nized to the instruction simulation.
■ 100 frames of synchronous trace memory. The display
can be HLL source (e.g., C source), assembly or mixed
The most recent history prior to a break is available in th
trace memory.
EPU Order-Information
MetaLink Corporation
Phone
URL/email
www.metaice.com
Chandler, AZ
800-638-24
602-926
les@metaice.com
ationaSID
Description
EPUCOP8G1/2 Evaluation Programming Unit
with debugger and programmer
control software with 40 pin ZIF
programming socket. Programs
40-pin DIP COP87Lxxx.
■ Up to eight software configured break points; usINTR
instruction which is modestly intrusive.
ional Programming Adapters
■ Common look-feel debugger software across ll MeLink
products - only supported features are selectable.
COP8SA-PGMA
44 PLCC, 28, 20 and 16 SOIC,
and 28, and 20 DIP
Figure 18. EPU-COP8 Tool Environment
www.national.com
40
iceMASTER Debugger with Software Simulation
This is a software debugger tool that uses the common
iceMASTER PC DOS based debugger to provide instruction
level debugging. Setup and configuration are common to all
MetaLink tools. The simulator is instruction level only and
does not simulation I/O or interrupt behavior. Available at no
charge from National’s COP8 web site:
System General (Taiwan)
www.sg.com.tw
sales@sg.com.tw
TAI: Taipei
2-917-3005
Fax: 2-911-1283
bbs: 2-918-1076
Xeltek (USA)
www.xeltec.com
info@xeltec.com
USA: Sunnyvale, CA
408-524-1929
Fax: 408-245-7084
bbs: 408-245-7082
www.cop8.com
Industry Wide OTP / EPROM Programming
Support
Available Literature
Programming support, in addition to the MetaLink develop-
ment tools, is provided by a full range of independent ap-
proved vendors to meet the needs from the engineering
laboratory to full production. Updated information can be ob-
tained from our web site at:
For more information, please see the COP8 Feature Family
User's Manual, Literature Number 620897, and National's
Family of 8-bit Microcontrollers COP8 Selection Guide,
Literature Number 630006. Literature can be obtained from
National’s web site at:
www.cop8.com
www.cop8.com
Approved List:
Customer Resse Cter
Complete product inforation and technical support is available
from National'stomer sponse centers.
Manufacturer
URL/email
Home Office Location
Telephone/Fax/bbs
CANADTel:
ema
(800) 272-9959
BP Microsystems (USA)
www.bpmicro.com
sales@bpmicro.com
USA: Houston, TX
800-225-2102
713-688-4600
Fax : 713-688-0920
bbs: 713-688-9283
support@tevm2.nsc.com
europe.support@nsc.com
+49 (0) 180-530 85 85
+49 (0) 180-532 78 32
+81-043-299-2309
EURPE:
mail:
Deutsch Tel:
English Tel:
Tel:
Data I/O (USA)
USA: Redmon, WA
800-426-1045
206-881-6444
Fax: 206-882-104
bbs: 206-882-3211
:
www.data-io.com
sales@data-io.com
techhelp@data-io.com
. ASIA:
Singapore Tel: (+65) 254-4466
email: sea.support@nsc.com
AUSTRALIA: Tel:
INDIA: Tel:
(+61) 3-9558-9999
(+91) 80-559-9467
HI - LO (Taiwan)
www.hilosystems.com.tw
hilosys@fit.ivnet.com.tw
T: Taip
2-760
Fax: 2-
: 2-76
ICE Technology (UK
www.icetech.com
istone, S. York
67404
sales@icetech.com
226-370434
ck:0-1226-761844
s: 0-1226-761181
MetaLink (USA)
www.metaice.com
sales@metaice.com
USA: Chandler, AZ
800-638-2423
602-926-0797
Fax: 602-693-0681
Needhams (USA)
www.needhams.com
support@needhams.com
USA: Sacramento, CA
916-924-8037
Fax: 916-924-8065
SMS (Germany)
Fax: 7522-9728-88
www.sms-sprint.com
info@sms-sprint.com
Stag (UK)
Fax: 01707-371503
www.stagdev.com
stagdev@henge.com
www.national.com
41
Physical Diamensions inches (millimeters) unless otherwise noted
Plastic LeaCarrier (V)
Order Numbr COP888GD-XXX/V or COP988GD-XXX/V
ee Paage Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Asia Pacific
National Semiconductor
Japan Ltd.
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
Customer Response Group
Tel: 65-254-4466
Fax: 65-250-4466
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
Fax:
(+49) 0-180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel:
English Tel:
(+49) 0-180-530 85 85
(+49) 0-180-532 78 32
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the reight at any time without notice to change said circuitry and specifications.
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