COPC881 [NSC]
Microcontrollers; 微控制器
| 型号： | COPC881 |
| 厂家： | 
National Semiconductor |
| 描述： | Microcontrollers |
| 文件： | 总30页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1996
COP680C/COP681C/COP682C/COP880C/COP881C/
COP882C/COP980C/COP981C/COP982C
Microcontrollers
Y
Schmitt trigger inputs on Port G
General Description
Y
Y
MICROWIRE PLUS serial I/O
Packages:
Ð 20 DIP/SO with 16 I/O pins
Ð 28 DIP/SO with 24 I/O pins
Ð 40 DIP, 36 I/O pins
The COP680C/COP681C/COP682C/COP880C/COP881C
/COP882C/COP980C/COP981C and COP982C are mem-
bers of the COPSTM microcontroller family. They are fully
static parts, fabricated using double-metal silicon gate
microCMOS technology. This low cost microcontroller is a
complete microcomputer containing all system timing, inter-
rupt logic, ROM, RAM, and I/O necessary to implement
dedicated control functions in a variety of applications. Fea-
tures include an 8-bit memory mapped architecture, MI-
CROWIRE/PLUSTM serial I/O, a 16-bit timer/counter with
capture register and a multi-sourced interrupt. Each I/O pin
has software selectable options to adapt the device to the
specific application. The part operates over a voltage range
of 2.5 to 6.0V. High throughput is achieved with an efficient,
regular instruction set operating at a 1 microsecond per in-
struction rate.
Ð 44 PLCC, 36 I/O pins
CPU/Instruction Set Features
Y
1 ms instruction cycle time
Y
Three multi-source interrupts servicing
Ð External interrupt with selectable edge
Ð Timer interrupt
Ð Software interrupt
Y
Versatile and easy to use instruction set
Y
8-bit Stack Pointer (SP)Ðstack in RAM
Y
Two 8-bit Register Indirect Data Memory Pointers
(B and X)
Key Features
Y
16-bit multi-function timer supporting
Ð PWM mode
Fully Static CMOS
Y
Y
Y
k
1 mA)
Low current drain (typically
Ð External event counter mode
Ð Input capture mode
Single supply operation: 2.5V to 6.0V
Temperature ranges: 0 C to 70 C,
b
a
85 C,
40 C to
§
§
§
§
Y
4 kbytes of ROM
b
a
55 C to 125 C.
§
§
Y
128 bytes of RAM
Development Support
Y
I/O Features
Y
Emulation and OTP devices
Memory mapped I/O
Y
Real time emulation and full program debug offered by
MetaLink’s development system
Y
Software selectable I/O options (TRI-STATE
, Push-
É
Pull, Weak Pull-Up Input, High Impedance Input)
High current outputs (8 pins)
Y
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
COPSTM, HPCTM, MICROWIRETM and MICROWIRE/PLUSTM are trademarks of National Semiconductor Corporation.
iceMASTERTM is a trademark of MetaLink Corporation.
PC-XTÉ and PC-ATÉ are registered trademarks of International Business Machines Corporation.
C
1996 National Semiconductor Corporation
TL/DD10802
RRD-B30M106/Printed in U. S. A.
http://www.national.com
Block Diagram
TL/DD/10802–1
FIGURE 1
http://www.national.com
2
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package (N)
and 28 Wide SO (WM)
TL/DD/10802–23
Top View
Order Number COP882C-XXX/N, COP982C-XXX/N,
COP882C-XXX/WM, COP982C-XXX/WM,
COP982C-XXX/N or COP982CH-XXX/WM
TL/DD/10802–5
Top View
Order Number COP881C-XXX/N, COP981C-XXX/N,
COP881C-XXX/WM, COP981C-XXX/WM,
COP981CH-XXX/N or COP981CH-XXX/WM
Dual-In-Line Package
Plastic Chip Carrier
TL/DD/10802–3
Top View
Order Number COP680C-XXX/V, COP880C-XXX/V,
COP980C-XXX/V or COP980CH-XXX/V
TL/DD/10802–4
Top View
Order Number COP680C-XXX/N, COP880C-XXX/N,
COP980C-XXX/N or COP980CH-XXX/N
FIGURE 3. Connection Diagrams
3
http://www.national.com
COP980C/COP981C/COP982C
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Total Current out of GND Pin (Sink)
Storage Temperature Range
60 mA
b
a
65 C to 140 C
§
§
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
Supply Voltage (V
)
CC
7V
b
a
0.3V
Voltage at any Pin
Total Current into V Pin (Source)
0.3V to V
CC
50 mA
CC
s
s
a
DC Electrical Characteristics COP98xC; 0 C
T
A
70 C unless otherwise specified
§
§
Parameter
Condition
Min
Typ
Max
Units
Operating Voltage
98XC
98XCH
Power Supply Ripple (Note 1)
2.3
4.0
4.0
6.0
V
V
V
Peak to Peak
0.1 V
CC
Supply Current
e
e
e
e
e
e
e
e
e
e
CKI
CKI
CKI
CKI
10 MHz
4 MHz
4 MHz
1 MHz
V
CC
V
CC
V
CC
V
CC
6V, tc
6V, tc
1 ms
2.5 ms
2.5 ms
10 ms
6.0
4.4
2.2
1.4
mA
mA
mA
mA
e
4.0V, tc
4.0V, tc
e
(Note 2)
HALT Current
(Note 3)
k
k
e
e
e
e
V
CC
V
CC
6V, CKI
4.0V, CKI
0 MHz
0 MHz
0.7
0.4
8
5
mA
mA
Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.9 V
0.7 V
V
V
CC
0.1 V
0.2 V
CC
CC
V
V
CC
e
e
b
b
a
1.0
Hi-Z Input Leakage
Input Pullup Current
V
CC
V
CC
6.0V
6.0V, V
1.0
40
mA
mA
e
b
0V
250
IN
G Port Input Hysteresis
0.35 V
V
CC
Output Current Levels
D Outputs
Source
e
e
e
e
e
b
b
10
2
V
CC
V
CC
V
CC
V
CC
4.5V, V
2.3V, V
4.5V, V
2.3V, V
3.8V
1.6V
1.0V
0.4V
0.4
0.2
mA
mA
mA
mA
OH
OH
OL
OL
e
e
e
Sink
All Others
Source (Weak Pull-Up)
e
e
e
e
e
e
e
e
e
e
e
e
e
b
b
a
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
4.5V, V
2.3V, V
4.5V, V
2.3V, V
4.5V, V
2.3V, V
6.0V
3.2V
1.6V
3.8V
1.6V
0.4V
0.4V
10
2.5
0.4
0.2
110
mA
mA
mA
OH
OH
OH
OH
OL
OL
b
b
b
1.6
0.7
b
33
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
mA
b
1.0
1.0
mA
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
15
3
mA
mA
Maximum Input Current (Note 4)
Without Latchup (Room Temp)
g
Room Temp
100
mA
RAM Retention Voltage, Vr
(Note 5)
500 ns Rise and
Fall Time (Min)
2.0
V
Input Capacitance
7
pF
pF
Load Capacitance on D2
1000
http://www.national.com
4
COP980C/COP981C/COP982C
DC Electrical Characteristics (Continued)
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L, C and G ports TRI-STATE
CC
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V and the pins will
CC
have sink current to V
CC
resistance to V
CC
when biased at voltages greater than V
(the pins do not have source current when biased at a voltage below V ). The effective
CC
CC
is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
s
s
a
AC Electrical Characteristics 0 C
§
T
A
70 C unless otherwise specified
§
Parameter
Condition
Min
Typ
Max
Units
Instruction Cycle Time (tc)
t
s
t
s
Crystal/Resonator or External
(Div-by 10)
V
4.0V
1
DC
DC
DC
DC
ms
ms
ms
ms
CC
2.3V
s
s
V
CC
4.0V
4.0V
4.0V
2.5
3
R/C Oscillator Mode
(Div-by 10)
V
CC
2.3V
V
CC
7.5
e
e
e
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
fr
fr
fr
Max
40
60
12
8
%
ns
ns
10 MHz Ext Clock
10 MHz Ext Clock
Fall Time (Note 6)
Inputs
t
s
t
s
t
V
4.0V
200
500
60
ns
ns
ns
ns
SETUP
CC
s
s
2.3V
V
CC
4.0V
4.0V
4.0V
t
V
CC
2.3V
HOLD
V
CC
150
e
e
2.2 kX
Output Propagation Delay
C
L
100 pF, R
L
t
, t
PD1 PD0
t
SO, SK
V
4.0V
0.7
1.75
1
ms
ms
ms
ms
CC
s
t
s
s
s
2.3V
V
CC
4.0V
4.0V
4.0V
All Others
V
CC
2.3V
V
CC
2.5
MICROWIRETM Setup Time (t
UWS)
20
56
ns
ns
MICROWIRE Hold Time (t
MICROWIRE Output
UWH)
Propagation Delay (t
)
220
ns
UPD
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
t
C
t
C
t
C
t
C
Reset Pulse Width
1.0
ms
Note 6: Parameter characterized but not production tested.
5
http://www.national.com
COP880C/COP881C/COP882C
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Total Current out of GND Pin (Sink)
Storage Temperature Range
60 mA
b
a
65 C to 140 C
§
§
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
Supply Voltage (V
)
CC
7V
b
a
0.3V
Voltage at any Pin
Total Current into V Pin (Source)
0.3V to V
CC
50 mA
CC
s
s
a
b
DC Electrical Characteristics COP88xC; 40 C
T
85 C unless otherwise specified
§
§
A
Parameter
Condition
Min
2.5
Typ
Max
Units
Operating Voltage
Power Supply Ripple (Note 1)
Supply Current
6.0
0.1 V
CC
V
V
Peak to Peak
e
e
e
e
e
e
e
e
e
e
CKI
CKI
CKI
CKI
10 MHz
4 MHz
4 MHz
1 MHz
V
CC
V
CC
V
CC
V
CC
6V, tc
6V, tc
1 ms
2.5 ms
2.5 ms
10 ms
6.0
4.4
2.2
1.4
mA
mA
mA
mA
e
4.0V, tc
4.0V, tc
e
(Note 2)
HALT Current
(Note 3)
k
k
e
e
e
e
V
CC
V
CC
6V, CKI
3.5V, CKI
0 MHz
0 MHz
1
0.5
10
6
mA
mA
Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.9 V
0.7 V
V
V
CC
0.1 V
0.2 V
CC
CC
V
V
CC
e
e
b
b
a
2
Hi-Z Input Leakage
Input Pullup Current
V
CC
V
CC
6.0V
6.0V, V
2
40
mA
mA
e
b
0V
250
IN
G Port Input Hysteresis
0.35 V
V
CC
Output Current Levels
D Outputs
Source
e
e
e
e
e
b
b
10
2
V
CC
V
CC
V
CC
V
CC
4.5V, V
2.5V, V
4.5V, V
2.5V, V
3.8V
1.8V
1.0V
0.4V
0.4
0.2
mA
mA
mA
mA
OH
OH
OL
OL
e
e
e
Sink
All Others
Source (Weak Pull-Up)
e
e
e
e
e
e
e
e
e
e
e
e
e
b
b
a
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
4.5V, V
2.5V, V
4.5V, V
2.5V, V
4.5V, V
2.5V, V
6.0V
3.2V
1.8V
3.8V
1.8V
0.4V
0.4V
10
2.5
0.4
0.2
110
mA
mA
mA
OH
OH
OH
OH
OL
OL
b
b
b
1.6
0.7
b
33
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
mA
b
2.0
2.0
mA
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
15
3
mA
mA
Maximum Input Current (Note 4)
Without Latchup (Room Temp)
g
Room Temp
100
mA
RAM Retention Voltage, Vr
(Note 5)
500 ns Rise and
Fall Time (Min)
2.0
V
Input Capacitance
7
pF
pF
Load Capacitance on D2
1000
http://www.national.com
6
COP880C/COP881C/COP882C
DC Electrical Characteristics (Continued)
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L, C and G ports TRI-STATE
CC
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V and the pins will
CC
have sink current to V
CC
resistance to V
CC
when biased at voltages greater than V
(the pins do not have source current when biased at a voltage below V ). The effective
CC
CC
is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
s
s
a
b
AC Electrical Characteristics 40 C
T
A
85 C unless otherwise specified
§
§
Parameter
Condition
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal/Resonator or External
(Div-by 10)
t
s
t
s
V
4.5V
1
DC
DC
DC
DC
ms
ms
ms
ms
CC
2.5V
k
k
V
CC
4.5V
4.5V
4.5V
2.5
3
R/C Oscillator Mode
(Div-by 10)
V
CC
2.5V
V
CC
7.5
e
e
e
CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
fr
fr
fr
Max
40
60
12
8
%
ns
ns
10 MHz Ext Clock
10 MHz Ext Clock
Fall Time (Note 6)
Inputs
t
s
t
s
t
V
4.5V
200
500
60
ns
ns
ns
ns
SETUP
CC
k
k
2.5V
V
CC
4.5V
4.5V
4.5V
t
V
CC
2.5V
HOLD
V
CC
150
e
e
2.2 kX
Output Propagation Delay
C
L
100 pF, R
L
t
, t
PD1 PD0
t
SO, SK
V
4.5V
0.7
1.75
1
ms
ms
ms
ms
CC
s
t
s
k
k
2.5V
V
CC
4.5V
4.5V
4.5V
All Others
V
CC
2.5V
V
CC
2.5
MICROWIRETM Setup Time (t
UWS)
20
56
ns
ns
MICROWIRE Hold Time (t
MICROWIRE Output
UWH)
Propagation Delay (t
)
220
ns
UPD
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
t
C
t
C
t
C
t
C
Reset Pulse Width
1.0
ms
Note 6: Parameter characterized but not production tested.
Timing Diagram
TL/DD/10802–2
FIGURE 2. MICROWIRE/PLUS Timing
7
http://www.national.com
COP680C/COP681C/COP682C
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Total Current Out of GND Pin (Sink)
Storage Temperature Range
48 mA
b
a
65 C to 140 C
§
§
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
Supply Voltage (V
)
CC
6V
b
a
0.3V
Voltage at Any Pin
Total Current into V Pin (Source)
0.3V to V
CC
40 mA
CC
s
s
a
b
DC Electrical Characteristics COP68xC: 55 C
T
125 C unless otherwise specified
§
§
A
Parameter
Condition
Min
Typ
Max
Units
Operating Voltage
4.5
5.5
V
V
Power Supply Ripple (Note 1)
Supply Current (Note 2)
Peak to Peak
0.1 V
CC
e
e
e
e
e
e
e
CKI
CKI
10 MHz
4 MHz
V
CC
V
CC
V
CC
5.5V, tc
5.5V, tc
1 ms
2.5 ms
8.0
4.4
30
mA
mA
mA
k
e
HALT Current (Note 3)
5.5V, CKI
0 MHz
10
Input Levels
RESET, CKI
Logic High
Logic Low
0.9 V
0.7 V
V
V
CC
0.1 V
0.2 V
CC
All Other Inputs
Logic High
Logic Low
V
V
CC
CC
e
e
b
a
5
Hi-Z Input Leakage
Input Pullup Current
V
V
5.5V
5
mA
mA
CC
e
b
b
5.5V, V
0V
35
300
CC
IN
G Port Input Hysteresis
0.35 V
V
CC
Output Current Levels
D Outputs
e
e
e
e
b
b
Source
V
V
4.5V, V
4.5V, V
3.8V
1.0V
0.35
9
mA
mA
CC
OH
Sink
CC
OL
All Others
e
e
e
e
e
e
e
b
b
120
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
V
CC
V
CC
V
CC
V
CC
4.5V, V
4.5V, V
4.5V, V
5.5V
3.2V
3.2V
0.4V
9
mA
mA
mA
mA
OH
OH
OL
0.35
1.4
b
a
5.0
5.0
Allowable Sink/Source Current per Pin
D Outputs (Sink)
12
2.5
mA
mA
All Others
Maximum Input Current (Room Temp)
without Latchup (Note 4)
g
Room Temp
500 ns Rise and Fall Time (Min)
100
mA
V
RAM Retention Voltage, Vr (Note 5)
Input Capacitance
2.5
7
pF
pF
Load Capacitance on D2
1000
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L and G ports TRI-STATE
CC
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V and the pins will
CC
have sink current to V
CC
resistance to V
CC
when biased at voltages greater than V
(the pins do not have source current when biased at a voltage below V ). The effective
CC
CC
is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
http://www.national.com
8
COP680C/COP681C/COP682C
s
s
a
b
AC Electrical Characteristics 55 C
T
A
125 C unless otherwise specified
§
§
Parameter
Condition
Min
1
Typ
Max
DC
60
Units
ms
Instruction Cycle Time (tc)
Ext. or Crystal/Resonant
(Div-by 10)
t
V
fr
4.5V
CC
e
CKI Clock Duty Cycle
(Note 6)
Max
40
%
e
e
Rise Time (Note 6)
Fall Time (Note 6)
fr
fr
10 MHz Ext Clock
10 MHz Ext Clock
12
8
ns
ns
MICROWIRE Setup Time (t
)
20
56
ns
ns
UWS
MICROWIRE Hold Time (t
MICROWIRE Output Valid
)
UWH
220
ns
Time (t
)
UPD
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
t
C
t
C
t
C
t
C
Reset Pulse Width
1
ms
Note 6: Parameter characterized but not production tested.
9
http://www.national.com
s
s
a
b
Typical Performance Characteristics ( 40 C
T
A
85 C)
§
§
HallÐI
DynamicÐI (Crystal Clock Option)
DD
DD
TL/DD/10802–16
TL/DD/10802–17
Port L/C/G Weak Pull-Up
Source Current
Port L/C/G Push-Pull Source Current
TL/DD/10802–19
TL/DD/10802–18
Port L/C/G Push-Pull Sink Current
Port D Source Current
TL/DD/10802–20
TL/DD/10802–21
Port D Sink Current
TL/DD/10802–22
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10
PORT D is an 8-bit output port that is preset high when
RESET goes low. Care must be exercised with the D2 pin
operation. At RESET, the external loads on this pin must
Pin Descriptions
and GND are the power supply pins.
V
CC
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc-
tion with CKO). See Oscillator description.
ensure that the output voltages stay above 0.9 V
CC
vent the chip from entering special modes. Also, keep the
external loading on D2 to less than 1000 pF.
to pre-
RESET is the master reset input. See Reset description.
Functional Description
PORT I is an 8-bit Hi-Z input port. The 28-pin device does
not have a full complement of Port I pins. The unavailable
pins are not terminated i.e., they are floating. A read opera-
tion for these unterminated pins will return unpredictable
values. The user must ensure that the software takes this
into account by either masking or restricting the accesses to
bit operations. The unterminated Port I pins will draw power
only when addressed.
Figure 1 shows the block diagram of the internal architec-
ture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each oth-
er in implementing the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.
PORT L is an 8-bit I/O port.
PORT C is a 4-bit I/O port.
There are five CPU registers:
A is the 8-bit Accumulator register
Three memory locations are allocated for the L, G and C
ports, one each for data register, configuration register and
the input pins. Reading bits 4–7 of the C-Configuration reg-
ister, data register, and input pins returns undefined data.
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register, can be auto incremented or
decremented.
There are two registers associated with the L and C ports: a
data register and a configuration register. Therefore, each L
and C I/O bit can be individually configured under software
control as shown below:
X is the 8-bit alternate address register, can be incremented
or decremented.
SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
Config. Data
Ports L and C Setup
B, X and SP registers are mapped into the on chip RAM.
The B and X registers are used to address the on chip RAM.
The SP register is used to address the stack in RAM during
subroutine calls and returns.
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
Push-Pull One Output
PROGRAM MEMORY
On the 28-pin part, it is recommended that all bits of Port C
be configured as outputs.
Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data. The
program memory is addressed by the 15-bit program coun-
ter (PC). ROM can be indirectly read by the LAID instruction
for table lookup.
PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs.
There are two registers associated with the G port: a data
register and a configuration register. Therefore, each G port
bit can be individually configured under software control as
shown below:
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the in-
struction or indirectly by the B, X and SP registers.
Config. Data
Port G Setup
The device has 128 bytes of RAM. Sixteen bytes of RAM
are mapped as ‘‘registers’’ that can be loaded immediately,
decremented or tested. Three specific registers: B, X and
SP are mapped into this space, the other bytes are available
for general usage.
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
Push-Pull One Output
The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except the A & PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. A is not mem-
ory mapped, but bit operations can be still performed on it.
Note: RAM contents are undefined upon power-up.
Since G6 and G7 are input only pins, any attempt by the
user to configure them as outputs by writing a one to the
configuration register will be disregarded. Reading the G6
and G7 configuration bits will return zeros. The device will
be placed in the HALT mode by writing to the G7 bit in the
G-port data register.
RESET
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports L, G and C are
placed in the TRI-STATE mode and the Port D is set high.
The PC, PSW and CNTRL registers are cleared. The data
and configuration registers for Ports L, G and C are cleared.
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
Pins G1 and G2 currently do not have any alternate func-
tions.
11
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Functional Description (Continued)
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
TL/DD/10802–6
t
RC
5X Power Supply Rise Time
FIGURE 4. Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 5 shows the three clock oscillator configurations.
A. CRYSTAL OSCILLATOR
The device can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.
Table I shows the component values required for various
standard crystal values.
B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is avail-
able as a general purpose input and/or HALT restart con-
trol.
TL/DD/10802–7
FIGURE 5. Crystal and R-C Connection Diagrams
OSCILLATOR MASK OPTIONS
C. R/C OSCILLATOR
The device can be driven by clock inputs between DC and
10 MHz.
CKI is configured as a single pin RC controlled Schmitt trig-
ger oscillator. CKO is available as a general purpose input
and/or HALT restart control.
e
TABLE I. Crystal Oscillator Configuration, T
25 C
§
A
R1
R2
C1
C2
CKI Freq
(MHz)
Conditions
(kX)
(MX)
(pF)
(pF)
e
5V
0
0
1
1
1
30
30
30–36
30–36
10
4
V
CC
e
V
CC
2.5V
e
5V
5.6
200
100–150
0.455
V
CC
e
TABLE II. RC Oscillator Configuration, T
25 C
§
A
R
C
CKI Freq.
(MHz)
Instr. Cycle
Conditions
(kX)
(pF)
(ms)
e
e
e
3.3
5.6
6.8
82
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
V
CC
V
CC
V
CC
5V
5V
5V
100
100
s
s
s
s
C 200 pF.
Note: (R/C Oscillator Configuration): 3k
R
200k, 50 pF
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12
Functional Description (Continued)
The device has three mask options for configuring the clock
input. The CKI and CKO pins are automatically configured
upon selecting a particular option.
ENI and ENTI bits select external and timer interrupt re-
spectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.
e
falling edge). The user can get an interrupt on both
Ð Crystal (CKI/10); CKO for crystal configuration
Ð External (CKI/10); CKO available as G7 input
Ð R/C (CKI/10); CKO available as G7 input
IEDG selects the external interrupt edge (0
e
rising edge,
1
rising and falling edges by toggling the state of IEDG bit
after each interrupt.
G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode.
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
HALT MODE
The device supports a power saving mode of operation:
HALT. The controller is placed in the HALT mode by setting
the G7 data bit, alternatively the user can stop the clock
input. In the HALT mode all internal processor activities in-
cluding the clock oscillator are stopped. The fully static ar-
chitecture freezes the state of the controller and retains all
information until continuing. In the HALT mode, power re-
quirements are minimal as it draws only leakage currents
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address 00FFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main pro-
gram: RET, RETSK or RETI. Either one of the three instruc-
tions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruc-
tion additionally sets the GIE bit to re-enable further inter-
rupts.
and output current. The applied voltage (V ) may be de-
CC
creased down to Vr (minimum RAM retention voltage) with-
out altering the state of the machine.
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
microcontroller and starts executing from the address
0000H. A low to high transition on the CKO pin (only if the
external or R/C clock option selected) causes the micro-
controller to continue with no reinitialization from the ad-
dress following the HALT instruction. This also resets the
G7 data bit.
INTERRUPTS
There are three interrupt sources, as shown below.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
A maskable interrupt on external G0 input (positive or nega-
tive edge sensitive under software control)
A maskable interrupt on timer underflow or timer capture
A non-maskable software/error interrupt on opcode zero
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset
but an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid
this scenario, the user should always use a two, three or four cycle
instruction to reset interrupt enable bits.
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
13
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Functional Description (Continued)
TL/DD/10802–8
FIGURE 6. Interrupt Block Diagram
DETECTION OF ILLEGAL CONDITIONS
TABLE III
SL0
The device contains a hardware mechanism that allows it to
detect illegal conditions which may occur from coding er-
rors, noise and ‘brown out’ voltage drop situations. Specifi-
cally it detects cases of executing out of undefined ROM
area and unbalanced stack situations.
SL1
SK Cycle Time
0
0
1
0
1
x
2t
C
4t
C
8t
C
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents. The opcode for a software interrupt is
also ‘00’. Thus a program accessing undefined ROM will
cause a software interrupt.
where,
is the instruction cycle clock.
t
C
MICROWIRE/PLUS OPERATION
Reading an undefined RAM location returns an FF (hexade-
cimal). The subroutine stack grows down for each subrou-
tine call. By initializing the stack pointer to the top of RAM,
the first unbalanced return instruction will cause the stack
pointer to address undefined RAM. As a result the program
will attempt to execute from FFFF (hexadecimal), which is
an undefined ROM location and will trigger a software inter-
rupt.
Setting the BUSY bit in the PSW register causes the MI-
CROWIRE/PLUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The devoce may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 8 shows how
two COP880C microcontrollers and several peripherals may
be interconnected using the MICROWIRE/PLUS arrange-
ment.
MICROWIRE/PLUSTM
Master MICROWIRE/PLUS Operation
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with any of National
Semiconductor’s MICROWIRE peripherals (i.e. A/D con-
verters, display drivers, EEPROMS, etc.) and with other mi-
crocontrollers which support the MICROWIRE/PLUS inter-
face. It consists of an 8-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK).Figure 7 shows the block diagram of the MICRO-
WIRE/PLUS interface.
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE/
PLUS Master always initiates all data exchanges. (See Fig-
ure 8). The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table IV
summarizes the bit settings required for Master mode of
operation.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS interface with the internal clock source is called the
Master mode of operation. Similarly, operating the MICRO-
WIRE/PLUS interface with an external shift clock is called
the Slave mode of operation.
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table IV sum-
marizes the settings required to enter the Slave mode of
operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS ,
the MSEL bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SL0 and SL1, in the
CNTRL register. Table III details the different clock rates
that may be selected.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated. (See Figure 8.)
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14
Functional Description (Continued)
TABLE IV
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the regis-
ter R1 gets automatically reloaded into the timer which con-
tinues to count down. The timer underflow can be pro-
grammed to interrupt the microcontroller. A bit in the control
register CNTRL enables the TIO (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure 9.)
G4
G5
G4
G5
G6
Config. Config.
Operation
Fun.
Fun. Fun.
Bit
1
Bit
1
SO
Int. SK SI MICROWIRE Master
0
1
TRI-STATE Int. SK SI MICROWIRE Master
SO Ext. SK SI MICROWIRE Slave
TRI-STATE Ext. SK SI MICROWIRE Slave
1
0
0
0
MODE 2. EXTERNAL COUNTER
TIMER/COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt. (SeeFigure 9)
The device has a powerful 16-bit timer with an associated
16-bit register enabling them to perform extensive timer
functions. The timer T1 and its register R1 are each orga-
nized as two 8-bit read/write registers. Control bits in the
register CNTRL allow the timer to be started and stopped
under software control. The timer-register pair can be oper-
ated in one of three possible modes. Table V details various
timer operating modes and their requisite control settings.
MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external fre-
quencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occur-
rence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge. (See Figure 10.)
TL/DD/10802–9
FIGURE 7. MICROWIRE/PLUS Block Diagram
TL/DD/10802–10
FIGURE 8. MICROWIRE/PLUS Application
15
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Functional Description (Continued)
TABLE V. Timer Operating Modes
CNTRL
Bits
Timer
Counts
On
Operation Mode
T Interrupt
7 6 5
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
External Counter W/Auto-Load Reg.
External Counter W/Auto-Load Reg.
Not Allowed
Timer Underflow
Timer Underflow
Not Allowed
TIO Pos. Edge
TIO Neg. Edge
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Timer W/Auto-Load Reg.
Timer W/Auto-Load Reg./Toggle TIO Out
Timer W/Capture Register
Timer W/Capture Register
Timer Underflow
Timer Underflow
TIO Pos. Edge
TIO Neg. Edge
t
C
t
C
t
C
t
C
TIMER PWM APPLICATION
Figure 11 shows how a minimal component D/A converter
can be built out of the Timer-Register pair in the Auto-Re-
load mode. The timer is placed in the ‘‘Timer with auto re-
load’’ mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruc-
tion cycle rate. The underflow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily gener-
ated.
TL/DD/10802–11
FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram
TL/DD/10802–13
TL/DD/10802–12
FIGURE 11. Timer Application
FIGURE 10. Timer Capture Mode Block Diagram
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16
RELATIVE
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
b a
location. JP has a range of from 31 to 32 to allow a one
1 is implemented by a NOP instruc-
The Timer and MICROWIRE/PLUS control register contains
the following bits:
a
byte relative jump (JP
tion). There are no ‘pages’ when using JP, all 15 bits of PC
are used.
SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by
IEDG
External interrupt edge polarity select
e
e
falling edge)
(0
rising edge, 1
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
MSEL
TRUN
TC3
Enable MICROWIRE/PLUS functions SO and
SK
e
e
Start/Stop the Timer/Counter (1
stop)
run, 0
Address
Contents
e
Timer input edge polarity select (0
e
rising
00 to 6F On Chip RAM Bytes
edge, 1
falling edge)
70 to 7F Unused RAM Address Space (Reads as all Ones)
TC2
TC1
Selects the capture mode
Selects the timer mode
80 to BF Expansion Space for future use
C0 to CF Expansion Space for I/O and Registers
D0 to DF On Chip I/O and Registers
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
Port L Data Register
BIT 7
BIT 0
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE
ENI
Global interrupt enable
External interrupt enable
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
BUSY MICROWIRE/PLUS busy shifting
IPND External interrupt pending
ENTI Timer interrupt enable
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
TPND Timer interrupt pending
C
Carry Flag
HC
Half carry Flag
Port D Data Register
DD–DF Reserved for Port D
HC
Bit 7
C
TPND ENTI IPND BUSY ENI GIE
Bit 0
E0 to EF On Chip Functions and Registers
E0–E7 Reserved for Future Parts
E8
E9
EA
EB
EC
ED
EE
EF
Reserved
Addressing Modes
REGISTER INDIRECT
MICROWIRE/PLUS Shift Register
Timer Lower Byte
Timer Upper Byte
This is the ‘‘normal’’ mode of addressing. The operand is
the memory addressed by the B register or X register.
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
F0 to FF On Chip RAM Mapped as Registers
IMMEDIATE
FC
FD
FE
X Register
SP Register
B Register
The instruction contains an 8-bit immediate field as the op-
erand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.
This is a register indirect mode that automatically incre-
ments or decrements the B or X register after executing the
instruction.
17
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Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
Symbols
[
[
]
]
X
A
8-bit Accumulator register
8-bit Address register
B
Memory indirectly addressed by B register
Memory indirectly addressed by X register
B
[
[
]
]
X
8-bit Address register
Mem Direct address memory or
MemI Direct address memory or
Imm 8-bit Immediate data
B
B
SP
PC
PU
PL
C
8-bit Stack pointer register
15-bit Program counter register
upper 7 bits of PC
or Immediate data
Reg
Register memory: addresses F0 to FF (Includes B, X
and SP)
lower 8 bits of PC
Bit
Bit number (0 to 7)
Loaded with
1-bit of PSW register for carry
Half Carry
w
Ý
HC
GIE
Exchanged with
1-bit of PSW register for global interrupt enable
Instruction Set
a
a
ADD
ADC
add
add with carry
w
MemI
MemI
Half Carry
A w A
w
A
w
w
Carry
Carry
a
C, C
A
HC
a
Half Carry
a
SUBC
subtract with carry
A
w
A
MemI C, C
HC w
w
A w A and MemI
AND
OR
Logical AND
Logical OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
Logical Exclusive-OR
IF equal
A
Compare A and MemI, Do next if A
A w AA xoor rMMeemmI I
e
l
MemI
Compare A and MemI, Do next if A MemI
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit
i
Do next if lower 4 bits of B Imm
b
Reg 1, skip if Reg goes to 0
Reg w
1 to bit,
e
Mem (bit 0 to 7 immediate)
RBIT
IFBIT
Reset bit
If bit
0 to bit,
Mem
If bit,
Mem is true, do next instr.
X
LD A
Exchange A with memory
Load A with memory
A
A w MemI
Ý Mem
LD mem
LD Reg
Load Direct memory Immed.
Load Register memory Immed.
w
Imm
MReegmw Imm
[
[
]
]
[
[
]
B
g
g
X
Exchange A with memory
Exchange A with memory
B
A
A
A
A
[
Ý
Ý
w
X
1)
X
X
X
((XB w B
1)
]
[
[
]
]
[
]
g
g
X
w
(B w B
X
LD A
LD A
LD M
Load A with memory
Load A with memory
B
w
B
w
1)
1)
[
]
X
Imm (B(Xw
B
1)
]
g
Load Memory Immediate
B
w
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
Clear A
Increment A
Decrement A
w
A w 0
A w A
A w A
1
a
b
1
A w ROM(PU,A)
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
A7 . . . AA47 Ý A3 . . . A0
C
A x BCD correction (follows ADC, SUBC)
x
. . .
x
A0
x
C
Swap nibbles of A
Set C
w
w
0
RC
IFC
Reset C
If C
If not C
C
If C is true, do next instruction
If C is not true, do next instruction
C w 01,, HHCC w 1
IFNC
e
w i (i
JMPL
JMP
JP
Jump absolute long
Jump absolute
PC w
PC11..0
ii (ii
15 bits, 0 to 32k)
e
r (r is 31 to 32, not 1)
12 bits)
a
b
w
a
PU,SP-2,PC
PU,SP-2,PC11.. 0
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
PC
[
[
w
PC
w PL, SP-1
]
[
]
]
JSRL
JSR
JID
SP
w
ii
]
[
w
PL, SP-1
w
w
i
PSLPw ROM(PU,A)
a
a
a
]
[
[
[
]
[
[
[
]
]
]
RET
RETSK
RETI
INTR
NOP
Return from subroutine
Return and Skip
SP 2,PL
w
w
w
[
SP ,PU
w
w
w
SP-1
]
SP 2,PL
SP ,PU
SP-1 ,Skipwnext instruction
1
]
Return from Interrupt
Generate an interrupt
No operation
SP 2,PL
[
SP ,PU
PUS,SPP--12,,PGCIEw 0FF
b
]
1
w
PL, SP
w
PSCPw PC
1
a
http://www.national.com
18
OPCODE LIST
Bits 3–0
19
http://www.national.com
Instruction Execution Time
Most instructions are single byte (with immediate address-
ing mode instruction taking two bytes).
BYTES and CYCLES per
INSTRUCTION
The following table shows the number of bytes and cycles
Most single instructions take one cycle time to execute.
for each instruction in the format of byte/cycle.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Arithmetic and Logic Instructions
[
]
B
Direct
Immed.
ADD
ADC
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
1/3
SBIT
RBIT
IFBIT
1/1
1/1
1/1
3/4
3/4
3/4
Memory Transfer Instructions
Register
Indirect Direct Immed.
Register Indirect
Auto Incr & Decr
a
b
a
b
]
, X
[
]
[
]
[
]
[
B
X
B
, B
X
X A,*
LD A,*
LD B,Imm
LD B,Imm
LD Mem,Imm
LD Reg,Imm
1/1 1/3 2/3
1/1 1/3 2/3
1/2
1/2
1/3
1/3
2/2
1/1
2/3
k
(If B 16)
l
(If B 15)
2/2
3/3
2/2
2/3
l
e
*
Memory location addressed by B or X or directly.
Instructions Using A & C
Transfer of Control Instructions
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
JMPL
JMP
JP
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
RC
IFC
IFNC
http://www.national.com
20
BYTES and CYCLES per
INSTRUCTION (Continued)
The following table shows the instructions assigned to un-
used opcodes. This table is for information only. The opera-
tions performed are subject to change without notice. Do
not use these opcodes.
Development Support
SUMMARY
iceMASTERTM: IM-COP8/400ÐFull feature in-circuit em-
#
ulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
COP8 Debug Module: Moderate cost in-circuit emulation
and development programming unit.
#
Unused
Opcode
Unused
Opcode
Instruction
Instruction
COP8 Evaluation and Programming Unit: EPU-
COP880CÐlow cost In-circuit simulation and develop-
ment programming unit.
#
60
61
62
63
67
8C
99
9F
A7
A8
NOP
NOP
NOP
NOP
NOP
RET
NOP
A9
AF
B1
B4
B5
B7
B9
BF
NOP
[
]
LD A,
C
x HBC
Assembler: COP8-DEV-IBMA. A DOS installable cross
development Assembler, Linker, Librarian and Utility
Software Development Tool Kit.
#
NOP
NOP
[
NOP
]
X A,
X
C Compiler: COP8C. A DOS installable cross develop-
ment Software Tool Kit.
#
[
]
Ý
[
]
LD B ,
i
LD A,
X
OTP/EPROM Programmer Support: Covering needs
from engineering prototype, pilot production to full pro-
duction environments.
#
[
]
B
X A,
NOP
Option List
The mask programmable options are listed out below. The
options are programmed at the same time as the ROM pat-
tern to provide the user with hardware flexibility to use a
variety of oscillator configuration.
OPTION 1: CKI INPUT
e
e
e
1 Crystal (CKI/10) CKO for crystal con-
figuration
2 External (CKI/10) CKO available as G7
input
3 R/C
(CKI/10) CKO available as G7
input
OPTION 2: BONDING
e
e
e
e
1 44-Pin PLCC
2 40-Pin DIP
3 28-Pin SO
4 28-Pin DIP
The following option information is to be sent to National
along with the EPROM.
Option Data
Option 1 Value is: CKI Input
Ð
Option 2 Value is: COP Bonding
Ð
21
http://www.national.com
Development Support (Continued)
Watch windows, content updated automatically at each
execution break.
#
#
#
iceMASTER (IM) IN-CIRCUIT EMULATION
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool developed and marketed by Meta-
Link Corporation to support the whole COP8 family of prod-
ucts. National is a resale vendor for these products.
Instruction by instruction memory/register changes dis-
played on source window when in single step operation.
Single base unit and debugger software reconfigurable to
support the entire COP8 family; only the probe personali-
ty needs to change. Debugger software is processor cus-
tomized, and reconfigured from a master model file.
See Figure 12 for configuration.
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing, test-
ing and maintaining product:
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
#
Real-time in-circuit emulation; full 2.4V–5.5V operation
range, full DC-10 MHz clock. Chip options are program-
mable or jumper selectable.
#
Halt/Idle mode notification.
#
#
On-line HELP customized to specific processor using
master model file.
Direct connection to application board by package com-
patible socket or surface mount assembly.
#
Includes a copy of COP8-DEV-IBMA assembler and link-
er SDK.
#
Full 32 kbyte of loadable programming space that over-
#
IM Order Information
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on
the probe as necessary.
Base Unit
Full 4k frame synchronous trace memory. Address, in-
IM-COP8/400-1
iceMASTER base unit,
110V power supply
#
struction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), assem-
bly or mixed.
IM-COP8/400-2
iceMASTER base unit,
220V power supply
A full 64k hardware configurable break, trace on, trace
off control, and pass count increment events.
#
iceMASTER Probe
MHW-880C20DWPC
MHW-880C28DWPC
MHW-880CJ40DWPC
MHW-880CJ44PWPC
DIP to SO Adapters
MHW-SOIC20
Tool set integrated interactive symbolic debuggerÐsup-
ports both assembler (COFF) and C Compiler (.COD)
linked object formats.
#
20 DIP
28 DIP
40 DIP
44 PLCC
Real time performance profiling analysis; selectable
bucket definition.
#
20 SO
28 DIP
MHW-SOIC28
TL/DD/10802–24
FIGURE 12. COP8 iceMASTER Environment
http://www.national.com
22
Development Support (Continued)
iceMASTER DEBUG MODULE (DM)
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
#
The iceMASTER Debug Module is a PC based, combination
in-circuit emulation tool and COP8 based OTP/EPROM pro-
gramming tool developed and marketed by MetaLink Corpo-
ration to support the whole COP8 family of products. Nation-
al is a resale vendor for these products.
Halt/Idle mode notification.
#
#
Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
See Figure 13 for configuration.
Programming of 44 PLCC and 68 PLCC parts requires
external programming. adapters.
#
The iceMASTER Debug Module is a moderate cost devel-
opment tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product fami-
lies. Summary of features is as follows:
Includes wallmount power supply.
#
#
On-board VPP generator from 5V input or connection to
external supply supported. Rquires VPP level adjustment
per the family programming specification (correct level is
provided on an on-screen pop-down display).
Real-time in-circuit emulation; full operating voltage
range operation, full DC-10 MHz clock.
#
On-line HELP customized to specific processor using
master model file.
#
#
All processor I/O pins can be cabled to an application
development board with package compatible cable to
socket and surface mount assembly.
#
Includes a copy of COP8-DEV-IBMA assembler and link-
er SDK.
Full 32 kbyte of loadable programming space that over-
#
DM Order Information
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
Debug Model Unit
COP8-DM/880C
Cable Adapters
DM-COP8/20D
100 frames of synchronous trace memory. The display
#
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
20 DIP
28 DIP
40 DIP
44 PLCC
DM-COP8/28D
Configured break points; uses INTR instruction which is
modestly intrusive.
#
DM-COP8/40D
SoftwareÐonly supported features are selectable.
#
#
DM-COP8/44P
Tool set integrated interactive symbolic debuggerÐsup-
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
DIP to SO Adapters
DM-COP8/20D-SO
DM-COP8/28D-SO
20 SO
28 SO
Instruction by instruction memory/register changes dis-
played when in single step operation.
#
Debugger software is processor customized, and recon-
figured from a master model file.
#
TL/DD/10802–25
FIGURE 13. COP8-DM Environment
23
http://www.national.com
Development Support (Continued)
Tool set integrated interactive symbolic debuggerÐsup-
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
#
iceMASTER EVALUATION PROGRAMMING UNIT (EPU)
The iceMASTER EPU-COP880C is a PC based, in-circuit
simulation tool to support the feature family COP8 products.
Instruction by instruction memory/register changes dis-
played when in single step operation.
#
#
#
#
See Figure 14 for configuration.
The simulation capability is a very low cost means of evalu-
ating the general COP8 architecture. In addition, the EPU
has programming capability, with added adapters, for pro-
gramming the whole COP8 product family of OTP and
EPROM products. The product includes the following fea-
tures:
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
Halt/Idle mode notification. Restart requires special han-
dling.
Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Only a 40 ZIF
socket is available on the EPU unit. Adapters are avail-
able for other part package configurations.
Non-real-time in-circuit simulation. Program overlay
#
memory is PC resident; instructions are downloaded over
RS-232 as executed. Approximate performance is
20 kHz.
Integral wall mount power supply provides 5V and devel-
ops the required V to program parts.
PP
#
#
Includes a 40 pin DIP cable adapter. Other target pack-
ages are not supported. All processor I/O pins are ca-
bled to the application development environment.
#
Includes a copy of COP8-DEV-IBMA assembler, linker
SDK.
EPU Order Information
Full 32 kbyte of loadable programmable space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
Evaluation Programming Unit
EPU-COP880C Evaluation Programming Unit
with debugger and programmer
control software with 40 ZIF
programming socket.
On-chip timer and WATCHDOG execution are not well
synchronized to the instruction simulation.
#
100 frames of synchronous trace memory. The display
#
General Programming Adapters
can be HLL source (e.g., C source), assembly or mixed.
The most recent history prior to a break is available in the
trace memory.
COP8-PGMA-DS
28 and 20 DIP and SOIC adapter
COP8-PGMA-DS44P 28 and 20 DIP and SOIC plus 44
PLCC adapter
Up to eight software configured break points; uses INTR
instruction which is modestly intrusive.
#
Common look-feel debugger software across all Meta-
Link productsÐonly supported features are selectable.
#
TL/DD/10802–26
FIGURE 14. EPU-COP8 Tool Environment
http://www.national.com
24
Development Support (Continued)
COP8 ASSEMBLER/LINKER SOFTWARE
DEVELOPMENT TOOL KIT
COP8 C COMPILER
A C Compiler is developed and marketed by Byte Craft Lim-
ited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embed-
ded configuration of the COP8 family of products.
National Semiconductor offers a relocateable COP8 macro
cross assembler, linker, librarian and utility software devel-
opment tool kit. Features are summarized as follows:
Basic and Feature Family instruction set by ‘‘device’’
type.
Features are summarized as follows:
#
ANSI C with some restrictions and extensions that opti-
mize development for the COP8 embedded application.
#
Nested macro capability.
#
Ý
BITS data type extension. Register declaration pragma
with direct bit level definitions.
Extensive set of assembler directives.
#
#
#
#
#
#
#
Supported on PC/DOS platform.
C language support for interrupt routines.
#
#
Generates National standard COFF output files.
Expert system, rule based code geration and optimiza-
tion.
Integrated Linker and Librarian.
Integrated utilities to generate ROM code file outputs.
Performs consistency checks against the architectural
definitions of the target COP8 device.
#
DUMPCOFF utility.
This product is integrated as a part of MetaLink tools as a
development kit, fully supported by the MetaLink debugger.
It may be ordered separately or it is bundled with the Meta-
Link products at no additional cost.
Generates program memory code.
#
#
Supports linking of compiled object or COP8 assembled
object formats.
Global optimization of linked code.
#
#
Order Information
Symbolic debug load format fully sourced level support-
ed by the MetaLink debugger.
Assembler SDK:
INDUSTRY WIDE OTP/EPROM PROGRAMMING
SUPPORT
COP8-DEV-IBMA Assembler SDK on installable 3.5
×
PC/DOS Floppy Disk Drive format.
Periodic upgrades and most recent
version is available on National’s
BBS and Internet.
Programming support, in addition to the MetaLink develop-
ment tools, is provided by a full range of independent ap-
proved vendors to meet the needs from the engineering
laboratory to full production.
Approved List
North
Manufacturer
Europe
Asia
America
a
a
a
a
BP
(800) 225-2102
49-8152-4183
852-234-16611
852-2710-8121
Microsystems
(713) 688-4600
49-8856-932616
Fax: (713) 688-0920
a
Data I/O
HI–LO
(800) 426-1045
44-0734-440011
Call
(206) 881-6444
North America
Fax: (206) 882-1043
a
886-2-764-0215
(510) 623-8860
Call Asia
a
Fax: 886-2-756-6403
a
Fax: 0-1226-370-434
ICE
(800) 624-8949
(919) 430-7915
44-1226-767404
Technology
a
a
a
MetaLink
(800) 638-2423
49-80 9156 96-0
852-737-1800
a
Fax: 49-80 9123 86
(602) 926-0797
Fax: (602) 693-0681
a
Systems
General
(408) 263-6667
41-1-9450300
886-2-917-3005
a
Fax: 886-2-911-1283
Needhams
(916) 924-8037
Fax: (916) 924-8065
25
http://www.national.com
Development Support (Continued)
AVAILABLE LITERATURE
DIAL-A-HELPER via WorldWide Web Browser
ftp://nscmicro.nsc.com
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and Na-
tional’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
National Semiconductor on the WorldWide Web
See us on the WorldWide Web at: http://www.national.com
CUSTOMER RESPONSE CENTER
Complete product information and technical support is avail-
able from National’s customer response centers.
DIAL-A-HELPER SERVICE
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Infor-
mation System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the Inter-
net via standard FTP client application or as an FTP site on
the Internet using a standard Internet browser such as Net-
scape or Mosaic.
CANADA/U.S.: Tel:
email:
(800)272-9959
@
support tevm2.nsc.com
@
europe.support nsc.com
EUROPE:
email:
a
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
Tel:
49 (0) 180-530 85 85
49 (0) 180-532 78 32
49 (0) 180-532 93 58
49 (0) 180-534 16 80
81-043-299-2309
The Dial-A-Helper system provides access to an automated
information storage and retrieval system . The system capa-
bilities include a MESSAGE SECTION (electronic mail,
when accessed as a BBS) for communications to and from
the Microcontroller Applications Group and a FILE SEC-
TION which consists of several file areas where valuable
application software and utilities could be found.
JAPAN:
a
S.E. ASIA:
Beijing Tel:
Shanghai Tel:
(
(
86) 10-6856-8601
DIAL-A-HELPER BBS via a Standard Modem
a
86) 21-6415-4092
Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427
a
Hong Kong Tel: ( 852) 2737-1600
a
14.4k
EUROPE:
Baud:
Set-Up:
(
49) 0-8141-351332
a
a
a
Korea Tel:
Malaysia Tel:
Singapore Tel:
Taiwan Tel:
Tel:
(
(
(
82) 2-3771-6909
60-4) 644-9061
65) 255-2226
Length:
Parity:
Stop Bit:
8-Bit
None
1
a
886-2-521-3288
Operation:
24 Hours, 7 Days
a
AUSTRALIA:
INDIA:
(
61) 3-9558-9999
91) 80-559-9467
DIAL-A-HELPER via FTP
ftp nscmicro.nsc.com
user:
password:
a
(
Tel:
anonymous
@
username yourhost.site.domain
http://www.national.com
26
Physical Dimensions inches, (millimeters)
Small Outline Molded Dual-In-Line Package (M)
Order Number COP882C-XXX/WM, COP982C-XXX/WM, COP682C-XXX/WM or COP982CH-XXX/WM
NS Package Number M20B
Small Outline Molded Dual-In-Line Package (M)
Order Number COP881C-XXX/WM, COP981C-XXX/WM, COP681C-XXX/WM or COP981CH-XXX/WM
NS Package Number M28B
27
http://www.national.com
Physical Dimensions inches, (millimeters)
Molded Dual-In-Line Package (N)
Order Number COP882C-XXX/N, COP682C-XXX/N, COP982C-XXX/N or COP982CH-XXX/N
NS Package Number N20B
Molded Dual-In-Line Package (N)
Order Number COP881C-XXX/N, COP681C-XXX/N, COP981C-XXX/N or COP981CH-XXX/N
NS Package Number N28B
http://www.national.com
28
Physical Dimensions inches, (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number COP880C-XXX/N, COP680C-XXX/N, COP980C-XXX/N or COP980CH-XXX/N
NS Package Number N40A
29
http://www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier (V)
Order Number COP880C-XXX/V, COP680C-XXX/V, COP980C-XXX/V or COP980CH-XXX/V
NS Package Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
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National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: 49 (0) 180-530 85 86
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Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2308
Fax: 81-043-299-2408
@
Email: europe.support nsc.com
a
Deutsch Tel: 49 (0) 180-530 85 85
a
English Tel: 49 (0) 180-532 78 32
a
Fran3ais Tel: 49 (0) 180-532 93 58
a
Italiano Tel: 49 (0) 180-534 16 80
http://www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
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IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20, Microcontroller
NSC
COPC912-XXX/N/NOPB
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