DAC1022LCJ [NSC]
IC PARALLEL, 8 BITS INPUT LOADING, 0.5 us SETTLING TIME, 10-BIT DAC, CDIP16, CERAMIC, DIP-16, Digital to Analog Converter;
| 型号： | DAC1022LCJ |
| 厂家： | 
National Semiconductor |
| 描述： | IC PARALLEL, 8 BITS INPUT LOADING, 0.5 us SETTLING TIME, 10-BIT DAC, CDIP16, CERAMIC, DIP-16, Digital to Analog Converter 转换器 |
| 文件： | 总14页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1996
DAC1020/DAC1021/DAC1022
10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222
12-Bit Binary Multiplying D/A Converter
General Description
The DAC1020 and the DAC1220 are, respectively, 10 and
12-bit binary multiplying digital-to-analog converters. A de-
posited thin film R-2R resistor ladder divides the reference
current and provides the circuit with excellent temperature
(note 1 of electrical characteristics). The DAC1020,
DAC1021 and DAC1022 are direct replacements for the 10-
bit resolution AD7520 and AD7530 and equivalent to the
AD7533 family. The DAC1220 and DAC1222 are direct re-
placements for the 12-bit resolution AD7521 and AD7531
family.
tracking characteristics (0.0002%/ C linearity error temper-
§
ature coefficient maximum). The circuit uses CMOS current
switches and drive circuitry to achieve low power consump-
tion (30 mW max) and low output leakages (200 nA max).
The digital inputs are compatible with DTL/TTL logic levels
as well as full CMOS logic level swings. This part, combined
with an external amplifier and voltage reference, can be
used as a standard D/A converter; however, it is also very
attractive for multiplying applications (such as digitally con-
trolled gain blocks) since its linearity error is essentially in-
dependent of the voltage reference. All inputs are protected
from damage due to static discharge by diode clamps to Va
and ground.
Features
Y
Linearity specified with zero and full-scale adjust only
Y
Non-linearity guaranteed over temperature
Y
Integrated thin film on CMOS structure
Y
10-bit or 12-bit resolution
@
Low power dissipation 10 mW 15V typ
Y
Y
Y
Y
Y
Y
s
s
25V
b
Accepts variable or fixed reference 25V
V
REF
4-quadrant multiplying capability
Interfaces directly with DTL, TTL and CMOS
This part is available with 10-bit (0.05%), 9-bit (0.10%), and
8-bit (0.20%) non-linearity guaranteed over temperature
Fast settling timeÐ500 ns typ
@
Low feedthrough errorÐ(/2 LSB 100 kHz typ
Eq
TL/H/5689–1
10-BIT D/A CONVERTERS
0 C to 70 C
Ordering Information
Temperature Range
b
40 C to 85 C
§
§
§
DAC1020LIV
§
0.05%
0.10%
0.20%
DAC1020LCN
AD7520LN,AD7530LN
AD7520KN,AD7530KN
AD7520JN,AD7530JN
DAC1020LCV
Non-
Linearity
DAC1021LCN
DAC1022LCN
Package Outline
N16A
12-BIT D/A CONVERTERS
V20A
b
a
40 C to 85 C
Temperature Range
0 C to 70 C
§
§
AD7521LN,AD7531LN
§
§
0.05%
0.20%
DAC1220LCN
DAC1222LCN
DAC1220LCJ
AD7521LD,AD7531LD
AD7521JD,AD7531JD
J18A
Non-
Linearity
AD7521JN,AD7531JN
DAC1222LCJ
Package Outline
N18A
Note. Devices may be ordered by either part number.
C
1996 National Semiconductor Corporation
TL/H/5689
RRD-B30M96/Printed in U. S. A.
http://www.national.com
Absolute Maximum Ratings (Note 5)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Ratings
Min
Max
Units
Temperature (T
)
A
DAC1020LIV, DAC1220LCJ,
DAC1222LCJ
Va to Gnd
17V
25V
40
85
C
b
a
§
DAC1020LCN, DAC1020LCV,
DAC1021LCN
g
V
to Gnd
REF
a
a
a
Va to Gnd
0
70
70
70
C
§
§
§
Digital Input Voltage Range
DAC1022LCN, DAC1220LCN
DAC1222LCN
0
0
C
a
b
DC Voltage at Pin 1 or Pin 2 (Note 3)
Storage Temperature Range
100 mV to V
C
b
a
65 C to 150 C
§
§
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
260 C
§
300 C
§
800V
ESD Susceptibility (Note 4)
Electrical Characteristics (Va 15V, V
10.000V, T
25 C unless otherwise specified)
§
e
e
e
REF
A
DAC1020, DAC1021,
DAC1022
DAC1220, DAC1222
Parameter
Conditions
Units
Min
Typ
Max
Min
Typ
Max
Resolution
10
12
Bits
k
k
T
MAX
Linearity Error
T
MIN
T
A
,
k
k
b
a
10V
V
REF
10V,
(Note 1) End Point Adjustment Only
(See Linearity Error in Definition of Terms)
DAC1020, DAC1220
10-Bit Parts
9-Bit Parts
8-Bit Parts
0.05
0.10
0.20
0.05
0.10
0.20
% FSR
% FSR
% FSR
DAC1021
DAC1022, DAC1222
s
s
b
(Notes 1 and 2)
a
a
,
Linearity Error Tempco
10V
V
REF
10V,
0.0002
0.0002 % FS/ C
§
s
s
b
(Notes 1 and 2)
Full-Scale Error
10V
V
REF
10V,
0.3
1.0
0.3
1.0
% FS
k
k
Full-Scale Error Tempco
Output Leakage Current
T
T
T
T
0.001
0.001 % FS/ C
§
MIN
(Note 2)
A
MAX
s
s
T
MIN
T
A
MAX
I
I
All Digital Inputs Low
All Digital Inputs High
200
200
200
200
nA
nA
OUT 1
OUT 2
Power Supply Sensitivity
All Digital Inputs High,
a
0.005
15
0.005
15
% FS/V
s
s
16V, (Note 2),
14V
V
(Figure 2)
V
REF
Input Resistance
10
20
10
20
kX
e
100X from 0 to 99. 95%
Full-Scale Current Settling
Time
R
L
FS
All Digital Inputs Switched
Simultaneously
500
500
ns
V
REF
Feedthrough
All Digital Inputs Low,
e
10
10
mVp-p
@
20 Vp-p 100 kHz
V
REF
J Package (Note 4)
N Package
6
2
9
5
6
2
9
5
mVp-p
mVp-p
Output Capacitance
I
All Digital Inputs Low
All Digital Inputs High
All Digital Inputs Low
All Digital Inputs High
40
200
200
40
40
200
200
40
pF
pF
pF
pF
OUT 1
I
OUT 2
http://www.national.com
2
Electrical Characteristics (Va 15V, V
10.000V, T
25 C unless otherwise specified) (Continued)
§
e
e
e
A
REF
DAC1020, DAC1021,
DAC1022
DAC1220, DAC1222
Parameter
Conditions
Units
Min
Typ
Max
Min
Typ
Max
Digital Input
(Figure 1)
k
k
k
k
Low Threshold
High Threshold
T
T
T
T
T
T
0.8
0.8
V
V
MIN
A
MAX
2.4
2.4
MIN
A
MAX
s
s
Digital Input Current
T
MIN
T
A
T
MAX
Digital Input High
Digital Input Low
1
100
1
100
b
200
mA
mA
b
b
b
50
0.2
0.6
200
50
0.2
0.6
Supply Current
All Digital Inputs High
All Digital Inputs Low
1.6
2
1.6
2
mA
mA
Operating Power Supply
Range
(Figures 1 and 2)
5
15
5
15
V
e
e
g
g
Note 1: V
10V and V
REF
1V. A linearity error temperature coefficient of 0.0002% FS for a 45 C rise only guarantees 0.009% maximum change in
§
REF
linearity error. For instance, if the linearity error at 25 C is 0.045% FS it could increase to 0.054% at 70 C and the DAC will be no longer a 10-bit part. Note,
§
§
however, that the linearity error is specified over the device full temperature range which is a more stringent specification since it includes the linearity error
temperature coefficient.
Note 2: Using internal feedback resistor as shown in Figure 3.
e
Note 3: Both I
OUT 1
0.005% linearity error will be introduced.
and I
must go to ground or the virtual ground of an operational amplifier. If V
10V, every millivolt offset between I
or I
,
OUT 2
OUT 2
REF
OUT 1
Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 5: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 6: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
b
T
, i , and the ambient temepature, T . The maximum
JMAX JA
)/i or the number given in the Absolute Maximum Ratings, whichever is lower. For this
A JA
A
e
allowable power dissipation at any temperature is P
(T
D
JMAX
e
120 C/W, for the N16 this number is 125 C/W, and for the V20 this number is 95 C/W.
device, T
JMAX
125 C, and the typical junction-to-ambient thermal resistance of the J18 package when board mounted is 85 C/W. For the N18 package, i is
§
§
JA
§
§
§
Typical Performance Characteristics
TL/H/5689–2
FIGURE 1. Digital Input Threshold vs
Ambient Temperature
FIGURE 2. Gain Error Variation vs Va
3
http://www.national.com
Typical Applications
The following applications are also valid for 12-bit systems
using the DAC1220 and 2 additional digital inputs.
Operational Amplifier V Adjust (Figure 3)
OS
Connect all digital inputs, A1–A10, to ground and adjust the
g
1
is less than 10V, a finer
potentiometer to bring the op amp V
pin to within
OUT
Operational Amplifier Bias Current (Figure 3)
mV from ground potential. If V
REF
adjustment is required. It is helpful to increase the reso-
The op amp bias current, I , flows through the 15k internal
b
feedback resistor. BI-FET op amps have low I and, there-
V
OS
b
lution of the V
adjust procedure by connecting a 1 kX
OS
resistor between the inverting input of the op amp to
ground. After V has been adjusted, remove the 1 kX.
c
strongly recommended for the DAC1020 applications.
fore, the 15k
I error they introduce is negligible; they are
b
OS
V
OS
Considerations
Full-Scale Adjust (Figure 4)
The output impedance, R , of the DAC is modulated by
OUT
the digital input code which causes a modulation of the op-
Switch high all the digital inputs, A1–A10, and measure the
op amp output voltage. Use a 500X potentiometer, as
erational amplifier output offset. It is therefore recommend-
E
c
shown, to bring
1023/1024.
V
to a voltage equal to V
REF
ll OUTll
ed to adjust the op amp V . R
OS OUT
is 15k if more than 4
E
digital inputs are high; R
is high, and R
is 45k if a single digital input
approaches infinity if all inputs are low.
OUT
OUT
SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER
Circuit Settling
Circuit Small
Signal BW
Op Amp Family
C
F
R
i
P
V
W
Time, t
s
LF357
LF356
LF351
LM741
10 pF
22 pF
24 pF
0
2.4k
%
%
25k
25k
10k
10k
Va
Va
Vb
Vb
1.5 ms
3 ms
1M
0.5M
4 ms
0.5M
%
40 ms
200 kHz
TL/H/5689–3
A1
A2
4
A3
8
A10
e b
s
a
a
a
# # #
V
V
REF
OUT
2
1024
#
J
s
b
10V
V
REF
10V
1023
1024
s
s
b
0
V
V
REF
OUT
e
where A
1 if the A digital input is high
N
N
e
A
N
0 if the A digital input is low
N
FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying
Configuration (Digital Attenuator)
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4
Typical Applications (Continued)
FIGURGain)
A1
2
A2
4
A3
8
A10
TL/H/5689–4
e b
a
a
a
# # #
V
V
V
OUT 1
OUT2
REF
1024
#
J
A1
2
A2
4
A3
8
A10
B1
2
B2
4
B3
8
B10
e
a
a
a
c
a
a
a
# # #
V
REF
# # #
1024
1024
#
J #
J
where V
can be an AC signal
REF
FIGURE 6. Precision Analog-to-Digital Multiplier
5
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Typical Applications (Continued)
COMPLEMENTARY OFFSET BINARY
(BIPOLAR) OPERATION
DIGITAL INPUT
V
OUT
a
c
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
V
REF
1022/1024
V
REF
c
V
2/1024
REF
0
b
b
c
2/1024
V
REF
V
(1022/1024)
REF
Note that:
V
1023
1024
REF
a
e
c
I
#
I
OUT 2
OUT 1
R
# J
LADDER
By doubling the output range we get half the
resolution
#
#
TL/H/5689–5
A1
2
A2
4
A10
1
e b
a
a
a
b
V
V
REF
# # #
OUT
The 10M resistor, adds a 1 LSB ‘‘thump’’, to
allow full offset binary operation where the out-
put reaches zero for the half-scale code. If
symmetrical output excursions are required,
omit the 10M resistor.
1024 1024
#
J
e
e
a
where: AN
AN
1 if A input is high
N
b
1 if A input is low
N
FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration
Operational Amplifiers V Adjust (Figure 7)
OS
Gain Adjust (Full-Scale Adjust)
a) Switch all the digital inputs high; adjust the V potenti-
OS
ometer of op amp B to bring its output to a value equal
Assuming that the external 10k resistors are matched to
better than 0.1%, the gain adjust of the circuit is the same
with the one previously discussed.
b
to (V
/1024) (V).
REF
b) Switch the MSB high and the remaining digital inputs
low. Adjust the V potentiometer of op amp A, to bring
OS
its output value to within a 1 mV from ground potential.
k
mentioned in the previous application.
For V
REF
10V, a finer adjust is necessary, as already
TL/H/5689–6
b
R2
R1
A
V
TRUE OFFSET BINARY OPERATION
b
e
a
b
e
e
R4
R3
(2A
1) R,
,
#
#
V
b
b
A
1
V
DIGITAL INPUT
V
OUT
V
OUT(PEAK)
b
e
e
20k
R1 R2
ll
R; A
, R
V
V
c
REF
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
V
REF
1022/1024
0
b
10V: A
V
j
e
e
5V
g
Example: V
2V, V
(swing)
REF
OUT
e
e
e
e
0.2R then R2 0.25R,
Then R4
9R, R1
0.8 R2. If R1
b
V
REF
e
R3
0.64R
e
t
1.8 ms
s
FIGURE 9. Bipolar Configuration with
Increased Output Swing
use LM336 for a voltage reference
FIGURE 8. Bipolar Configuration with a Single Op Amp
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6
Typical Applications (Continued)
FIGier)
TL/H/5689–7
A1
2
A2
4
A10
1024
A10
a
a
a
a
a
a
. . .
. . .
b
1023
N
e
e
s
V
V
REF
or V
V
OUT
OUT
REF
A1
2
A2
4
N
#
J
1024
%
–
s
e
where: 0
N
1023
e
e
N
N
.
0 for A
all zeros
N
e
e
1 for A10
1, A1–A9
0
.
.
e
e
all 1’s
N
1023 for A
N
FIGURE 11. Digitally controlled Amplifier-Attenuator
7
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Typical Applications (Continued)
TL/H/5689–8
f
CLK
j
e
Output frequency
; f
2 kHz
b
10V peak
#
MAX
512
e
Output voltage range
0V
#
#
#
#
k
THD
0.2%
Excellent amplitude and frequency stability with temperature
Low pass filter shown has a 1 kHz corner (for output frequencies below 10 Hz,
filter corner should be reduced)
Any periodic function can be implemented by modifying the contents of the look
up table ROM
#
#
No start up problems
FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM
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8
Typical Applications (Continued)
MM74C00 Ð N
MM74C32 Ð O
MM74C74 Ð D
MM74C193 Ð
TL/H/5689–9
Binary up/down counter digitally ‘‘ramps’’ the DAC
output
#
Can stop counting at any desired 10-bit input code
Senses up or down count overflow and automatically
reverses direction of count
#
#
FIGURE 13. A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits
9
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Definition of Terms
Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the D/A output. It is directly
related to the number of switches or bits within the D/A. For
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the D/A
full-scale output.
10
example, the DAC1020 has 2 or 1024 steps while the
12
DAC1220 has 2 or 4096 steps. Therefore, the DAC1020
Settling Time: Full-scale settling time requires a zero to full-
scale or full-scale to zero output change. Settling time is the
time required from a code transition until the D/A output
has 10-bit resolution, while the DAC1220 has 12-bit resolu-
tion.
g
reaches within (/2 LSB of final output value.
Full-Scale Error: Full-scale error is a measure of the output
error between an ideal D/A and the actual device output.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
D/A transfer characteristic. It is measured after calibrating
b
Ideally, for the DAC1020 full-scale is V
V
1 LSB. For
REF
operation,
e
10.0000VÐ9.8 mV 9.9902V. Full-scale error is ad-
10V
and
unipolar
V
for zero (see V
OS
adjust in typical applications) and full-
REF
FULL-SCA-
e
e
justable to zero as shown in Figure 5.
scale. Linearity error is a design parameter intrinsic to the
device and cannot be externally adjusted.
LE
TL/H/5689–10
a
(a) End point test after zero and full-scale adjust.
b1
b2
(b) By shifting the full-scale calibration on of the DAC of
Figure (b1) we could pass the ‘‘best straight line’’ (b2)
The DAC has 1 LSB linearity error.
g
test and meet the (/2 linearity error specification.
Note. (a), (b1) and (b2) above illustrate the difference between ‘‘end point’’ National’s linearity test (a) and ‘‘best straight line’’ test. Note that both devices in (a) and
g
(b2) meet the (/2 LSB linearity error specification but the end point test is a more ‘‘real life’’ way of characterizing the DAC.
Connection Diagrams
DAC102X
Dual-In-Line Package
DAC1020
PLCC Package
DAC122X
Dual-In-Line Package
TL/H/5689–12
TL/H/5689–13
TL/H/5689–11
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10
11
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Physical Dimensions inches (millimeters) unless otherwise noted
Cavity Dual-In-Line Package (J)
Order Number DAC1220LCJ or DAC1222LCJ
NS Package Number J18A
Molded Dual-In-Line Package (N)
Order Number DAC1020LCN, DAC1021LCN or DAC1022LCN
NS Package Number N16A
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12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number DAC1220LCN, DAC1221LCN or DAC1222LCN
NS Package Number N18A
13
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Plastic Leaded Chip Carrier (V)
Order Number DAC1020LCV or DAC1020LIV
NS Package Number V20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: 49 (0) 180-530 85 86
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2308
Fax: 81-043-299-2408
@
Email: europe.support nsc.com
a
Deutsch Tel: 49 (0) 180-530 85 85
a
English Tel: 49 (0) 180-532 78 32
a
Fran3ais Tel: 49 (0) 180-532 93 58
a
Italiano Tel: 49 (0) 180-534 16 80
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
DAC1022LJ
IC PARALLEL, 8 BITS INPUT LOADING, 0.5 us SETTLING TIME, 10-BIT DAC, CDIP16, CERAMIC, DIP-16, Digital to Analog Converter
NSC
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