DM74LS160AN [NSC]
Synchronous Presettable BCD Decade Counters; 同步可预置BCD十进制计数器
| 型号： | DM74LS160AN |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous Presettable BCD Decade Counters |
| 文件： | 总9页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1992
54LS160A/DM74LS160A, 54LS162A/DM74LS162A
Synchronous Presettable BCD Decade Counters
General Description
Features
Y
Synchronous counting and loading
The ’LS160 and ’LS162 are high speed synchronous dec-
ade counters operating in the BCD (8421) sequence. They
are synchronously presettable for application in programma-
ble dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming synchro-
nous multistage counters. The ’LS160 has an asynchronous
Master Reset input that overrides all other inputs and forces
the outputs LOW. The ’LS162 has a Synchronous Reset
input that overrides counting and parallel loading and allows
all outputs to be simultaneously reset on the rising edge of
the clock.
Y
High speed synchronous expansion
Y
Typical count rate of 35 MHz
Y
Fully edge triggered
Connection Diagram
Dual-In-Line Package
TL/F/10177–1
*MR for ’LS160
*SR for ’LS162
Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB,
54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM,
DM74LS160AN, DM74LS162AM or DM74LS162AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Logic Symbol
Pin
Description
Names
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset
Input (Active LOW)
CP
MR (’160)
SR (’162)
Synchronous Reset
Input (Active LOW)
P0–P3
PE
Parallel Data Inputs
Parallel Enable Input
(Active LOW)
Q0–Q3
TC
Flip-Flop Outputs
TL/F/10177–2
e
e
V
Pin 16 *MR for ’LS160
Pin 8 *SR for ’LS162
Terminal Count Output
CC
GND
C
1995 National Semiconductor Corporation
TL/F/10177
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
54LS
DM74LS
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
54LS160A/162A
DM74LS160A/162A
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
Nom
Max
V
V
V
Supply Voltage
5
5.5
4.75
2
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time, HIGH or LOW
IH
0.7
0.8
V
IL
b
b
0.4
I
I
0.4
mA
mA
OH
OL
4
8
b
T
A
55
125
0
70
C
§
t (H)
s
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
t (L)
s
P
n
to CP
20
t (H)
h
Hold Time, HIGH or LOW
P to CP
n
0.0
0.0
0.0
0.0
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
PE to CP
20
20
20
20
t (L)
s
t (H)
h
Hold Time, HIGH or LOW
PE to CP
0
0
0
0
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
CEP, CET or SR to CP
20
20
20
20
t (L)
s
t (H)
h
Hold Time, HIGH or LOW
CEP, CET or SR to CP
0
0
0
0
t (L)
h
t
t
(H)
(L)
CP Pulse Width,
HIGH or LOW
15
25
15
25
w
w
t
(L)
MR Pulse Width
LOW (’160)
w
15
20
15
20
t
Recovery Time
MR to CP (’160)
rec
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
Max,
V
V
I
CC
I
High Level Output
Voltage
V
V
54LS
DM74
54LS
DM74
DM74
2.5
2.7
OH
CC
OH
e
Max
IL
e
e
Max,
V
OL
Low Level Output
Voltage
V
V
Min, I
0.4
CC
OL
e
Min
IH
0.5
0.4
V
e
e
Min
I
4 mA, V
CC
OL
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
CC
A
2
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
@
Input Current Max
e
e
e
e
e
e
I
I
I
V
V
V
Max, V
Max, V
Max, V
7V
Other
PE, CET Inputs
Other
0.1
0.2
20
I
CC
CC
CC
I
I
I
mA
Input Voltage
High Level Input Current
2.7V
IH
IL
mA
PE, CET Inputs
40
b
b
b
Low Level Input Current
0.4V Inputs
54LS
0.4
1.6
mA
DM74
PE, CET Inputs
0.8
mA
mA
e
CC
b
b
b
b
I
Short Circuit
V
Max
54LS
20
20
100
100
OS
Output Current
(Note 2)
DM74
e
CC
e
GND
I
I
Supply Current with
Outputs HIGH
V
Max, PE
CCH
CCL
31
31
mA
mA
e
e
4.5V
CP
L, Other Inputs
e
e
GND
Supply Current with
Outputs LOW
V
CC
Max, V
IN
e
CP
L
e a
e a
25 C
Switching Characteristics V
5.0V, T
§
CC
A
e
e
R
2 kX
L
Symbol
Parameter
C
L
15 pF
Units
Min
25
Max
f
Maximum Clock Frequency
MHz
ns
max
t
t
Propagation Delay
CP to TC
25
21
PLH
PHL
t
t
Propagation Delay
24
27
PLH
ns
ns
ns
CP to Q
PHL
n
t
t
Propagation Delay
CET to TC
14
23
PLH
PHL
t
Propagation Delay
PHL
28
MR to Q (’160)
n
Functional Description
The ’LS160 and ’LS162 count modulo-10 in the BCD (8421)
sequence. From state 9 (HLLH) they increment to state 0
(LLLL). The ’161 and ’163 count modulo-16 binary se-
quence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the ’LS160) occur as a re-
sult of, and synchronous with, the LOW-to-HIGH transition
of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous
reset (’LS160), synchronous reset (’LS162), parallel load,
count-up and hold. Five control inputsÐMaster Reset (MR,
’LS160), Synchronous Reset (SR, ’LS162), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable Trickle
(CET)Ðdetermine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP.
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (P ) inputs to be loaded into the
n
flip-flops on the next rising edge of CP. With PE and MR
(’LS160) or SR (’LS162) HIGH, CEP and CET permit count-
ing when both are HIGH. Conversely, a LOW signal on ei-
ther CEP or CET inhibits counting.
The ’LS160A and ’LS162A use D-type edge-triggered flip-
flops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided that
the recommended setup and hold times, with respect to the
rising edge of CP, are observed.
3
Functional Description (Continued)
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in its maximum count state (9 for the
decade counters, 15 for the binary counters). To implement
synchronous multistage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Mode Select Table
Action on the Rising
*SR
PE
CET
CEP
Clock Edge (L )
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
LROEASDET(P(Cnxlear)Q )
These two schemes are shown in the 9310 data sheet. The
TC output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, counters or regis-
ters. In the decade counters of the ’LS160, ’LS162, the TC
output is fully decoded and can only be HIGH in state 9.
n
H
H
H
COUNT (Increment)
NO CHANGE (Hold)
NO CHANGE (Hold)
X
*For the ’LS162
e
e
e
H
HIGH Voltage Level
LOGIC EQUATIONS:
L
LOW Voltage Level
Immaterial
X
e
Count Enable
CEP CET PE
#
#
Q0 Q1 Q2 Q3 CET
e
TC
#
#
#
#
State Diagrams
’LS160, ’LS162
TL/F/10177–5
4
Logic Diagrams
’LS160
TL/F/10177–3
’LS162
TL/F/10177–4
5
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier Package (E)
Order Number 54LS160ALMQB or 54LS162ALMQB
NS Package Number E20A
Ceramic Dual-In-Line Package (J)
Order Number 54LS160ADMQB or 54LS162ADMQB
NS Package Number J16A
6
Physical Dimensions inches (millimeters) (Continued)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS160AM DM74LS162AM
NS Package Number M16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS160AN or DM74LS162AN
NS Package Number N16E
7
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 54LS160AFMQB or 54LS162AFMQB
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
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This datasheet has been download from:
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