DM74LS169AN [NSC]

Synchronous 4-Bit Up/Down Binary Counter; 同步4位加/减二进制计数器


型号：	DM74LS169AN
厂家：	National Semiconductor
描述：	Synchronous 4-Bit Up/Down Binary Counter 同步4位加/减二进制计数器计数器触发器逻辑集成电路光电二极管
文件：	总8页 (文件大小：168K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

June 1989

54LS169/DM54LS169A/DM74LS169A

Synchronous 4-Bit Up/Down Binary Counter

General Description

This synchronous presettable counter features an internal

carry look-ahead for cascading in high-speed counting ap-

plications. Synchronous operation is provided by having all

flip-flops clocked simultaneously, so that the outputs all

change at the same time when so instructed by the count-

enable inputs and internal gating. This mode of operation

helps eliminate the output counting spikes that are normally

associated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four master-slave flip-flops

on the rising edge of the clock waveform.

counting up, and approximately equal to the low portion of

the Q output when counting down. This low-level overflow

carry pulse can be used to enable successively cascaded

stages. Transitions at the enable P or T inputs are allowed

regardless of the level of the clock input. All inputs are diode

clamped to minimize transmission-line effects, thereby sim-

plifying system design.

This counter features

a fully independent clock circuit.

Changes at control inputs (enable P, enable T, load, up/

down), which modify the operating mode, have no effect

until clocking occurs. The function of the counter (whether

enabled, disabled, loading, or counting) will be dictated

solely by the conditions meeting the stable setup and hold

times.

This counter is fully programmable; that is, the outputs may

each be preset either high or low. The load input circuitry

allows loading with the carry-enable output of cascaded

counters. As loading is synchronous, setting up a low level

at the load input disables the counter and causes the out-

puts to agree with the data inputs after the next clock pulse.

Features

The carry look-ahead circuitry permits cascading counters

for n-bit synchronous applications without additional gating.

Both count-enable inputs (P and T) must be low to count.

The direction of the count is determined by the level of the

up/down input. When the input is high, the counter counts

up; when low, it counts down. Input T is fed forward to en-

able the carry outputs. The carry output thus enabled will

produce a low-level output pulse with a duration approxi-

Fully synchronous operation for counting and

programming.

Internal look-ahead for fast counting.

Carry output for n-bit cascading.

Fully independent clock circuit

Alternate Military/Aerospace device (54LS169) is

a National Semiconductor Sales

available. Contact

Office/Distributor for specifications.

mately equal to the high portion of the Q output when

Connection Diagram

Dual-In-Line Package

TL/F/6401–1

Order Number 54LS169DMQB, 54LS169FMQB, 54LS169LMQB,

DM54LS169AJ, DM54LS169AW, DM74LS169AM or DM74LS169AN

See NS Package Number E20A, J16A, M16A, N16E or W16A

1995 National Semiconductor Corporation

TL/F/6401

RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Note: The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Supply Voltage

Input Voltage

Operating Free Air Temperature Range

DM54LS and 54LS

DM74LS

55 C to 125 C

0 C to 70 C

65 C to 150 C

Storage Temperature Range

Recommended Operating Conditions

DM54LS169A

DM74LS169A

Symbol

Parameter

Units

Min

4.5

Nom

Max

Min

4.75

Nom

Max

Supply Voltage

5.5

5.25

High Level Input Voltage

Low Level Input Voltage

High Level Output Current

Low Level Output Current

Clock Frequency (Note 1)

Clock Frequency (Note 2)

Clock Pulse Width (Note 3)

0.7

0.8

0.4

MHz

CLK

Setup Time

(Note 3)

Data

Enable

T or P

Load

U/D

Hold Time (Note 3)

Free Air Operating Temperature

125

Note 1: C

Note 2: C

Note 3: T

15 pF, R

50 pF, R

2 kX, T

25 C and V

5V.

25 C and V

5V.

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Typ

(Note 4)

Symbol

Parameter

Conditions

Min

Max

Units

e b

1.5

Input Clamp Voltage

Min, I

18 mA

High Level Output

Voltage

Max

Min

DM54

2.5

2.7

3.4

Max, V

DM74

Low Level Output

Voltage

Min, I

Max

Min

DM54

0.25

0.35

0.25

0.4

Max, V

DM74

0.5

0.4

0.2

0.1

Min

4 mA, V

DM74

Input Current Max

Input Voltage

Max

Enable T

Others

Enable T

Others

Enable T

Others

DM54

2.7V

High Level Input

Current

Max

0.4V

Low Level Input

Current

0.8

0.4

(Note 5)

Short Circuit

Output Current

100

DM74

Supply Current

Max (Note 6)

25 C.

Note 4: All typicals are at V

5V and T

Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 6: I

is measured after a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the outputs open.

25 C (See Section 1 for Test Waveforms and Output Load)

Switching Characteristics at V

5V and T

2 kX

From (Input)

To (Output)

Symbol

Parameter

15 pF

50 pF

Max

Units

Min

Max

Min

Maximum Clock

Frequency

MAX

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

MHz

Propagation Delay Time

Low to High Level Output

Clock to

Ripple Carry

Propagation Delay Time

High to Low Level Output

Clock to

Ripple Carry

Propagation Delay Time

Low to High Level Output

Clock to

Any Q

Propagation Delay Time

High to Low Level Output

Clock to

Any Q

Propagation Delay Time

Low to High Level Output

Enable T to

Ripple Carry

Propagation Delay Time

High to Low Level Output

Enable T to

Ripple Carry

Propagation Delay Time

Low to High Level Output

Up/Down to

Ripple Carry (Note 1)

Propagation Delay Time

High to Low Level Output

Up/Down to

Ripple Carry (Note 1)

Note 1: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level

of the up/down input is changed, the ripple carry output will follow. If the count is minimum, the ripple carry output transition will be in phase. If the count is

maximum, the ripple carry output will be out of phase.

Logic Diagram

LS169A Binary Counter

TL/F/6401–2

Timing Diagram

LS169A Binary Counters

Typical Load, Count, and Inhibit Sequences

TL/F/6401–3

Physical Dimensions inches (millimeters)

Ceramic Leadless Chip Carrier Package (E)

Order Number 54LS169LMQB

NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 54LS169DMQB or DM54LS169AJ

NS Package Number J16A

Physical Dimensions inches (millimeters) (Continued)

16-Lead Small Outline Molded Package (M)

Order Number DM74LS169AM

NS Package Number M16A

16-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS169AN

NS Package Number N16E

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Number 54LS169FMQB or DM54LS169AW

NS Package Number W16A

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failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

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