DP83257VF_技术文档

PRELIMINARY

October 1994

DP83256/56-AP/57

TM

a

PLAYER

Device (FDDI Physical Layer Controller)

Y

Alternate PMD Interface (DP83256-AP/57) supports

UTP twisted pair FDDI PMDs with no external clock re-

covery or clock generation functions required

No External Filter Components

General Description

The DP83256/56-AP/57 Enhanced Physical Layer Control-

a

ler (PLAYER device) implements one complete Physical

Y

Layer (PHY) entity as defined by the Fiber Distributed Data

Interface (FDDI) ANSI X3T9.5 standard.

Connection Management (CMT) Support (LEM, TNE,

PC React, CF React, Auto Scrubbing)

Ð Ð

Full on-chip configuration switch

a

The PLAYER

device integrates state of the art digital

Y

clock recovery and improved clock generation functions to

enhance performance, eliminate external components and

remove critical layout requirements.

Low Power CMOS-BIPOLAR design using a single 5V

supply

Y

Full duplex operation with through parity

Separate management interface (Control Bus)

Selectable Parity on PHY-MAC Interface and Control

Bus Interface

FDDI Station Management (SMT) is aided by Link Error

Monitoring support, Noise Event Timer (TNE) support, Op-

tional Auto Scrubbing support, an integrated configuration

switch and built-in functionality designed to remove all strin-

Y

Two levels of on-chip loopback

gent response time requirements such as PC React and

Ð

CF React.

Ð

4B/5B encoder/decoder

Framing logic

Elasticity Buffer, Repeat Filter, and Smoother

Line state detector/generator

Features

Y

Single chip FDDI Physical Layer (PHY) solution

Y

Supports single attach stations, dual attach stations

and concentrators with no external logic

DP83256 for SAS/DAS single path stations

DP83257 for SAS/DAS single/dual path stations

DP83256-AP for SAS/DAS single path stations that re-

quire the alternate PMD interface

Integrated Digital Clock Recovery Module provides en-

hanced tracking and greater lock acquisition range

Y

Integrated Clock Generation Module provides all neces-

sary clock signals for an FDDI system from an external

12.5 MHz reference

TL/F/11708–1

FIGURE 1-1. FDDI Chip Set Overview

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

BMAC^TM, BSI^TM, CDD^TM, CDL^TM, CRD^TM, CYCLONE^TM, MACSI^TM, PLAYER^TM, PLAYER

TM

and TWISTER^TMare trademarks of National Semiconductor Corporation.

a

C

1995 National Semiconductor Corporation

TL/F/11708

RRD-B30M115/Printed in U. S. A.

Table of Contents

1.0 FDDI CHIP SET OVERVIEW

5.21 Current State Prescale Count Register (CSPCR)

5.22 Link Error Threshold Register (LETR)

5.23 Current Link Error Count Register (CLECR)

5.24 User Definable Register (UDR)

1.1 FDDI 2-Chip Set

1.2 FDDI TP-PMD Solutions

2.0 ARCHITECTURE DESCRIPTION

5.25 Device ID Register (DIR)

2.1 Block Overview

2.2 Interfaces

5.26 Current Injection Count Register (CIJCR)

5.27 Interrupt Condition Comparison Register (ICCR)

5.28 Current Transmit State Comparison Register

(CTSCR)

3.0 FUNCTIONAL DESCRIPTION

3.1 Clock Recovery Module

3.2 Receiver Block

5.29 Receive Condition Comparison Register A (RCCRA)

5.30 Receive Condition Comparision Register B (RCCRB)

5.31 Mode Register 2 (MODE2)

3.3 Transmitter Block

3.4 Configuration Switch

3.5 Clock Generation Module

3.6 Station Management Support

3.7 PHY-MAC Interface

3.8 PMD Interface

5.32 CMT Condition Comparison Register (CMTCCR)

5.33 CMT Condition Register (CMTCR)

5.34 CMT Condition Mask Register (CMTCMR)

5.35 Reserved Registers 22H-23H (RR22H-RR23H)

5.36 Scrub Timer Threshold Register (STTR)

5.37 Scrub Timer Value Register (STVR)

4.0 MODES OF OPERATION

5.38 Trigger Definition Register (TDR)

4.1 Run Mode

5.39 Trigger Transition Configuration Register (TTCR)

5.40 Reserved Registers 28H-3AH (RR28H-RR3AH)

5.41 Clock Generation Module Register (CGMREG)

5.42 Alternate PMD Register (APMDREG)

4.2 Stop Mode

4.3 Loopback Mode

4.4 Device Reset

4.5 Cascade Mode

5.43 Gain Register (GAINREG)

5.0 REGISTERS

5.44 Reserved Registers 3EH-3FH (RR3EH-RR3FH)

5.1 Mode Register (MR)

6.0 SIGNAL DESCRIPTIONS

5.2 Configuration Register (CR)

6.1 DP83256VF Signal Descriptions

6.2 DP83256VF-AP Signal Descriptions

6.3 DP83257VF Signal Descriptions

5.3 Interrupt Condition Register (ICR)

5.4 Interrupt Condition Mask Register (ICMR)

5.5 Current Transmit State Register (CTSR)

5.6 Injection Threshold Register (IJTR)

5.7 Injection Symbol Register A (ISRA)

5.8 Injection Symbol Register B (ISRB)

5.9 Current Receive State Register (CRSR)

5.10 Receive Condition Register A (RCRA)

5.11 Receive Condition Register B (RCRB)

5.12 Receive Condition Mask Register A (RCMRA)

5.13 Receive Condition Mask Register B (RCMRB)

5.14 Noise Threshold Register (NTR)

7.0 ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

7.2 Recommended Operating Conditions

7.3 DC Electrical Characteristics

7.4 AC Electrical Characteristics

8.0 CONNECTION DIAGRAMS

8.1 DP83256VF Connection Diagram/Pin Descriptions

8.2 DP83256VF-AP Connection Diagram/Pin Descrip-

tions

5.15 Noise Prescale Threshold Register (NPTR)

5.16 Current Noise Count Register (CNCR)

5.17 Current Noise Prescale Count Register (CNPCR)

5.18 State Threshold Register (STR)

8.3 DP83257VF Connection Diagram/Pin Descriptions

9.0 PACKAGE INFORMATION

9.1 Land Patterns

5.19 State Prescale Threshold Register (SPTR)

5.20 Current State Count Register (CSCR)

9.2 Mechanical Drawings

2

1.0 FDDI Chip Set Overview

National Semiconductor’s next generation FDDI 2-chip set

DP83266 MACSI^TMDevice Media

Access Controller and System

Interface

The DP83266 Media Access Controller and System Inter-

face (MACSI) implements the ANSI X3T9.5 Standard Media

Access Control (MAC) protocol for operation in an FDDI

token ring and provides a comprehensive System Interface.

consists of two components as shown in Figure 1-1. The

a

PLAYER device integrates the features of the DP83231

CRD^TMClock Recovery Device, DP83241 CDD^TMClock

Distribution Device, and DP83251/55 PLAYER^TMPhysical

a

Layer Controller. In addition, the PLAYER device contains

enhanced SMT support.

The MACSI device transmits, receives, repeats, and strips

tokens and frames. It produces and consumes optimized

data structures for efficient data transfer. Full duplex archi-

tecture with through parity allows diagnostic transmission

and self testing for error isolation in point-to-point connec-

tions.

National Semiconductor’s FDDI TP-PMD Solutions consist

of two componentsÐthe DP83222 CYCLONE^TMTwisted

Pair FDDI Stream Cipher Device and the DP83223A

TWISTER^TMTwisted Pair FDDI Transceiver Device.

For more information on the other devices of the chip set,

consult the appropriate datasheets and application notes.

The MACSI device includes the functionality of both the

DP83261 BMAC device and the DP83265 BSI-2 device with

additional enhancements for higher performance and reli-

ability.

1.1 FDDI 2-CHIP SET

a

Device Physical Layer Controller

DP83256/56-AP/57 PLAYER

Features

Y

a

The PLAYER

device implements the Physical Layer

Over 9 Kbytes of on-chip FIFO

(PHY) protocol as defined by the ANSI FDDI PHY X3T9.5

standard.

Y

5 DMA Channels (2 Output and 3 Input)

Y

12.5 MHz to 33 MHz operation

Y

Features

Y

Full duplex operation with through parity

Y

Single chip FDDI Physical Layer (PHY) solution

Real-time VOID frame stripping indicator for bridges

Y

Integrated Digital Clock Recovery Module provides en-

hanced tracking and greater lock acquisition range

On-chip Address bit swapping capability

Y

32-bit wide Address/Data path with byte parity

Y

Integrated Clock Generation Module provides all neces-

sary clock signals for an FDDI system from an external

12.5 MHz reference

Programmable transfer burst sizes of

words

4 or 8 32-bit

Y

Receive frame filtering services

Y

Alternate PMD Interface (DP83256-AP/57) supports

UTP twisted pair FDDI PMDs with no external clock re-

covery or clock generation functions required

Frame-per-Page mode controllable on each DMA

channel

Y

Demultiplexed Addresses supported on ABus

New multicast address matching

Y

No External Filter Components

Y

Connection Management (CMT) Support (LEM, TNE,

PC React, CF React, Auto Scrubbing)

ANSI X3T9.5 MAC standard defined ring service op-

tions

Ð Ð

Full on-chip configuration switch

Y

Supports all FDDI Ring Scheduling Classes (Synchro-

nous, Asynchronous, etc.)

Low Power CMOS-BIPOLAR design using a single 5V

supply

Supports Individual, Group, Short, Long, and External

Addressing.

Y

Full duplex operation with through parity

Separate management interface (Control Bus)

Selectable Parity on PHY-MAC Interface and Control

Bus Interface

Y

Generates Beacon, Claim, and Void frames

Extensive ring and station statistics gathering

Extension for MAC level bridging

Y

Two levels of on-chip loopback

Enhanced SBus compatibility

4B/5B encoder/decoder

Interfaces to DRAMs or directly to system bus

Supports frame Header/Info splitting

Programmable Big or Little Endian alignment

Framing logic

Elasticity Buffer, Repeat Filter, and Smoother

Line state detector/generator

Supports single attach stations, dual attach stations

and concentrators with no external logic

DP83256/56-AP for SAS/DAS single path stations

P83257 for SAS/DAS single/dual path stations

Y

In addition, the DP83257 contains the additional PHY Da-

Ð

ta.request and PHY Data.indicate ports required for con-

Ð

centrators and dual attach, dual path stations.

3

DP83222 CYCLONE Twisted Pair

FDDI Stream Cipher Device

DP83223A TWISTER High Speed

Networking Transceiver Device

General Description

The DP83222 CYCLONE Stream Cipher Scrambler/Des-

crambler Device is an integrated circuit designed to inter-

face directly with the serial bit streams of a Twisted Pair

FDDI PMD. The DP83222 is designed to be fully compatible

with the National Semiconductor FDDI Chip Sets, including

twisted pair FDDI Transceivers, such as the DP83223A

Twisted Pair Transceiver (TWISTER). The DP83222 re-

quires a 125 MHz Transmit Clock and corresponding Re-

ceive Clock for synchronous data scrambling and descram-

bling. The DP83222 is compliant with the ANSI X3T9.5

TP-PMD standard and is required for the reduction of EMI

emission over unshielded media. The DP83222 is specified

to work in conjunction with existing twisted pair transceiver

signalling schemes and enables high bandwidth transmis-

sion over Twisted Pair copper media.

The DP83223A Twisted Pair Transceiver is an integrated

circuit capable of driving and receiving either binary or

(MLT-3) encoded datastreams. The DP83223A Transceiver

is designed to interface directly with standards compliant

FDDI, 100BASE-TX or STS-3c ATM chip sets, allowing low

cost data links over copper based media. The DP83223A

allows links of up to 100 meters over both Shielded Twisted

Pair (STP) and datagrade Unshielded Twisted Pair (UTP) or

equivalent. The electrical performance of the DP83223A

meets or exceeds all performance parameters specified

in the ANSI X3T9.5 TP-PMD standard, the IEEE 802.3

100BASE-TX Fast Ethernet Specification and the ATM Fo-

rum 155 Mbps Twisted Pair PMD Interface Specification.

The DP83223A also provides important features such as

baseline restoration, TRI-STATE capable transmit outputs,

É

and controlled transmit output edge rates (to reduce EMI

radiation) for both binary and MLT-3 modes of operation.

Features

Y

Enables 100 Mbps FDDI signalling over Category

Unshielded Twisted Pair (UTP) cable and Type

Shielded Twisted Pair (STP)

5

1

Features

Y

Compliant with ANSI X3T9.5 TP-PMD standard

Y

Reduces EMI emissions over Twisted Pair media

Compatible with ANSI X3T9.5 TP-PMD standard

Compliant with IEEE 802.3 100BASE-TX Ethernet draft

standard

Y

a

Compliant with ATM Forum 155 Mbps Twisted Pair

Specification

Requires a single 5V supply

Transparent mode of operation

Flexible NRZ and NRZI format options

Advanced BiCMOS process

Y

Integrated baseline restoration circuit

Y

Integrated transmitter and receiver with adaptive equali-

zation circuit

Signal Detect and Clock Detect inputs provided for en-

hanced functionality

Y

Programmable binary or MLT-3 operation

Y

Isolated TX and RX power supplies for minimum noise

coupling

Y

Suitable for Fiber Optic PMD replacement applications

Y

Controlled transmit output edge rates for reduced EMI

Y

TRI-STATE capable current transmit outputs

Y

Loopback feature for board diagnostics

Y

Programmable transmit voltage amplitude

4

2.0 Architecture Description

2.1 BLOCK OVERVIEW

The Receiver Block performs the following operations:

Optionally converts the incoming data stream from NRZI

to NRZ.

#

a

The PLAYER

device is comprised of six blocks: Clock

Recovery, Receiver, Configuration Switch, Transmitter, Sta-

tion Management (SMT) Support, and Clock Generation

Module as shown in Figure 2-1.

Decodes the data from 5B to 4B coding.

#

Converts the serial bit stream into 10-bit bytes composed

of 8 bits data, 1 bit parity, and 1 bit control information.

Clock Recovery

Compensates for the differences between the upstream

station clock and the local clocks.

#

The Clock Recovery Module accepts a 125 Mbps NRZI data

stream from the external PMD receiver. It then provides the

extracted and synchronized data and clock to the Receiver

block.

Decodes Line States.

#

Detects link errors.

The Clock Recovery Module performs the following opera-

tions:

Presents data symbol pairs (bytes) to the Configuration

Switch Block.

#

Locks to and tracks the incoming NRZI data stream

#

Configuration Switch

Extracts data stream and synchronized 125 MHz clock

#

An FDDI station may be in one of three configurations: Iso-

late, Wrap or Thru. The Configuration Switch supports these

configurations by switching the transmitted and received

a

data paths between PLAYER devices and one or more

MACSI devices.

Receiver

During normal operation, the Receiver Block accepts serial

data as inputs at the rate of 125 Mbps from the Clock Re-

covery Module. During the Internal Loopback mode of oper-

ation, the Receiver Block accepts data directly from the

Transmitter Block.

a

The configuration switch is integrated into the PLAYER

device, therefore no external logic is required for this func-

tion.

Setting the Configuration switch can be done explicitly via

the Control Bus Interface or it can be set automatically with

the CF React SMT Support feature.

Ð

TL/F/11708–2

a

FIGURE 2-1. PLAYER Device Block Diagram

5

2.0 Architecture Description (Continued)

Transmitter

PMD Interface

a

device to a

The Transmitter Block accepts 10-bit bytes composed of 8

bits data, 1 bit parity, and 1 bit control information from the

Configuration Switch.

The PMD Interface connects the PLAYER

standard FDDI Physical Media Connection such as a fiber

optic transceiver or a copper twisted pair transceiver. It is a

125 MHz full duplex serial connection.

The Transmitter Block performs the following operations:

a

The DP83256-AP and DP83257 PLAYER devices contain

Encodes the data from 4B to 5B coding.

#

two PMD interfaces. The Primary PMD Interface should be

used for all PMD implementations that do not require an

external scrambler/descrambler function, clock recovery

function, or clock generation function, such as a Fiber Optic

or Shielded Twisted Pair (SDDI) PMD. The second, Alter-

nate PMD Interface can be used to support Unshielded

Twisted Pair (UTP) PMDs that require external scrambling,

and allows implementation with no external clock recovery

or clock generation functions required.

Filters out code violations from the data stream.

#

Generates Idle, Master, Halt, Quiet, or other user defined

symbol pairs upon request.

Converts the data stream from NRZ to NRZI format for

transmission.

#

Provides smoothing function when necessary.

#

During normal operation, the Transmitter Block presents se-

rial data to the PMD transmitter. While in Internal Loopback

mode, the Transmitter Block presents serial data to the Re-

ceiver Block. While in the External Loopback mode, the

Transmitter Block presents serial data to the Clock Recov-

ery Module.

PHY Port Interface

a

The PHY Port Interface connects the PLAYER device to

one or more MAC devices and/or PLAYER devices. Each

a

PHY Port Interface consists of two byte-wide interfaces, one

a

for PHY Request data input to the PLAYER device and

one for the PHY Indicate data output of the PLAYER de-

Clock Generation Module

a

The Clock Generation Module is an integrated phase locked

loop that generates all of the required clock signals for the

vice. Each byte-wide interface consists of a parity bit (odd

parity), a control bit, and two 4-bit symbols.

a

12.5 MHz reference.

PLAYER

device and an FDDI system from

a

single

a

The DP83257 PLAYER device has two PHY Port Interfac-

es while the DP83256 has one PHY Port Interface.

The Clock Generation Module features:

Control Bus Interface

High precision clock timing generated from

12.5 MHz reference.

a

single

#

a

The Control Bus Interface connects the PLAYER device

to a wide variety of microprocessors and microcontrollers.

The Control Bus is an asynchronous interface which pro-

vides access to 64 8-bit registers which monitor and control

Multiple precision phased (8 ns/16 ns) 12.5 MHz Local

Byte Clocks to eliminate timing skew in large multi-board

concentrator configurations.

#

a

the behavior of the PLAYER device.

LBC timing which is insensitive to loading variations over

a wide range (20 pF to 70 pF) of LBC loads.

The Control Bus Interface allows a user to:

Configure SMT features.

#

A selectable dual frequency system clock.

#

Program the Configuration Switch.

Low clock edge jitter, due to high VCO stability.

Enable/disable functions within the Transmitter and Re-

Station Management (SMT) Support

ceiver Blocks (i.e., NRZ/NRZI Encoder, Smoother, PHY

Request Data Parity, Line State Generation, Symbol pair

Injection, NRZ/NRZI Decoder, Cascade Mode, etc.).

The Station Management Support Block provides a number

of useful features to simplify the implementation of the Con-

nection Management (CMT) portion of SMT.

The Control Bus Interface also can be used to perform the

following functions:

These features eliminate the time critical CMT response

time constraints imposed by PC React and CF React

times.

Monitor Line States received.

#

Ð

Monitor link errors detected by the Receiver Block.

Integrated counters and timers eliminate the need for addi-

tional external devices.

Monitor other error conditions.

Clock Interface

The following are the CMT features supported:

The Clock Interface is used to configure the Clock Genera-

tion Module and to provide the required clock signals for an

FDDI system.

PC React

Ð

CF React

Ð

Auto Scrubbing (TCF Timer)

#

The following clock signals are generated:

Timer, Idle Detection (TID Timer)

#

5 phase offset 12.5 MHz Local Byte Clocks

#

25 MHz Local Symbol Clock

Noise Event Counter (TNE Timer)

15.625 or 31.25 MHz System Clock

Link Error Monitor (LEM Counter)

Miscellaneous Interface

2.2 INTERFACES

The Miscellaneous Interface consists of:

a

The PLAYER device connects to other devices via five

A reset signal.

#

functional interfaces: PMD Interface, PHY Port Interface,

Control Bus Interface, Clock Interface, and the Miscellane-

ous Interface.

User definable sense signals.

User definable enable signals.

a

Synchronization for cascading PLAYER

high-performance non-FDDI mode).

Device Power and Ground pins.

devices (a

#

6

3.0 Functional Description

a

The PLAYER

device is comprised of six blocks: Clock

DIGITAL PHASE DETECTOR

Recovery, Receiver, Transmitter, Configuration Switch,

Clock Generation, and Station Management Support.

The Digital Phase Detector has two main functions: phase

error detection and data recovery.

3.1 CLOCK RECOVERY MODULE

Phase error detection is accomplished by a digital circuit

that compares the input data (PMID) to an internal phase-

locked 125 MHz reference clock and generates a pair of

error signals. The first signal is a pulse whose width is equal

to the phase error between the input data and a reference

clock and the second signal is a 4 ns reference pulse.

These signals are fed into the Digital Phase Error Processor

block.

The Clock Recovery Module accepts a 125 Mbps NRZI data

stream from the external PMD receiver. It then provides the

extracted and synchronized data and clock to the Receiver

block.

The Clock Recovery Module performs the following opera-

tions:

Locks onto and tracks the incoming NRZI data stream

#

The data recovery function converts the incoming encoded

data stream (PMID) into synchronized data and clock sig-

nals. When the circuit is in lock the rising edge of the recov-

ered clock is exactly centered in the recovered data bit cell.

Extracts the data stream and the synchronized 125 MHz

clock

#

The Clock Recovery Module is implemented using an ad-

vanced digital architecture that replaces sensitive analog

The digital phase detector uses a common path for phase

error detection and data recovery so as to minimize clock

Static Alignment Error (SAE). Phase error averaging is also

included so that phase errors generated by positive and

negative PMID edges equally affect the clock recovery cir-

cuit. This greatly improves the immunity to Duty Cycle Dis-

tortion (DCD) in the data recovery circuit.

a

blocks with digital circuitry. This allows the PLAYER de-

vice to be manufactured to tighter tolerances since it is less

sensitive to processing variations that can adversely affect

analog circuits.

The Clock Recovery Module is comprised of 5 main func-

tional blocks:

Digital Phase Detector

DIGITAL PHASE ERROR PROCESSOR

Digital Phase Error Processor

The Digital Phase Error Processor is responsible for sam-

pling the Phase Detector’s phase error outputs and produc-

ing two digital outputs that indicate to the digital loop filter

how to adjust for a difference between the data phase and

reference phases.

Digital Loop Filter

Digital Phase to Frequency Converter

Frequency Controlled Oscillator

See Figure 3-1, Clock Recovery Module Block Diagram.

The Phase Error Processor is designed to eliminate the ef-

fects of different clock edge densities between data sym-

bols and the various line state symbols on the PLL’s loop

gain.

TL/F/11708–3

FIGURE 3-1. Clock Recovery Module Block Diagram

7

3.0 Functional Description (Continued)

Since the loop gain is held constant regardless of the in-

coming signal edge density, PLL characteristics such as jit-

ter, acquisition rate, locking range etc., are deterministic and

show minimal spread under various operating environments.

Each valid Up or Down signal causes a partial 7-bit counter

(using only 96 counts) to increment or decrement at the

O

–F converter’s clock rate of 15.625 MHz (250 MHz/16).

When the Data Valid signal is not asserted, the counter

holds count.

The phase error processor also automatically puts the loop

in open-loop-mode when the incoming data stream contains

abnormal low edge rates. When the PLL is in open-loop-

mode, no update is made to the PLL’s filter variables in the

filter block. The PLL can then use the pretrained frequency

and phase contents to perform data recovery. Since the

loop is implemented digitally, these values (the frequency

and phase variables) are retained. The resolution of the fre-

quency variable is about 1.3 ppm of the incoming frequency.

The resolution of the phase variable is about 40 ps.

The counter value is used to produce 3 triangle waves that

are offset in phase by 120 degrees. This is done with a

special Pulse Density Modulator waveform synthesizer

which takes the place of a traditional Digital-Analog convert-

er. The frequency of the triangle waves tells the Frequency

Controlled Oscillator how much to adjust oscillation. The

phase relationships (leading or lagging) between the 3 sig-

nals indicates the direction of change.

The minimum frequency of the triangle waves is 0 and cor-

responds to the case when the PLL is in perfect lock with

the incoming signal.

DIGITAL LOOP FILTER

The digital loop filter emulates a 1-pole, 1-zero filter and

uses an automatic acquisition speed control circuit to dy-

namically adjust loop parameters.

O

The maximum frequency that the

–F converter can pro-

duce determines the locking range of the PLL. In this case

the maximum frequency of each triangle wave is 162.76

The digital loop filter takes the phase error indicator signals

Data Valid and Up/Down from the Phase Error processor

and accumulates errors over a few cycles before passing on

the Data Valid and Up/Down signals to the Phase Error to

Frequency converter.

O

kHz, which is produced when the

continuous count in one direction that is valid every

–F converter gets a

O

–F

converter clock cycle of 15.625 MHz (250 MHz/16). The

triangle waves have an amplitude resolution of 48 digital

steps, so a full rising and falling period takes 96 counts

The filter has 4 sets of bandwidth and damping parameters

which are switched dynamically by an acquisition control

circuit. The input Signal Detect (SD) starts the sequence

and, thereafter, no user programming is required to finish

the sequence.

which produces a maximum frequency of 162.76 kHz

(1/(1/15.625 kHz * 96)).

The 96 digital counts of the triangle waves also lead to a

very fine PLL phase resolution of 42 ps (4 ns/96 counts).

This high phase resolution is achieved using very low fre-

quency signals, in contrast to a standard PLL which must

operate at significantly higher frequencies than the data be-

ing tracked to achieve such high phase resolution.

At the completion of the locking sequence, the loop has the

narrowest bandwidth such that the loop produces minimal

recovered clock jitter. The PLL can track an incoming fre-

g

quency offset of approximately 200 ppm. After the acqui-

sition sequence, the equivalent natural frequency of the

FREQUENCY CONTROLLED OSCILLATOR (FCO)

g

loop is reduced to about 7 kHz ( 56 ppm) of frequency

offset.

The frequency controlled oscillator produces a 250 MHz

clock that, when divided by 2, is phase locked to the incom-

ing data’s clock.

The automatic tracking mechanism allows the loop to quick-

ly lock onto the initial data stream for data recovery (typical-

ly less than 10 ms) and yet produce very little recovered

clock jitter.

The FCO uses three 250 MHz reference clock signals from

the Clock Generation Module and three 0 Hz to 162.76 kHz

error clock signals from the Phase Error to Frequency Con-

verter as inputs. Each signal in a triplet is 120 degrees

phase shifted from the next.

PHASE ERROR TO FREQUENCY CONVERTER (O–F)

The Phase Error to Frequency Converter takes the Data

Valid and Up/Down signals modified by the Digital Loop

Filter and converts them to triangle waves. The frequency of

the triangle waves is then used to control the Frequency

Controlled Oscillator’s (FCO) 250 MHz oscillations.

Each corresponding pair (one 250 MHz and one error sig-

nal) of signals is mixed together using an amplitude switch-

ing modulator, with the error signal modulating the refer-

ence. All of the outputs are then summed together to pro-

a

where f is the error frequency.

duce the final 250 MHz

f

m

phase locked clock signal,

m

8

3.0 Functional Description (Continued)

3.2 RECEIVER BLOCK

NRZI TO NRZ DECODER

During normal operation, the Receiver Block accepts serial

data input at the rate of 125 Mbps from the Clock Recovery

Module. During the Internal Loopback mode of operation,

the Receiver Block accepts input data from the Transmitter

Block.

The NRZI to NRZ Decoder converts Non-Return-To-Zero-

Invert-On-Ones data to Non-Return-To-Zero format.

NRZ format data is the natural data format that the receiver

block utilizes internally, so this function is required when the

standard NRZI format data is fed into the device. The re-

ceiver block can bypass this conversion function in the case

where an alternate data source outputs NRZ format data.

The Receiver Block performs the following operations:

Optionally converts the incoming data stream from NRZI

to NRZ.

#

This function can be enabled and disabled through bit 7

(RNRZ) of the Mode Register (MR). When the bit is cleared,

it converts the incoming bit stream from NRZI to NRZ. This

is the normal configuration required. When the bit is set, the

incoming NRZ bit stream is passed unchanged.

Decodes the data from 5B to 4B coding.

#

Converts the serial bit stream into the National byte-wide

code.

#

Compensates for the differences between the upstream

station clock and the local clock.

#

SHIFT REGISTER

The Shift Register converts the serial bit stream into sym-

bol-wide data for the 5B/4B Decoder.

Decodes Line States.

#

Detects link errors.

The Shift Register also provides byte-wide data for the

Framing Logic.

Presents data symbol pairs to the Configuration Switch

Block.

FRAMING LOGIC

The Receiver Block consists of the following functional

blocks:

The Framing Logic performs the Framing function by detect-

ing the beginning of a frame or the Halt-Halt or Halt-Quiet

symbol pair.

NRZI to NRZ Decoder

Shift Register

The J-K symbol pair (11000 10001) indicates the beginning

of a frame during normal operation. The Halt-Halt (00100

00100) and Halt-Quiet (00100 00000) symbol pairs are de-

tected for Connection Management (CMT).

Framing Logic

Symbol Decoder

Line State Detector

Elasticity Buffer

Link Error Detector

See Figure 3-2.

TL/F/11708–4

FIGURE 3-2. Receiver Block Diagram

9

3.0 Functional Description (Continued)

Framing may be temporarily suspended (i.e. framing hold),

in order to maintain data integrity.

TABLE 3-1. 5B/4B Symbol Decoding

Symbol

Incoming 5B

Decoded 4B

Detecting JK

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

The JK symbol pair can be used to detect the beginning of a

frame during Active Line State (ALS) and Idle Line State

(ILS) conditions.

While the Line State Detector indicates Idle Line State the

receiver ‘‘reframes’’ upon detecting a JK symbol pair and

enters the Active Line State.

During Active Line State, acceptance of a JK symbol (re-

framing) is allowed for any on-boundary JK which is detect-

ed at least 1.5 byte times after the previous JK.

During Active Line State, once reframed on a JK, a subse-

quent off-boundary JK is ignored, even if it is detected be-

yond 1.5 byte times after the previous JK.

During Active Line State, an Idle or Ending Delimiter (T)

symbol will allow reframing on any subsequent JK, if a JK is

detected at least 1.5 byte times after the previous JK.

Detecting HALT-HALT AND HALT-QUIET

I (Idle)

11111

1010

0001

1101

During Idle Line State, the detection of a Halt-Halt, or Halt-

Quiet symbol pair will still allow the reframing of any subse-

quent on-boundary JK.

H (Halt)

00100

JK (Starting

11000 and

10001

Delimiter)

Once a JK is detected during Active Line State, off-bounda-

ry Halt-Halt, or Halt-Quiet symbol pairs are ignored until the

Elasticity Buffer (EB) has an opportunity to recenter. They

are treated as violations.

T (Ending

01101

0101

Delimiter)

R (Reset)

00111

11001

00000

00001

00010

00011

00101

00110

01000

01100

10000

0110

0111

0010

After recentering on a Halt-Halt, or Halt-Quiet symbol pair,

all off boundary Halt-Halt or Halt-Quiet symbol pairs are ig-

nored until the EB has a chance to recenter during a line

state other than Active Line State (which may be as long as

2.8 byte times).

S (Set)

Q (Quiet)

V (Violation)

V

SYMBOL DECODER

The Symbol Decoder is a two level system. The first level is

a 5-bit to 4-bit converter, and the second level is a 4-bit

symbol pair to byte-wide code converter.

The first level latches the received 5-bit symbols and de-

codes them into 4-bit symbols. Symbols are decoded into

two types: data and control. The 4-bit symbols are sent to

the Line State Detector and the second level of the Symbol

Decoder. See Table 3-1 for the 5B/4B Symbol Decoding

list.

Note: V denotes PHY Invalid or an Elasticity Buffer stuff byte

Ê

denotes Idle symbol in ILS or an Elasticity Buffer stuff byte

I

Ê

LINE STATES DESCRIPTION

Active Line State

The second level translates two symbols from the 5B/4B

converter and the line state information from the Line State

Detector into the National byte-wide code.

The Line State Detector recognizes the incoming data to be

in the Active Line State upon the reception of the Starting

Delimiter (JK symbol pair).

The Line State Detector continues to indicate Active Line

State while receiving data symbols, Ending Delimiter (T

symbols), and Frame Status symbols (R and S) after the JK

symbol pair.

LINE STATE DETECTOR

The ANSI X3T9.5 FDDI Physical Layer (PHY) standard

specifies eight Line States that the Physical Layer can

transmit. These Line States are used in the Connection

Management process. They are also used to indicate data

within a frame during normal operation.

Idle Line State

The Line State Detector recognizes the incoming data to be

in the Idle Line State upon the reception of 2 Idle symbol

pairs nominally (plus up to 9 bits of 1 in start up cases).

The Line States are reported through the Current Receive

A

State Register (CRSR), Receive Condition Register

(RCRA), and Receive Condition Register B (RCRB).

Idle Line State indicates the preamble of a frame or the lack

of frame transmission during normal operation. Idle Line

State is also used in the handshake sequence of the PHY

Connection Management process.

10

3.0 Functional Description (Continued)

Super Idle Line State

The Elasticity Buffer will support a maximum clock skew of

50 ppm with a maximum packet length of 4500 bytes.

The Line State Detector recognizes the incoming data to be

in the Super Idle Line State upon the reception of 8 consec-

utive Idle symbol pairs nominally (plus 1 symbol pair).

To make up for the accumulation of frequency disparity be-

tween the two clocks, the Elasticity Buffer will insert or de-

lete Idle symbol pairs in the preamble. Data is written into

the byte-wide registers of the Elasticity Buffer with the Re-

ceive Clock, while data is read from the registers with the

Local Byte Clock.

The Super Idle Line State is used to insure synchronization

of PCM signalling.

No Signal Detect

The Line State Detector recognizes the incoming data to be

in the No Signal Detect state upon the deassertion of the

Signal Detect signal or lack of internal clock detect from the

Clock Recovery Module, and reception of 8 Quiet symbol

pairs nominally. No Signal Detect indicates that the incom-

ing link is inactive. This is the same as receiving Quiet Line

State (QLS).

The Elasticity Buffer will recenter (i.e. set the read and write

pointers to a predetermined distance from each other) upon

the detection of a JK or every four byte times during PHY

Invalid (i.e. MLS, HLS, QLS, NLS, NSD) and Idle Line State.

The Elasticity Buffer is designed such that a given register

cannot be written and read simultaneously under normal op-

erating conditions. To avoid metastability problems, the EB

overflow event is flagged and the data is tagged before the

over/under run actually occurs.

Master Line State

The Line State Detector recognizes the incoming data to be

in the Master Line State upon the reception of eight consec-

utive Halt-Quiet symbol pairs nominally (plus up to 2 symbol

pairs in start up cases).

LINK ERROR DETECTOR

The Link Error Detector provides continuous monitoring of

an active link (i.e. during Active and Idle Line States) to

insure that it does not exceed the maximum Bit Error Rate

requirement as set by the ANSI standard for a station to

remain on the ring.

The Master Line State is used in the handshaking sequence

of the PHY Connection Management process.

Halt Line State

The Line State Detector recognizes the incoming data to be

in the Halt Line State upon the reception of eight consecu-

tive Halt symbol pairs nominally (plus up to 2 symbol pairs in

start up cases).

Upon detecting a link error, the internal 8-bit Link Error Mon-

itor Counter is decremented. The start value for the Link

Error Monitor Counter is programmed through the Link Error

Threshold Register (LETR). When the Link Error Monitor

Counter reaches zero, bit 4 (LEMT) of the Interrupt Condi-

tion Register (ICR) is set to 1. The current value of the Link

Error Monitor Counter can be read through the Current Link

Error Count Register (CLECR). For higher error rates the

current value is an approximate count because the counter

rolls over.

The Halt Line State is used in the handshaking sequence of

the PHY Connection Management process.

Quiet Line State

The Line State Detector recognizes the incoming data to be

in the Quiet Line State upon the reception of eight consecu-

tive Quiet symbol pairs nominally (plus up to 9 bits of 0 in

start up cases).

There are two ways to monitor Link Error Rate: polling and

interrupt.

The Quiet Line State is used in the handshaking sequence

of the PHY Connection Management process.

Polling

The Link Error Monitor Counter can be set to a large value,

like FF. This will allow for the greatest time between polling

the register. This start value is programmed through the Link

Error Threshold Register (LETR).

Noise Line State

The Line State Detector recognizes the incoming data to be

in the Noise Line State upon the reception of 16 noise sym-

bol pairs without entering any known line state.

Upon detecting a link error, the Line Error Monitor Counter

is decremented.

The Noise Line State indicates that data is not being re-

ceived correctly.

The Host System reads the current value of the Link Error

Monitor Counter via the Current Link Error Count Register

(CLECR). The Counter is then reset to FF.

Line State Unknown

The Line State Detector recognizes the incoming data to be

in the Line State Unknown state upon the reception of 1

inconsistent symbol pair (i.e. data that is not expected). This

may signify the beginning of a new line state.

Interrupt

The Link Error Monitor Counter can be set to a small value,

like 5 to 10. This start value is programmed through the Link

Error Threshold Register (LETR).

Line State Unknown indicates that data is not being re-

ceived correctly. If the condition persists the Noise Line

State (NLS) may be entered.

Upon detecting a link error, the Line Error Monitor Counter

is decremented. When the counter reaches zero, bit 4

(LEMT) of the Interrupt Condition Register (ICR) is set to 1,

and the interrupt signal goes low, interrupting the Host Sys-

tem.

ELASTICITY BUFFER

The Elasticity Buffer performs the function of a ‘‘variable

depth’’ FIFO to compensate for phase and frequency clock

skews between the Receive Clock (RXCg) and the Local

Byte Clock (LBC).

Miscellaneous Items

When bit 0 (RUN) of the Mode Register (MR) is set to zero,

Bit 5 (EBOU) of the Receive Condition Register B (RCRB) is

set to 1 to indicate an error condition when the Elasticity

Buffer cannot compensate for the clock skew.

a

or when the PLAYER device is reset through the Reset

pin ( RST), the internal signal detect line is internally

E

forced to zero and the Line State Detector is set to Line

State Unknown and No Signal Detect.

11

3.0 Functional Description (Continued)

While in Internal Loopback mode, the Transmitter Block

presents serial data to the Receiver Block. While in the Ex-

ternal Loopback mode, the Transmitter Block presents seri-

al data to the Clock Recovery Module.

3.3 TRANSMITTER BLOCK

The Transmitter Block accepts 10-bit bytes consisting of

8 bits data, 1 bit parity, and 1 bit control information, from

the Configuration Switch.

The Transmitter Block consists of the following functional

blocks:

The Transmitter Block performs the following operations:

Encodes the data from 4B to 5B coding.

#

Data Registers

Parity Checker

Filters out code violations from the data stream.

Is capable of generating Idle, Master, Halt, Quiet, or oth-

er user defined symbol pairs.

4B/5B Encoder

Repeat Filter

Smoother

Line State Generator

Injection Control Logic

Shift Register

#

Converts the data stream from NRZ to NRZI for trans-

mission.

#

Serializes data.

#

During normal operation, the Transmitter Block presents se-

rial data to a PMD transmitter.

NRZ to NRZI Encoder

See Figure 3-3, Transmitter Block Diagram.

TL/F/11708–5

FIGURE 3-3. Transmitter Block Diagram

12

3.0 Functional Description (Continued)

TABLE 3-2. 4B/5B Symbol Encoding

DATA REGISTERS

Symbol

4B Code

5B Code

Data from the Configuration Switch is stored in the Data

Registers. The 10-bit byte-wide data consists of a parity bit,

a control bit, and two 4-bit data symbols as shown below.

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

b9

Parity Bit Control Bit

FIGURE 3-4. Byte-Wide Data

b8

b7

b0

Data Bits

The parity is odd parity. The control bit determines whether

the Data bits represent Data or Control information. When

the control bit is 0 the Data field is interpreted as data and

when it is 1 the field is interpreted as control information

according to the National Semiconductor control codes.

PARITY CHECKER

The Parity Checker verifies that the parity bit in the Data

Register represents odd parity (i.e. odd number of 1s).

The parity is enabled and disabled through bit 6 (PRDPE) of

the Current Transmit State Register (CTSR).

N

0000

1101

11110 or

11111

If a parity error occurs, the Parity Checker will set bit 0 (DPE)

in the Interrupt Condition Register (ICR) and report the error

to the Repeat Filter.

JK (Starting

Delimiter)

T (Ending

Delimiter)

R (Reset)

11000 and

10001

4B/5B ENCODER

0100 or

0101

01101

The 4B/5B Encoder converts the two 4-bit data symbols

from the Configuration Switch into their respective 5-bit

codes.

0110

00111

Note: The upper group of symbols are sent with the Control/Data pin set to

Data, while the bottom grouping of symbols are sent with the Control/Data

pin set to Control.

See Table 3-2 for the Symbol Encoding list.

REPEAT FILTER

The Repeat Filter is used to prevent the propagation of

code violations to the downstream station.

Upon receiving violations in data frames, the Repeat Filter

replaces them with two Halt symbol pairs followed by Idle

symbols. Thus the code violations are isolated and recov-

ered at each link and will not be propagated throughout the

entire ring.

13

3.0 Functional Description (Continued)

TL/F/11708–6

FIGURE 3-5. Repeat Filter State Diagram

Note: Inputs to the Repeat Filter state machine are shown above the transition lines, while outputs from the state machine are shown below the transition lines.

Note: Abbreviations used in the Repeat Filter State Diagram are shown in Table 3-3.

14

3.0 Functional Description (Continued)

1. In Repeat State, violations cause transitions to Halt State

and two Halt symbol pairs are transmitted (unless JK or Ix

occurs) followed by transition to Idle State.

TABLE 3-3. Abbreviations used in the

Repeat Filter State Diagram

2. When Ix is encountered, the Repeat Filter goes to the Idle

State, during which Idle symbol pairs are transmitted until

a JK is encountered.

F

IDLE:

Force Idle true when not in Active

Ð

Transmit Mode.

Ð

W:

Represents the symbols R, or S, or T

3. The Repeat Filter goes to the Repeat State following a JK

from any state.

E

TPARITY: Parity error

Data symbols (for C

interface)

e

nn :

0 in the PHY-MAC

The END State, which is not part of the FDDI PHY standard,

allows an R or S prior to a T within a frame to be recognized

as a violation. It also allows NT to end a frame as opposed

to being treated as a violation.

N:

X:

Data portion of a control and data symbol

mixture

Any symbol (i.e. don’t care)

SMOOTHER

V :

Ê

Violation symbols or symbols inserted by

the Receiver Block

The Smoother is used to keep the preamble length of a

frame to a minimum of 6 Idle symbol pairs.

I :

Idle symbols or symbols inserted by the

Receiver Block

Ê

Idle symbols in the preamble of a frame may have been

added or deleted by each station to compensate for the

difference between the Receive Clock and its Local Clock.

The preamble needs to be maintained at a minimum length

to allow stations enough time to complete processing of one

frame and prepare to receive another. Without the Smooth-

er function, the minimum preamble length (6 Idle symbol

pairs) cannot be maintained as several stations may con-

secutively delete Idle symbols.

ALSZILSZ:

Active Line State or Idle Line State (i.e.

PHY Invalid)

E

ALSZILSZ: Not in Active Line State nor in Idle Line

State (i.e. PHY Valid)

H:

R:

S:

T:

Halt Symbol

Reset Symbol

Set Symbol

The Smoother attempts to keep the number of Idle symbol

pairs in the preamble at 7 by:

Frame ending delimiter

JK:

I:

Frame start delimiter

Idle symbol (Preamble)

Code violations

Deleting an Idle symbol pair in preambles which have

more than 7 Idle symbol pairs

#

and/or

V:

Inserting an idle symbol pair in preambles which have

less than 7 idle symbol pairs (i.e. Extend State).

#

The Repeat Filter complies with the FDDI standard by ob-

serving the following (see Figure 3-5 ):

The Smoother Counter starts counting upon detecting an

Idle symbol pair. It stops counting upon detecting a JK sym-

bol pair.

Figure 3-6 describes the Smoother state diagram.

15

3.0 Functional Description (Continued)

TABLE 3-4. Transmit Modes

LINE STATE GENERATOR

The Line State Generator allows the transmission of the

PHY Request data and can also generate and transmit Idle,

Master, Halt, or Quiet symbol pairs which can be used to

implement the Connection Management procedures as

specified in the FDDI Station Management (SMT) standard

document.

Transit Mode

Behavior

Active Transmit Mode

Transmit data that comes

from Configuration Switch

Off Transmit Mode

Transmit Quiet symbol

pairs and disable the PMD

Transmitter

The Line State Generator is programmed through Transmit

l

k

bits 0 to 2 (TM 2:0 ) of the Current Transmit State Regis-

ter (CTSR).

Idle Transmit Mode

Transmit Idle symbol pairs

Master Transmit Mode

Transmit Halt-Quiet

symbol pairs

Based on the setting of these bits, the Transmitter Block

operates in a Transmit Mode where the Line State Genera-

tor overwrites the Repeat Filter and Smoother outputs.

Quiet Transmit Mode

Transmit Quiet symbol

pairs

See INJECTION CONTROL LOGIC section for a listing of

the injection Transmit Modes.

Reserved Transmit Mode

Reserved for future use. If

Mode selected, Quiet

symbol pairs will be

transmitted.

Table 3-4 describes the Transmit Modes.

Halt Transmit Mode

Transmit Halt Symbol

pairs

Notes:

TL/F/11708–7

SE: Smoother Enable

C: Preamble Counter

F

IDLE: Force Idle (Stop or ATM)

Ð

X : Current Byte

n

X

n–1

: Previous Byte

W: RST

FIGURE 3-6. Smoother State Diagram

16

3.0 Functional Description (Continued)

In the One Shot mode, ISRA and ISRB are injected once on

the nth byte after a JK, where n is the programmed value

specified in the Injection Threshold Register.

INJECTION CONTROL LOGIC

The Injection Control Logic replaces the data stream with a

programmable symbol pair. This function is used to transmit

data other than the normal data frame or Line States. The

injection modes can be used for station diagnostic software.

In the Periodic mode, ISRA and ISRB are injected every nth

symbol.

In the Continuous mode, all data symbols are replaced with

the content of ISRA and ISRB. This is the same as periodic

e

mode with IJTR 0.

The Injection Symbols overwrite the Line State Generator

(Transmit Modes) and the Repeat Filter and Smoother out-

puts.

These programmable symbol pairs are stored in the Injec-

tion Symbol Register A (ISRA) and Injection Symbol Regis-

ter B (ISRB). The Injection Threshold Register (IJTR) deter-

mines where the Injection Symbol pair will replace the data

symbols.

SHIFT REGISTER

The Shift Register converts encoded parallel data to serial

data. The parallel data is clocked into the Shift Register by

the Local Byte Clock (LBC1), and clocked out by the Trans-

g

mit Bit Clock (TXC ) (externally available on the DP83257.)

The Injection Control Logic is programmed through the bits

NRZ TO NRZI ENCODER

k

l

0 and 1 (IC 1:0 ) of the Current Transmit State Register

(CTSR) to one of the following Injection Modes (see Figure

3-7 ):

The NRZ to NRZI Encoder converts the serial Non-Return-

To-Zero data to Non-Return-To-Zero-Invert-On-One format.

This function can be enabled and disabled through bit 6

(TNRZ) of the Mode Register (MR). When programmed to

‘‘0’’, it converts the bit stream from NRZ to NRZI. When

programmed to ‘‘1’’, the bit stream is transmitted NRZ.

1. No Injection (i.e. normal operation)

2. One Shot

3. Periodic

4. Continuous

In the No Injection mode, the data stream is transmitted

unchanged.

One Shot (Notes 1,3)

TL/F/11708–8

Periodic (Notes 2,3)

TL/F/11708–9

Continuous (Note 3)

TL/F/11708–10

e

Note 1: In one shot, when n 0, the JK is replaced

e

Note 2: In periodic, when n 0, all symbols are replaced.

e

Note 3: Max value on n 255.

FIGURE 3-7. Injection Modes

17

3.0 Functional Description (Continued)

respective data path. The first two are PHY Port interface

output data paths, A Indicate and B Indicate, that can

drive output data paths of the external PHY Port interface.

The third output data path is connected internally to the

Transmit Block.

3.4 CONFIGURATION SWITCH

Ð

The Configuration Switch consists of a set of multiplexers

a

and latches which allow the PLAYER device to configure

the data paths without any external logic. The Configuration

Switch is controlled through the Configuration Register

(CR).

The Configuration Switch is the same on the DP83256 de-

vice, the DP83256-AP device, and the DP83257 device.

However, the DP83257 has two PHY Port interfaces con-

nected to the Configuration Switch, whereas the DP83256

and DP83256-AP have one set of PHY port interfaces. The

DP83257 uses the A Request and A Indicate paths as

The Configuration Switch has four internal buses: the

Request bus, the B Request bus, the Receive bus, and

A

the PHY Invalid bus. The two Request buses can be driv-

Ð

en by external input data connected to the external PHY

Port interface. The Receive bus is internally connected to

Ð

one PHY Port interface and the B Request and B Indi-

Ð

a

PHY Invalid bus has a fixed 10-bit SMT PHY Invalid con-

the Receive Block of the PLAYER

device, while the

cate paths as the other PHY Port interface (SeeFigure 3-8 ).

The DP83256 and DP83256-AP, having one port interface,

use the B Request and A Indicate paths as its external

Ð

nection (LSU) pattern (1 0011 1010), which is useful during

the connection process.

Ð

port. The A Request and B Indicate paths of the

Ð Ð

DP83256 and DP83256-AP are null connections and are not

used by the device (See Figure 3-9 ).

The configuration switch also has three internal multiplex-

ers, each can select any of the four buses to connect to its

TL/F/11708–12

FIGURE 3-9. Configuration Switch

Block Diagram for DP83256

TL/F/11708–11

FIGURE 3-8. Configuration Switch

Block Diagram for DP83257

and DP83256-AP

18

3.0 Functional Description (Continued)

Dual Attach Station(DAS)

STATION CONFIGURATIONS

Single Attach Station (SAS)

A Dual Attach Station can be connected directly to the dual

ring, or, optionally to a concentrator. There are two types of

Dual Attach Stations: DAS with a single MAC and DAS with

two MAC layers. See Figure 3-12 and Figure 3-13.

The Single Attach Station can be connected to either the

Primary or Secondary ring via a Concentrator. Only 1 MAC

is needed in a SAS.

Two DP83256 or DP83256-AP parts can be connected to-

gether to build a Dual Attach Station, however this configu-

ration does not support the optional Thru B configuration.

When the optional Thru B configuration is desired, it is rec-

Ð

ommended that the DP83257 be used.

The DP83256, DP83256-AP, and DP83257 can be used in a

Single Attach Station. The DP83256 and DP83256-AP can

be connected to the MAC via its only PHY Port interface.

The DP83257 can be connected to the MAC via either one

of its 2 PHY Port Interfaces.

Ð

A DAS with a single MAC and two paths can be configured

as follows (see Figure 3-12 ):

See Figure 3-10 and Figure 3-11.

B Indicate data of PHY A is connected to A Request

Ð

input of PHY B. B Request input of PHY A is con-

#

Ð Ð

nected to A Indicate output of PHY B.

Ð

The MAC can be connected to either the A Request in-

#

put and the A Indicate output of PHY A or the B Re-

Ð

quest input and the B Indicate output of PHY B.

Ð

A DAS with a single MAC and one path using the DP83256

or DP83256-AP can be configured as follows (see Figure 3-

13 ):

B

output of PHY B.

Request input of PHY A is connected to A Indicate

Ð

#

Ð

The MAC is connected to the

B Request input of

#

PHY B and the A Indicate output of PHY A.

Ð

TL/F/11708–13

FIGURE 3-10. Single Attach Station

Using the DP83256 or DP83256-AP

A DAS with dual MACs can be configured as follows (see

Figure 3-14 ):

B Indicate data of PHY A is connected to A Request

Ð

input of PHY B. B Request input of PHY A is con-

#

Ð Ð

nected to A Indicate output of PHY B.

Ð

MAC 1 is connected to the B Indicate output and the

#

Ð

B

Request Input of PHY B.

Ð

MAC 2 is connected to the A Indicate output and the

Ð

A

Request Input of PHY A.

Ð

TL/F/11708–14

FIGURE 3-11. Single Attachment Station (SAS)

Using the DP83257

19

3.0 Functional Description (Continued)

TL/F/11708–15

FIGURE 3-12. Dual Attachment Station (DAS), Single MAC (DP83257)

TL/F/11708–16

FIGURE 3-13. Dual Attachment Station (DAS), Single MAC (DP83256/56-AP)

TL/F/11708–17

FIGURE 3-14. Dual Attachment Station (DAS), Dual MACs

20

3.0 Functional Description (Continued)

This may require external multiplexers, if used in conjunc-

tion with two other MAC layers.

CONCENTRATOR CONFIGURATIONS

There are 2 types of concentrators: Single Attach and Dual

Attach. These concentrators can be designed with or with-

out MAC(s). The configuration is determined based upon its

type and the number of active MACs in the concentrator.

Single Attach Concentrator

A Single Attach concentrator is a concentrator that has only

one PHY at the dual ring connect side. It cannot, therefore,

be connected directly to the dual ring. A Single Attach con-

centrator is a branch to the dual ring tree. It is connected to

the ring as a slave of another concentrator.

a

Using the PLAYER

device, a concentrator can be built

with many different configurations without any external log-

ic.

Multiple Single Attach concentrators can be connected to-

gether hierarchically to build a multiple levels of branches in

a dual ring.

The DP83256, DP83256-AP, and DP83257 can be used to

build a Single Attach concentrator.

See Application Note AN-675, Designing FDDI concentra-

tors and Application Note AN-741, Differentiating FDDI con-

centrators for further information.

The Single Attach concentrator can be connected to either

the primary or secondary ring depending on the connection

with its concentrator (the concentrator that it is connected

to as a slave).

Concepts

A concentrator is comprised of 2 parts: the Dual Ring Con-

nect portion and the Master Ports.

Figure 3-15 shows a Single Attach concentrator with a sin-

gle MAC.

The Dual Ring Connection portion connects the concentra-

tor to the dual ring directly or to another concentrator. If the

concentrator is connected directly to the dual ring, it is a

part of the ‘‘Dual Ring of Trees’’. If the concentrator is con-

nected to another concentrator, it is a ‘‘Branch’’ of the

‘‘Dual Ring of Trees’’.

Dual Attach Concentrator

A Dual Attach concentrator is a concentrator that has two

PHYs on the dual ring connect side. It is connected directly

to the dual ring and is a part of the dual ring tree.

The Dual Attach concentrator is connected to both the pri-

mary and secondary rings.

The Master Ports connect the concentrator to its ‘‘Slaves’’,

or S-class, Single Attach connections. A slave could be a

Single Attach Station or another concentrator (thus forming

another Branch of the Dual Ring Tree).

Dual Attach Concentrator with Single MAC

Figure 3-16 shows a Dual Attach concentrator with a single

MAC.

When a MAC in a concentrator is connected to the primary

or secondary ring, it is required to be situated at the exit port

of that ring (i.e. its PH IND is connected to the IND Inter-

face of the last Master Port in the concentrator (PHY M n)

Ð

that is connected to that ring).

Because the concentrator has one MAC, it can only transmit

and receive frames on the ring to which the MAC is con-

nected. The concentrator can only repeat frames on the

other ring.

Ð

Dual Attach Concentrator with Dual MACs

A concentrator can have two MACs, one connected to the

primary ring and one to the secondary ring. In addition, rov-

ing MACs can be included in the concentrator configuration.

A roving MAC can be used to test the stations connected to

the concentrator before allowing them to join the dual ring.

Figure 3-17 shows a Dual Attach concentrator with dual

MACs.

Because the concentrator has two MACs, it can transmit

and receive frames on both the primary and secondary

rings.

21

3.0 Functional Description (Continued)

TL/F/11708–18

TL/F/11708–19

TL/F/11708–20

FIGURE 3-15. Single Attach Concentrator (SAC), Single MAC

FIGURE 3-16. Dual Attach Concentrator (DAC), Single MAC

FIGURE 3-17. Dual Attach Concentrator (DAC), Dual MACs

22

3.0 Functional Description (Continued)

Another reference clock source option is a local 12.5 MHz

crystal circuit. An example crystal circuit with component

values is shown in Figure 3-19. This circuit is designed to

3.5 CLOCK GENERATION MODULE

The Clock Generation Module is an integrated phase locked

loop that generates all of the required clock signals for the

a

PLAYER device and the rest of an FDDI system from a

single 12.5 MHz reference.

operate with a crystal that has a C of 15 pF. The capacitor

L

values may need to be slightly adjusted for an individual

application to accomodate differences in parasitic loading.

The Clock Generation Module features:

The REF SEL signal selects between the two references.

Ð

High precision clock timing generated from

12.5 MHz reference.

a single

#

Multiple precision phased (8 ns/16 ns) 12.5 MHz Local

Byte Clocks to eliminate timing skew in large multi-board

concentrator configurations.

#

Component Values

Crystal: 12.50000 MHz

R:

270X 5%

C

:

56 pF (1%)

54 pF (1%)

ISO

:

LBC timing which is insensitive to loading variations over

a wide range (20 pF to 70 pF) of LBC loads.

#

IN

OUT

:

A selectable dual frequency system clock.

#

Low clock edge jitter, due to high VCO stability.

The Clock Generation Module is comprised of 6 main func-

tional blocks:

TL/F/11708–22

FIGURE 3-19. Crystal Circuit

PHASE COMPARATOR

Reference Selector

Phase Comparator

Loop Filter

250 MHz Voltage Controlled Oscillator

Output Phasing and Divide by 10

The Phase Comparator uses two signal inputs: the selected

12.5 MHz reference from the Reference Select Block and a

Local Byte Clock that has been selected for the feedback

input, FBK IN. Typically, LBC1 is used as the feedback

Ð

clock.

See Figure 3-18, Clock Generation Module Block Diagram.

REFERENCE SELECTOR

The Phase Comparator generates a pulse of current that is

proportional to the phase difference between the two sig-

nals. The current pulses are used to charge and discharge a

control voltage on the internal Loop Filter. This control volt-

age is used to minimize the phase difference between the

two signals.

The Reference Selector block allows the user to choose

between 2 sources for the Clock Generation Module’s

12.5 MHz reference clock.

The simplest reference clock source option is to use an

external 12.5 MHz reference signal fed into the REF IN

Ð

input. This input can come from a crystal oscillator module

a

or from a Local Byte Clock generated by another PLAYER

LOOP FILTER

device. Using the appropriate crystal oscillator ensures cor-

rect operating frequency without having to adjust any dis-

crete components.

The Loop Filter is a simple internal filter made up of one

capacitor in parallel with a serial capacitor and resistor com-

bination. One end of the filter is connected to Ground and

the other node is driven by the Phase Comparator and con-

trols the internal 250 MHz Voltage Controlled Oscillator.

This node can be examined for diagnostic purposes on the

LPFLTR pin when the FLTREN bit of the CGMREG register

is enabled. The LPFLTR pin is provided for diagnostic pur-

poses only and should not be connected in any application.

a

Using an LBC clock from another PLAYER device allows

one PLAYER device to create a master clock to which

a

other PLAYER devices in a system can be synchronized.

TL/F/11708–21

FIGURE 3-18. Clock Generation Module Block Diagram

23

3.0 Functional Description (Continued)

The voltage on the Loop Filter is set by the current pulses

generated by the Phase Comparator. The voltage on the

Loop Filter node controls the frequency of the 250 MHz

VCO.

3.6 STATION MANAGEMENT SUPPORT

The Station Management Support Block provides a number

of useful features to simplify the implementation of the Con-

nection Management (CMT) portion of SMT.

250 MHZ VOLTAGE CONTROLLED OSCILLATOR (VCO)

These features eliminate the most severe CMT response

time constraints imposed by the PC React and CF React

times. The many integrated counters and timers also elimi-

The internal Voltage Controlled Oscillator is a low gain VCO

whose primary frequency of oscillation centers around

250 MHz. The VCO produces little clock jitter due to its

exceptional stability under all circumstances.

Ð

nate the need for additional external devices.

The following CMT features are supported:

The VCO’s output frequency is proportional to the voltage

on the Loop Filter node.

PC React

Ð

CF React

Ð

Auto Scrubbing (TCF Timer)

#

OUTPUT PHASING

The Output Phasing block is a precision clock division circuit

that produces clock signals of 4 distinct frequencies. Within

the 12.5 MHz frequency, 5 clock signals with selectable 8 ns

or 16 ns phase difference are produced.

Timer, Idle Detection (TID Timer)

#

Noise Event Counter (TNE Timer)

Link Error Monitor (LEM Counter)

PC REACT

Ð

PC React is one of the timing restrictions imposed by Con-

The following clock signals are produced:

System Clock (CLK16/CLK32)

Local Symbol Clock (LSC)

Local Byte Clocks 1–5 (LBCn) (Divide by 10)

Ð

nection Management (CMT). It is one of the two most crit-

ical timing restrictions imposed (the other being CF Re-

act.)

Ð

System Clock (CLK16/CLK32)

The ANSI SMT standard states that ‘‘PC React is the max-

Ð

The System Clock is provided as an extra set of clock fre-

quencies that may be used as a clock for non-FDDI chipset

portions of a system or as a higher frequency System Inter-

face clock for the MACSI device. This clock is derived by

dividing the 125 MHz clock by 8 or 4 times.

[

]

imum time for PCM Physical Connection Management to

make a state transition to PC Break when QLS, a fault

Ð

condition, or PC Start signal is present. This maximum

Ð

time also places a limit on the time to react to a PC Stop

Ð

signal. This limitation does not apply to any other PCM tran-

The frequency is selectable through the CLKSEL bit of the

MODE2 register. The output has built-in glitch suppression

so that changing the CLKSEL bit will not result in glitches

appearing at the output.

sitions.’’ PC React puts a sharp time limit on how long it

Ð

takes to transition to the PC Break state and transmit the

Ð

correct line state when a PC Break transition is required.

Ð

s

The range for the timer is PC React

Ð

default value equal to 3.0 ms.

3.0 ms and has a

Local Symbol Clock (LSC)

The Local Symbol Clock is a 40% HIGH/60% LOW duty

cycle clock provided for use by the MACSI device and any

external logic that needs to be synchronized to the Symbol

timing.

a

The PLAYER device contains a Trigger Definition Regis-

ter and a set of CMT Condition Registers that can be used

to satisfy the PC React timing.

Ð

The Trigger Definition Register (TDR) controls two func-

tions. First, it allows the selection of the line state(s) on

which to trigger (SILS, MLS, HLS . . . ). For PC React, the

This clock is derived by dividing the 125 MHz clock by 5.

Local Byte Clocks 1–5 (LBCn)

Ð

The Local Byte Clocks are provided for use by the MACSI

device, by any external logic that needs to be synchronized

to the Byte timing, and for use in concentrators to synchro-

line states used would be the ones that caused a transition

to the PC Break state from the current PCM state.

Ð

Second, it allows specification of a line state to be transmit-

ted when the trigger condition is met. For PC React, this is

Ð

the line state that needs to be transmitted when a transition

to the PC Break state occurs, which is Quiet Line State

Ð

(QLS).

a

nize the timing between multiple PLAYER devices.

These clocks are derived by dividing the 125 MHz clock by

10. The different phase relationships between the LBCs are

achieved by tapping off of different outputs of a Johnson

counter inside the Output Phasing block.

The set of CMT Condition registers controls interrupt gener-

ation when a trigger condition occurs. The CMT Condition

Register set includes a CMT Condition Register (CMTCR), a

The phase relationship (separation by 8 ns or 16 ns) of the

LBCs is selected using the PH SEL pin.

Ð

One of the LBCs must be used as the source of the feed-

CMT Condition Comparison Register (CMTCCR), and

CMT Condition Mask Register (CMTCMR).

a

back input, FBK IN, which requires a 12.5 MHz frequency.

a

Ð

When the PLAYER device is using a crystal as a refer-

Line state triggering for PC React is enabled by selecting

Ð

line states to trigger on from the Trigger Definition Register

(TDR) bits 3-7.

ence it does not matter which LBC is used as the feedback

input. Typically the least loaded LBC is used. However,

when using an external reference that is supplied by anoth-

The Trigger Condition Occurred (TCO) bit of the CMTCR is

automatically set when the trigger condition specified by the

TDR register is met.

a

er PLAYER device, it is important to select the LBC that

keeps your system properly synchronized. Typically, all de-

vices will use LBC1 as the feedback input.

The line state specified by the Trigger Definition Register

(TDR) bits 0–2 is then loaded into the Current Transmit

Mode Register (CTSR), causing the line state to be trans-

mitted.

24

3.0 Functional Description (Continued)

If the TCO Mask (TCOM) bit of the CMTCMR is set, then

whenever the CMTCR.TCO bit becomes set the Receive

Condition Register B’s Connection Service Event

(RCRB.CSE) bit will be set. This allows an interrupt to be

generated for the trigger event.

AUTO SCRUBBING

Auto Scrubbing is an additional CMT feature that further

enhances the automatic configuration switch setting in or-

der to meet the CF React timing. When enabled, Auto

Ð

Scrubbing causes

2 PHY Invalid symbols followed by

Ð

As an example, suppose the PCM state machine is in the

ACTIVE state. From this state, if a Halt Line State (HLS) or

Quiet Line State (QLS) is detected, or the Noise Threshold

Scrub Symbol pairs (Idles) to be sourced for a user select-

able duration (the scrubbing time) after a trigger condition

(the same one used for PC React and CF React) occurs

and prior to a change in the configuration switch setting on

all indicate ports that will be changed.

Ð

is reached, the state machine must move to the PC Break

Ð

state and begin transmitting QLS. To implement this behav-

ior when the PC ACTIVE state is entered, set

Ð

Auto Scrubbing is enabled by setting the Enable Scrubbing

2

TDR.TTM2–0 to 110 (Quiet Transmit), set TDR.TOHLS,

TDR.TOQLS, and TDR.TONT and reset all other bits (TO-

SILS and TOMLS). Also set CMTCMR.TCOM if an interrupt

is desired.

on Trigger Conditions (ESTC) bit of Mode Register

(MODE2).

The Scrub Timer Threshold Register (STTR) defines the du-

ration of the scrubbing, which can last up to approximately

10ms. The Scrub Timer Value Register (STVR) can be used

to examine a snapshot of the upper 8 bits of the STTR

register.

CF REACT

Ð

CF React is one of the timing restrictions imposed by Con-

Ð

nection Management (CMT). It is one of the two most crit-

ical timing restrictions imposed (the other being

TIMER, IDLE DETECTION

PC React).

Ð

The ANSI SMT standard states that ‘‘CF React is the max-

The Idle Detection Timer is required to flag the continued

presence of the Idle Line State for a duration of 8 Idle Sym-

bol pairs plus 1 symbol pair.

Ð

[

]

imum time for CFM Configuration Management to recon-

figure to remove a non-Active connection from the token

path.’’

This feature is implemented in the Receiver Block by the

Super Idle Line State (SILS).

s

The range for the timer is CF React

Ð

default value equal to 3.0 ms.

3.0 ms and has a

NOISE EVENT COUNTER

a

The PLAYER device contains a Trigger Transition Config-

uration Register and a set of CMT Condition Registers that

The Noise Event Counter can be used to time the duration

between Noise Events (which are described in detail below)

and to count frame sizes. The first feature is the most often

recognized, but the second is often overlooked and can

lead to potential difficulty if not properly set.

can be used to satisfy the CF React timing.

Ð

he Trigger Transition Configuration Register (TTCR) holds

the new configuration switch settings to be loaded into the

Configuration Register (CR) when a trigger condition occurs.

The Noise Event Counter is implemented as a pair of down

counters: one the actual Noise Counter and the other a

Noise Counter Prescaling value. The Noise Threshold Reg-

ister (NTR) and the Noise Prescale Threshold Register

(NPTR) can be programmed to the counter’s initial value

while the Current Noise Count Register (CNCR) and the

Current Noise Prescale Count Register (CNPCR) provide a

snapshot of the actual counter.

Enabling line state triggering with the Trigger Definition Reg-

ister (TDR) bits 3–7 also enables the CF React response.

Ð

This means that whenever trigger conditions are actively

used for PC React, the value of the TTCR register will be

Ð

used also. This implies that it either must always then be

loaded with the current configuration setting, causing no

change to the CR, or it must be loaded with the appropriate

value to accommodate the CF React function.

Ð

The Noise Event Counter decrements whenever a Noise

Line State (NLS), Line State Unknown (LSU), or Active Line

State (ALS) is received and has its start value reloaded

whenever it receives Halt Line State (HLS), Idle Line State

(ILS), Master Line State (MLS), Quiet Line State (QLS), or

No Signal Detect (NSD). The Noise Event Counter is also

reset for a Start or End Delimiter. This means the Noise

counter increments for bad events as well as for every data

symbol in a frame. Should the Noise Counter expire, it indi-

cates that a new line state (including ALS) has not been

The Trigger Transition Configuration Register (TTCR) must

be set the configuration desired when the trigger condition

occurs. When the trigger condition occurs the value of this

register is loaded into the Configuration Register (CR). Dur-

ing this time writes to the CR are inhibited.

To continue the example from the PC React description,

Ð

suppose that when in the ACTIVE state for the PCM state

machine, the CFM state machine is also in the THRU A

state. If trigger conditions are enabled via the

CMTCMR.TCOM bit and it is desired to not implement CF

Ð

React, TTCR must be set to the present value of CR. If it is

Ð

entered for NT MAX time. This indicates that either a

Ð

frame is too long or that noise is being received.

For this reason it is important to choose a value for the

counter that is larger than the longest frame of 4500 bytes.

The ANSI SMT specification recommends a value for

NT MAX of 1.3ms for the noise threshold.

Ð

A Noise Event is defined as follows:

desired to not implement CF React then TTCR should be

Ð

set to the value which would change the configuration to the

WRAP state. The wrap conditions WRAP A or WRAP

Ð

B

Ð

depend on which PHY gets reconfigured.

A noise event is a noisebyte, or a byte of data which is not in

line with the current line state, indicating error or corruption.

25

3.0 Functional Description (Continued)

TABLE 3-5. Noise Event Description

LINK ERROR MONITOR

a

Link Error Monitoring is accomplished in the PLAYER de-

vice through the Link Error Monitor Counter. The initial value

of this down counter is set using the Link Error Threshold

Register (LETR). A snapshot of the counter can be taken

with the Current Link Error Count Register (CLECR).

e

E

a

]

CD

[

Noise Event

SD

#

E

#

a

e

a

]

AB)

]

SD CD PI

(II

JK

#

PI (PB

E

SD CD

II) AB

#

Where:

e

A Link Error is defined as follows:

Logical AND

Logical OR

Logical NOT

#

a

TABLE 3-6. Link Error Event Description

E

a

ILS

a

E

a

]

H)

[

Link Error

e

ALS (I

I

SD

xV

[

Vx

H

a

#

e

a

e

SD

CD

PB

PLS

PI

Signal Detect

Clock Detect

Previous Byte

E

a

E

a

]

JK)

]

ALS

ILS

(II

#

Event

E

e

]

SD)

ULS (PLS ALS)

#

SB

#

(HH HI

E

a

Link Error Flag

Ð

#

Ð

a

Previous Line State

a

]

II

JK)

e

a

QLS

#

PHY Invalid

a

HLS

a À

[

ULS PLS

MLS

(ALS

NLS

ILS)

e

]

TH)

a

RH

[

Set Link Error Flag

Ð

ALS (HH

#

NH

Ð

a

Ó

]

a

SH

ILS

Idle Line State

ALS

ULS

HLS

QLS

MLS

NLS

ULS

Active Line State

e

a

]

e

[

Clear Link Error Flag

Ð

ALS JK

#

Ð

Unknown Line State

Halt Line State

[

]

[

ILS JK

#

ULS (PLS ALS Link

#

HI

Ð

a

E

#

a

II

Error Flag

Ð

SB

(HH

#

Quiet Line State

Master Line State

Noise Line State

Unknown Line State

]

JK)

Where:

E

a

e

Logical NOT

Logical OR

Logical AND

e

I

Idle symbol

#

ILS

J

K

First symbol of start delimiter

Second symbol of start

Idle Line State

ALS

Active Line State

delimiter

ULS

Unknown Line State

Any symbol

e

R

S

T

A

B

n

Reset symbol

Set symbol

x

I

Idle symbol

End Delimiter

H

J

K

Halt symbol

a

n

R

S

T

First symbol of start delimiter

Second symbol of start

a

I

any data symbol

delimiter

e

V

R

S

T

Violation symbol

Reset symbol

Set symbol

End delimiter symbol

Data symbol converted to

N

a

0000 by the PLAYER device

Receiver Block in symbol pairs

that contain a data and a control

symbol

e

PLS

SD

Previous Line State

Signal Detect

SB

Stuff Byte: Byte inserted by EB

before a JK symbol pair for

recentering or due to off-axis JK

26

3.0 Functional Description (Continued)

3.7 PHY-MAC INTERFACE

to be in the Active Line State upon reception of the Starting

Delimiter (JK symbol pair).

NATIONAL BYTE-WIDE CODE

During Idle Line State any non Idle symbols will be reflected

as the code I uILS. If both symbols received during Idle Line

a

The PLAYER device outputs the National byte-wide code

Ê

State are Idle symbols, then the Symbol Decoder generates

from its PHY Port Indicate Output to the MAC device. Each

National byte-wide code may contain data or control codes

or the line state information of the connection. Table 3-7

lists all the possible outputs.

I kILS as its output. Note the coded Known/Unknown Bit

Ê

(b3) and the Last Known Line State (b2–0). The Receive

State is 4 bits long and it represents either the PHY Invalid

(0011) or the Idle Line State (1011) condition. The Known/

Unknown Bit shows if the symbols received match the line

state information in the last 3 bits.

During Active Line State all data and control symbols are

being repeated to the PHY Port Indicate Output with the

exception of data in data-control mixture bytes. That data

symbol is replaced by zero. If only one symbol in a byte is a

control symbol, the data symbol will be replaced by 0000

and the whole byte will be presented as control code. Note

that the Line State Detector recognizes the incoming data

During any line state other than Idle Line State or Active

Line State, the Symbol Decoder generates the code V kLS

Ê

if the incoming symbols match the current line state. The

symbol decoder generates V uLS if the incoming symbols

Ê

do not match the current line state.

TABLE 3-7. National Byte Wide Code

Symbol 1 Symbol 2

Control Bit Control Bit

National Code

Control Bit Data

Current Line State

ALS

Data

0

1

x

1

x

n

0

1

0

1

x

1

x

1

x

1

x

n

0

1

n-n

ALS

n

C

N-C

C-N

C-C

ALS

C

n

ALS

C

ILS

I

I -k-LS

Ê

ILS

I

Not I

I -u-LS

Ê

ILS

Not I

x

I

I -u-LS

Ê

ILS

Not I

x

I -u-LS

Ê

Stuff Byte during ILS

Not ALS and Not ILS

Stuff Byte during Not ALS

I -k-ILS

Ê

V -k-LS

M

Ê

M

Not M

M

V -u-LS

Ê

Not M

x

V -u-LS

Ê

Not M

x

V -u-LS

Ê

V -k-LS, V -u-LS

Ê

or L -u-ILS

Ê

EB Overflow/Underflow

1

0011 1011

0011 1010

1011 1000

SMT PI Connection (LSU)

Ð

Scrub Symbol Pair

Where:

e

À

Any data symbol in 0, 1, 2 . . . F

Ó

n

À Ó

Any control symbol in V, R, S, T, I, H

C

N

I

e

0000

Code for data symbol in a data control mixture byte

Idle Symbol

M

Any symbol that matches the current line state

e

I

Ê

1011

0011

First symbols of the byte in Idle Line State

PHY Invalid

V

Ê

LS

Line State

e

ALS

ILS

NSD

MLS

HLS

QLS

NLS

1

000

001

010

100

101

110

111

e

u

k

x

Indicates symbol received does not match current line state

Indicate symbol received matches current line state

0

Don’t care

27

3.0 Functional Description (Continued)

National Byte-Wide Code Example

Incoming 5B Code

98765 43210

Decoded 4B Code

National Byte-Wide Code (w/o parity)

7654 3210

C

1

0

3210

1010

1101

–––

C

1

0

3210

C

1

0

11111 11111 (II)

11000 10001 (JK)

1010 (II)

1102 (JK)

1011 0001 (I -k-ILS)*

Ê

1011 0001 (I -k-ILS)

Ê

1011 0001 (I -k-ILS)

Ê

1101 1101 (JK Symbols)

–––-

(xx)

–––

(xx)

–––

(Data Symbols)

–––

(More data

)

Ð

–––-

(xx)

0

1

–––

0

1

–––

(xx)

0

1

–––

(Data Symbols)

–––

01101 00111 (TR)

00111 00111 (RR)

11111 11111 (II)

00100 00100 (HH)

11111 11111 (II)

0101

0110

1010

0001

1010

0110 (TR)

0110 (RR)

1010 (II)

0101 0110 (T and R Symbols)

0110 0110 (Two R Symbols)

1010 1010 (Idle Symbols)

1010 (II)

1011 0001 (I -k-ILS)

Ê

1010 (II)

1011 0001 (I -k-ILS)

Ê

1010 (II)

1011 0001 (I -k-ILS)

Ê

0001 (HH)

1010 (II)

1011 1001 (I -u-ILS)

Ê

1011 1001 (I -u-ILS)

Ê

1011 1001 (I -u-ILS)

Ê

1011 1001 (I -u-ILS)

Ê

1011 1001 (I -u-ILS)

Ê

1011 1001 (I -u-ILS)

Ê

1011 1001 (I -u-ILS)

Ê

0011 0101 (V -k-HLS)

Ê

0011 0101 (V -k-HLS)

Ê

0011 0101 (V -k-HLS)

Ê

0011 1101 (V -u-HLS)

Ê

1010 (II)

1011 0001 (I -k-ILS)

Ê

1010 (II)

1011 0001 (I -k-ILS)

Ê

*Assume the receiver is in the Idle Line State.

28

3.0 Functional Description (Continued)

or clock generation function, such as

a Fiber Optic or

3.8 PMD INTERFACE

Shielded Twisted Pair (SDDI) PMDs. The second, Alternate

PMD Interface can be used to support Unshielded Twisted

Pair (UTP) PMDs that require external scrambling, and al-

lows implementation with no external clock recovery or

clock generation functions required. See Figure 3-21.

a

The PMD Interface connects the PLAYER

device to a

standard FDDI Physical Media Connection such as a fiber

optic transceiver or a copper twisted pair transceiver. It is a

125 MHz full duplex serial connection.

a

The DP83256 PLAYER device contains one PMD inter-

a

PLAYER TO PMD CONNECTIONS

face. This PMD Interface should be used for all PMD imple-

mentations that do not require an external scrambler/

descrambler function, clock recovery function, or clock

generation function, such as a Fiber Optic or Shielded

Twisted Pair (SDDI) PMDs.

a

The following figures illustrate how the PLAYER device

can be connected to various types of PMDs.

Figure 3-20 shows how the DP83256, DP83256-AP, or

a

DP83257 PLAYER device is connected to a Fiber Optic

or Shielded Twisted Pair (SDDI) PMD using the Primary

PMD Interface.

a

The DP83256-AP and DP83257 PLAYER devices contain

two PMD interfaces. The PMD Interface should be used for

all PMD implementations that do not require an external

scrambler/descrambler function, clock recovery function,

Figure 3-21 shows how the DP83256-AP or DP83257

a

PLAYER device is connected to an Unshielded Twisted

Pair (UTP) PMD using the Alternate PMD Interface.

TL/F/11708–47

FIGURE 3-20. Fiber Optic or STP PMD Connection

TL/F/11708–48

FIGURE 3-21. UTP PMD Connections

29

3.0 Functional Description (Continued)

INTERFACE ACTIVATION

in the CGMREG register. The transmit clocks are disabled

by default and should be left that way unless it is being

used.

The Primary PMD Interface is always enabled.

The Alternate PMD Interface is enabled by programming a

a

Note that when the Alternate PMD Interface is active, the

Primary PMD Interface can not be used without the Alter-

nate PMD Interface connections. Also note that the Long

Internal Loopback (LILB) can not be used when the Alter-

nate PMD Interface is activated.

PLAYER register bit. To enable the interface, write a 1 to

the APMDEN bit in the APMDREG register. The interface is

off by default and should be left that way unless it is being

used.

It will also probably be necessary to enable the Transmit

Clocks when using the Alternate PMD Interface. The Trans-

mit Clocks (TXC) are enabled by writing a 1 to the TXCE bit

30

4.0 Modes of Operation

a

The PLAYER device can operate in 4 basic modes: RUN,

STOP, LOOPBACK, and CASCADE.

4.1 RUN MODE

RUN is the normal mode of operation.

a

In this mode, the PLAYER device is configured to be con-

nected to the media via the PMD transmitter and PMD re-

ceiver at the PMD Interface. It is also connected to any

a

other PLAYER device(s) and/or MACSI device(s) via the

Port A and Port B Interfaces.

a

While operating in the RUN mode, the PLAYER device

receives and transmits Line States (Quiet, Halt, Master, Idle)

and frames (Active LIne State).

4.2 STOP MODE

a

The PLAYER device operates in the STOP mode while it

is being initialized or configured.

a

The PLAYER device is also reset to the STOP mode au-

tomatically when the RST pin is set to ground.

E

a

When in STOP mode, the PLAYER device performs the

following functions:

Resets the Repeat Filter.

#

Resets the Smoother.

#

Resets the Receiver Block Line State Counters.

#

Resets the Clock Recovery Module

#

Flushes the Elasticity Buffer.

#

Forces Line State Unknown in the Receiver Block.

#

TL/F/11708–23

Outputs PHY Invalid condition symbol pairs through the

#

FIGURE 4-1. Configuration Switch Loopback

for DP83257

k

l

PHY Data Indicate pins (AIP, AIC, AID 7:0 , BIP, BIC,

k

l

BID 7:0 ), when port is enabled.

Outputs Quiet symbol pairs through the PMD Data Re-

g

quest pins (PMRD ).

#

4.3 LOOPBACK MODE

a

The PLAYER device provides 3 types of loopback tests:

Configuration Switch Loopback, Short Internal Loopback,

and Long Internal Loopback. These Loopback modes can

be used to test different portions of the device.

Configuration Switch Loopback

The Configuration Switch Loopback can be used to test the

data paths of the MACSI device(s) that are connected to the

a

through the network.

PLAYER

device before transmitting and receiving data

a

In the Configuration Switch Loopback mode, the PLAYER

device Configuration Register (CR) can be programmed to

perform the following functions:

Select Port A PHY Request Data, Port B PHY Request

Data, or PHY Invalid to connect to Port A PHY Indicate

#

Data via the A IND Mux.

Ð

Select Port A PHY Request Data, Port B PHY Request

#

Data, or PHY Invalid to connect to Port B PHY Indicate

Data via the B IND Mux.

Ð

Connect data from the Receiver Block to the Transmitter

#

a

Block via the Transmitter Mux. (The PLAYER device

is repeating incoming data from the media in the Configu-

Ð

ration Switch Loopback mode.)

See Figure 4-1 and Figure 4-2.

TL/F/11708–24

FIGURE 4-2. Configuration Switch Loopback

for DP83256 and DP 83256-AP

31

4.0 Modes of Operation (Continued)

Short Internal Loopback

g

Ignores the PMD Data Indicate pins (PMID ),

#

The Short Internal Loopback mode can be used to test the

a

Clock Recovery function, and to test the data paths be-

Outputs Quiet symbols through the PMD Data Request

g

pins (PMRD ).

functionality of the PLAYER

device, not including the

The level of the Quiet symbols transmitted through the

g

PMRD pins during loopback is automatically set to the

transmitter off level.

a

tween the PLAYER

ring insertion.

device and MACSI devices before

a

When in the Short Internal Loopback mode, the PLAYER

device performs the following functions:

If both Short Internal Loopback and Long Internal Loopback

modes are selected, Long Internal Loopback mode will

have priority over Short Internal Loopback mode. This is the

Directs the output data of the Transmitter Block to the

input of the Receiver Block through an internal path.

#

a

longest loopback path within the PLAYER device.

See Figure 4-3, Short Internal Loopback.

TL/F/11708–25

FIGURE 4-3. Short Internal Loopback

32

4.0 Modes of Operation (Continued)

Long Internal Loopback

g

Ignores the PMD Data Indicate pins (PMID ),

#

The Long Internal Loopback mode implements the longest

a

loopback path that is completely within the PLAYER de-

vice.

Outputs Quiet symbols through the PMD Data Request

g

pins (PMRD ).

The level of the Quiet symbols transmitted through the

g

PMRD pins during loopback is automatically set to the

transmitter off level.

The Long Internal Loopback mode can be used to test the

a

functionality of the PLAYER device, including the Clock

Recovery function, and to test the data paths between the

If both Short Internal Loopback and Long Internal Loopback

modes are selected, Long Internal Loopback mode will

have priority over Short Internal Loopback mode. This is the

a

PLAYER device and MACSI devices before ring insertion.

a

When in the Long Internal Loopback mode, the PLAYER

device performs the following functions:

a

longest loopback path within the PLAYER device.

Directs the output data of the Transmitter Block to the

input of the Clock Recovery Module through an internal

path.

Note that the LILB path is disconnected and should not be

used when the Alternate PMD Interface is active.

#

See Figure 4-4, Long Internal Loopback.

TL/F/11708–26

FIGURE 4-4. Long Internal Loopback

33

4.0 Modes of Operation (Continued)

a

vice’s REF SEL pin is switched from using the REF IN

Reference Select Reset occurs when the PLAYER

de-

4.4 DEVICE RESET

Ð Ð

input to using a crystal with the XTAL IN and XTAL OUT

a

The revision B PLAYER device has five different levels of

Ð Ð

pins. This is the same as a Power Up Reset and is done

because the crystal is going from a dead stop to an active

state when REF SEL is switched. This reset, like the Pow-

Ð

er Up Reset, takes about 10 ms from the falling edge of

device ResetÐPower Up Reset, Hardware Reset, Player

Reset, Reference Select Reset, and Stop Mode. The Re-

sets can be used to return the whole device or a portion of

the device to its default configuration.

Power Up Reset begins automatically when power is first

a

applied to the PLAYER device and reaches a certain volt-

age level. Power Up Reset affects all of the modules in the

REF SEL.

Ð

Stop Mode is activated by writing a 0 to the RUN bit in the

Mode Register. Stop Mode is a selective reset that resets

the Clock Recovery Module and portions of the Player Mod-

ule.

a

PLAYER device, specifically the Clock Generation Mod-

ule (CGM), Clock Recovery Module (CRM), and the Player

Module, returning each module to its default configuration.

This reset begins by waiting for the crystal to stabilize, then

the CGM PLL proceeds to lock to the crystal and the rest of

Changes from Revision A to Revision B:

The previous descriptions describe the reset logic in the

a

revision B PLAYER device. Two changes were made to

the original revision A PLAYER device reset logic.

a

the PLAYER device is reset. This reset takes the longest

amount of time at approximately 10 ms from the time the

a

PLAYER

device’s power supply reaches 4.4V. Even

First, the Hardware Reset was shortened by eliminating the

requirement of having to wait for the crystal to settle before

letting the Clock Generation Module try to lock to the crys-

a

tal. This behavior is correct because the PLAYER device

has already waited for the crystal to settle once during the

though the Power Up Reset is usually effective, due to the

variation in the start-up conditions of a systems power sup-

ply, the Power Up Reset trigger can not be guaranteed to

operate correctly. Therefore, a Hardware Reset should al-

ways be performed on the PLAYER after waiting a mini-

mum of 10 ms for the Power Up Reset to complete its reset

attempt.

a

Power Up Reset. The revision A PLAYER follows a Power

Up Reset cycle when Hardware Reset is activated.

Second, a full Power Up Reset is now done when the clock

reference is switched to the crystal. This is necessary to

allow the crystal time to start up when it is switched to from

a

Hardware Reset occurs at the rising edge of PLAYER

E

device’s RST pin. Hardware Reset affects all of the mod-

ules in the PLAYER device, specifically the CGM, CRM

a

the REF IN input. This reset is not performed on the revi-

a

Ð

sion A PLAYER

and the Player Module, returning each module to its default

configuration. During Hardware Reset it is not necessary to

force the Clock Generation Module to wait for the crystal to

settle again at this time because it has settled in the time

since the initial reset at power up. This reset takes the sec-

ond longest amount of time at approximately 1 ms from the

.

Recommendations:

The following are some recommendations for using the re-

a

set mechanisms of the PLAYER most effectively:

1. Always wait a minimum of 10 ms after power-up before

a

E

rising edge of RST.

doing anything to the PLAYER device. 10 ms is a mini-

mum, it may be desirable to wait longer if the system

power supply or clock reference has not stabilized by this

time.

Player Reset is activated by writing a 1 to the PHYRST bit in

Mode Register 2. Player Reset only affects the Player Mod-

ule. This reset is the shortest and only takes about 3 ms

from the completion of the register write. The device should

not be accessed by the Control Bus during this reset.

a

2. Always use the Hardware Reset to reset the PLAYER

device after Power Up. This should be done after the

initial Power Up waiting period of at least 10 ms.

34

4.0 Modes of Operation (Continued)

Data frames must be a minimum of three bytes long

(including the JK symbol pair). Smaller frames will

cause Elasticity Buffer errors.

#

4.5 CASCADE MODE

a

The PLAYER device can operate in the Cascade (paral-

lel) mode (Figure 4-5) which is used in high bandwidth,

point-to-point data transfer applications. This is a non-FDDI

mode of operation. This is only available on the DP83257

device.

Data frames must have a maximum size of 4500 bytes,

with a JK starting delimiter and a T or R or S ending

delimiter.

3. Due to the different clock rates, the JK symbol pair may

a

arrive at different times at each PLAYER device. The

total skew between the fastest and slowest cascaded

Concepts

a

In the Cascade mode, multiple PLAYER devices are con-

nected together to provide data transfer at multiples of the

a

must not exceed 80 ns.

PLAYER

devices receiving the JK starting delimiter

a

FDDI data rate. Two cascaded PLAYER devices provide

data rate twice the FDDI data rate; three cascaded

a

4. The first PLAYER device to receive a JK symbol pair

will present it to the host system and release the Cas-

a

PLAYER devices provide a data rate three times the FDDI

data rate, etc.

a

cade Ready signal. The PLAYER

device will present

Multiple data streams are transmitted in parallel over each

a

pair of cascaded PLAYER devices. All data streams start

simultaneously and begin with the JK symbol pair on each

a

one more JK as it waits for the other PLAYER devices

to recognize their JK. The maximum number of consecu-

tive JKs that can be presented to the host is 2.

a

PLAYER device.

5. The Cascade Start signal is set to 1 when all the cascad-

a

ed PLAYER devices release their Cascade Ready sig-

nals.

a

Data is synchronized at the receiver of each PLAYER de-

vice by the JK symbol pair. Upon receiving a JK symbol pair,

a

a PLAYER device asserts the Cascade Ready signal to

indicate the beginning of data reception.

6. Bit 4 (CSE) of the Receive Condition Register B (RCRB)

is set to 1 if the Cascade Start signal (CS) is not set

before the second falling edge of clock signal LBC from

when Cascade Ready (CR) was released. CS has to be

set approximately within 80 ns of CR release. This condi-

a

The Cascade Ready signals of all PLAYER devices are

open drain ANDed together to create the Cascade Start

signal. The Cascade Start signal is used as the input to

a

indicate that all PLAYER devices have received the JK

a

tion signifies that not all cascaded PLAYER

devices

symbol pair. Data is now being received at every PLAYER

device and can be transferred from the cascaded

have received their respective JK symbol pair with the

allowed skew range.

a

PLAYER devices to the host system.

a

7. PLAYER devices may not report a Cascaded Synchro-

See Figure 4-6 for more information.

nization Error if the JK symbols are corrupted in the point-

to-point links.

Operating Rules

a

When the PLAYER device is operating in Cascade mode,

the following rules apply:

8. To guarantee integrity of the interframe information, the

user must put at least 8 Idle symbol pairs between

a

1. Data integrity can be guaranteed if the worst case PMD

transmission skew between parallel media is less than

40 ns. For example, this amounts to about 785 meters of

fiber optic cable, assuming a 1% worst case variance.

frames. The PLAYER device will function properly with

only 4 Idle symbol pairs, however the interframe symbols

may be corrupted with random non-JK symbols.

The MACSI device could be used to provide the required

framing and optional FCS support.

2. Even though this is a non-FDDI application, the general

rules for FDDI frames must be obeyed.

35

4.0 Modes of Operation (Continued)

TL/F/11708–27

FIGURE 4-5. Parallel Transmission

TL/F/11708–28

FIGURE 4-6. Cascade Mode of Operation

36

5.0 Registers

a

The PLAYER device can be initialized, configured, and monitored using 64 8-bit registers. These registers are accessible

through the Control Bus Interface.

The following tables summarize each register’s attributes.

Note: RESERVED Registers may be read at any time, although the values read are not specified. The results of RESERVED Register writes are not specified, and

may have adverse implications. The user should not write to RESERVED Register locations.

TABLE 5-1. Register Summary

Access Rules

Write

Always

Register

Address

Register

Symbol

Register Name

Read

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

MR

Mode Register

Always

CR

Configuration Register

Conditional

Always

ICR

Interrupt Condition Register

ICMR

CTSR

IJTR

Interrupt Condition Mask Register

Current Transmit State Register

Injection Threshold Register

Conditional

Always

ISRA

Injection Symbol Register A

Always

ISRB

Injection Symbol Register B

Always

CRSR

RCRA

RCRB

RCMRA

RCMRB

NTR

Current Receive State Register

Receive Condition Register A

Receive Condition Register B

Receive Condition Mask Register A

Receive Condition Mask Register B

Noise Threshold Register

Write Reject

Conditional

Always

NPTR

CNCR

CNPCR

STR

Noise Prescale Threshold Register

Current Noise Count Register

Current Noise Prescale Count Register

State Threshold Register

Always

Write Reject

Always

SPTR

CSCR

CSPCR

LETR

CLECR

UDR

State Prescale Threshold Register

Current State Count Register

Current State Prescale Count Register

Link Error Threshold Register

Current Link Error Count Register

User Definable Register

Always

Write Reject

Always

Write Reject

Always

IDR

Device ID Register

Write Reject

Always

CIJCR

ICCR

Current Injection Count Register

Interrupt Condition Comparison Register

Current Transmit State Comparison Register

Receive Condition Comparison Register A

CTSCR

RCCRA

Always

37

5.0 Registers (Continued)

TABLE 5-1. Register Summary (Continued)

Access Rules

Write

Register

Address

Register

Symbol

Register Name

Read

Always

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

RCCRB

MODE2

CMTCCR

CMTCR

CMTMR

RR22

Receive Condition Comparison Register B

Mode Register 2

Always

Conditional

CMT Condition Comparison Register

CMT Condition Register

CMT Condition Mask Register

Reserved Register 22

Always

Conditional

Always

DO NOT WRITE

Always

RR23

Reserved Register 23

STTR

Scrub Timer Threshold Register

Scrub Timer Value Register

Trigger Definition Register

Trigger Transition Configuration Register

Reserved Register 28

STVR

Write Reject

TDR

Always

TTCR

Always

RR28

DO NOT WRITE

Always

RR29

Reserved Register 29

RR2A

RR2B

RR2C

RR2D

RR2E

Reserved Register 2A

Reserved Register 2B

Reserved Register 2C

Reserved Register 2D

Reserved Register 2E

RR2F

Reserved Register 2F

RR30

Reserved Register 30

RR31

Reserved Register 31

RR32

Reserved Register 32

RR33

Reserved Register 33

RR34

Reserved Register 34

RR35

Reserved Register 35

RR36

Reserved Register 36

RR37

Reserved Register 37

RR38

Reserved Register 38

RR39

Reserved Register 39

RR3A

CGMREG

APMDREG

GAINREG

RR3E

Reserved Register 3A

Clock Generation Module Register

Alternate PMD Register

Gain Register

Always

Reserved Register 3E

DO NOT WRITE

RR3F

Reserved Register 3F

38

5.0 Registers (Continued)

TABLE 5-2. Register Bit Summary

Bit Symbols

Register

Address

Register

Symbol

D7

RNRZ

BIE

D6

TNRZ

AIE

D5

TE

D4

TQL

D3

CM

D2

EXLB

BIS0

CCR

D1

ILB

D0

RUN

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

MR

CR

TRS1

RCA

TRS0

LEMT

LEMTM

IC1

BIS1

AIS1

CPE

AIS0

DPE

ICR

UDI

RCB

CWI

ICMR

CTSR

IJTR

UDIM

RES

RCBM

PRDPE

IJT6

RCAM

SE

CWIM

IC0

CCRM

TM2

CPEM

TM1

DPEM

TM0

IJT7

IIJ5

IJT4

IJT3

IJT2

IJT1

IJT0

ISRA

RES

IJS4

IJS3

IJS2

IJS1

IJS0

ISRB

RES

IJS9

IJS8

IJS7

IJS6

IJS5

CRSR

RCRA

RCRB

RCMRA

RCMRB

NTR

RES

LSU

LS2

LS1

LS0

LSUPI

RES

LSC

NT

NLS

MLS

HLS

QLS

NSD

SILS

EBOU

NTM

EBOUM

NT5

CSE

LSUPV

MLSM

LSUPVM

NT3

ALS

ST

ILS

LSUPIM

RES

LSCM

SILSM

NT6

NLSM

CSEM

NT4

HLSM

ALSM

NT2

QLSM

STM

NT1

NSDM

ILSM

NT0

RES

NPTR

CNCR

CNPCR

STR

NPT7

NCLSCD

CNPC7

RES

NPT6

CNC6

CNPC6

ST6

NPT5

CNC5

CNPC5

ST5

NPT4

CNC4

CNPC4

ST4

NPT3

CNC3

CNPC3

ST3

NPT2

CNC2

CNPC2

ST2

NPT1

CNC1

CNPC1

ST1

NPT0

CNC0

CNPC0

ST0

SPTR

CSCR

CSPCR

LETR

CLECR

UDR

SPT7

SCLSCD

CSPC7

LET7

LEC7

RES

SPT6

CSC6

CSPC6

LET6

LEC6

RES

SPT5

CSC5

CSPC5

LET5

LEC5

RES

SPT4

CSC4

CSPC4

LET4

LEC4

RES

SPT3

CSC3

CSPC3

LET3

LEC3

EB1

SPT2

CSC2

CSPC2

LET2

LEC2

EB0

SPT1

CSC1

CSPC1

LET1

LEC1

SB1

SPT0

CSC0

CSPC0

LET0

LEC0

SB0

IDR

DID7

DID6

IJC6

DID5

IJC5

DID4

IJC4

DID3

IJC3

DID2

IJC2

DID1

IJC1

DID0

IJC0

CIJCR

ICCR

IJC7

UDIC

RESC

LSUPIC

RESC

ESTC

TCOC

TCO

RCBC

PRDPEC

LSCC

SILSC

RES

RCAC

SEC

LEMTC

IC1C

NLSC

CSEC

RES

CWIC

IC0C

MLSC

LSUPVC

RES

CCRC

TM2C

HLSC

ALSC

RES

CPEC

TM1C

QLSC

STC

DPEC

TM0C

NSDC

ILSC

PHYRST

RES

CTSCR

RCCRA

RCCRB

MODE2

CMTCCR

CMTCR

CMTMR

RR22

NTC

EBOUC

CLKSEL

RES

CBPE

RES

STEC

STE

RES

TCOM

RES

STEM

RES

39

5.0 Registers (Continued)

TABLE 5-2. Register Bit Summary (Continued)

Bit Symbols

Register

Address

Register

Symbol

D7

RES

STT7

STV7

TONT

BIE

D6

RES

STT6

STV6

TOQLS

AIE

D5

RES

D4

RES

D3

RES

D2

RES

STT2

STV2

TTM2

BIS0

RES

D1

RES

STT1

STV1

TTM1

AIS1

RES

D0

RES

STT0

STV0

TTM0

AIS0

RES

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

RR23

STTR

STVR

TDR

STT5

STV5

TOHLS

TRS1

RES

FLTREN

RES

FILT0

RES

STT4

STV4

TOMLS

TRS0

RES

STT3

STV3

TOSILS

BIS1

RES

TXCE

APMDEN

RES

TTCR

RR28

RR29

RR2A

RR2B

RR2C

RR2D

RR2E

RR2F

RR30

RR31

RR32

RR33

RR34

RR35

RR36

RR37

RR38

RR39

RR3A

CGMREG

APMDREG

GAINREG

RR3E

RR3F

RES

FILT2

RES

FILT1

RES

40

5.0 Registers (Continued)

TABLE 5-3. Register Reset Value Summary

Reset Contents

Register

Address

Symbol

MSB-LSB

00 h

Comments

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

MR

CR

00 h

ICR

X001 0000 B

00 h

depends on sense pins

ICMR

CTSR

IJTR

A2 h

00 h

ISRA

00 h

ISRB

00 h

CRSR

RCRA

RCRB

RCMRA

RCMRB

NTR

0A h

20 h

00X0 0010 B

00 h

depends on EB state

00 h

NPTR

CNCR

CNPCR

STR

00 h

SPTR

CSCR

CSPCR

LETR

CLECR

UDR

00 h

000X 00XX B

XX h

depends on sense pins

depends on chip version

IDR

CIJCR

ICCR

00 h

same as reg 02 h if reg 02 h is read first

same as reg 04 h if reg 04 h is read first

same as reg 09 h if reg 09 h is read first

same as reg 0A h if reg 0A h is read first

CTSCR

RCCRA

RCCRB

00 h

41

5.0 Registers (Continued)

TABLE 5-3. Register Reset Value Summary (Continued)

Reset Contents

Register

Address

Register

Symbol

MSB-LSB

00 h

XX h

00 h

XX h

05 h

00 h

XX h

Comments

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

MODE2

CMTCCR

CMTCR

CMTMR

RR22

RR23

STTR

STVR

TDR

TTCR

RR28

RR29

RR2A

RR2B

RR2C

RR2D

RR2E

RR2F

RR30

RR31

RR32

RR33

RR34

RR35

RR36

RR37

RR38

RR39

RR3A

CGMREG

APMDREG

GAINREG

RR3E

RR3F

42

5.0 Registers (Continued)

5.1 MODE REGISTER (MR)

a

The Mode Register is used to initialize and configure the PLAYER device.

ACCESS RULES

ADDRESS

READ

WRITE

00h

Always

D7

D6

D5

D4

TQL

D3

D2

D1

D0

RNRZ

TNRZ

TE

CM

LILB

SILB

RUN

Bit Symbol

Description

E

RUN/ STOP:

D0 RUN

0: Enables the STOP mode. Refer to section 4.2, STOP MODE, for more information.

1: Normal operation (i.e. RUN mode).

E

Note: The RUN bit is automatically set to 0 when the RST pin is asserted (i.e. set to ground).

D1 SILB

SHORT INTERNAL LOOPBACK:

0: Disables Internal Loopback mode (i.e. normal operation).

1: Enables Internal Loopback mode.

Refer to section 4.3, LOOPBACK MODE, for more information.

D2 LILB

LONG INTERNAL LOOPBACK:

0: Disables Long Internal Loopback mode (i.e. normal operation).

1: Enables Long Internal Loopback mode.

Note: Long Internal Loopback should not be used when the Alternate PMD Interface is enabled.

Refer to section 4.3, LOOPBACK MODE, for more information.

D3 CM

D4 TQL

D5 TE

CASCADE MODE:

a

0: Disables synchronization of cascaded PLAYER devices.

1: Enables the synchronization of cascaded PLAYER devices.

a

Refer to section 4.4, CASCADE MODE, for more information.

Note: Cascade Mode is only available on the DP83257 device. The other devices do not have the required CS and CR pins. Do not set this bit for

any device but the DP83257.

TRANSMIT QUIET LEVEL: This bit is used to program the transmission level of the Quiet symbols during Off

Transmit mode (OTM) only.

a e

0: Low (PMD OFF) level Quiet symbols are transmitted through the PMD Data Request pins (i.e. PMRD

b e

low,

PMRD

1: High (PMD ON) level Quiet symbols are transmitted through the PMD Data Request pins (i.e. PMRD

b e

high).

high,

PMRD

low).

TRANSMIT ENABLE: The TE bit controls the action of the PMD transmitter Enable (TXE) pin. When TE is 0, the

TXE output disables the PMD transmitter; when TE is 1, the PMD transmitter is disabled during the Off Transmit

Mode (OTM) and enabled otherwise. The On and Off level of the TXE is depended on the PMD transmitter Enable

a

Level (TEL) pin to the PLAYER device. The following rules summaries the output of TXE.

e

1. If TE 0, then TXE Off

2. If TE 1 and OTM, then TXE Off

e

3. If TE 1 and not OTM, then TXE On.

D6 TNRZ

D7 RNRZ

TRANSMIT NRZ DATA:

0: Transmits data in Non-Return-To-Zero-Invert-On-Ones (NRZI) format (normal format).

1: Transmits data in Non-Return-To-Zero format (NRZ).

RECEIVE NRZ DATA:

0: Receives data in Non-Return-To-Zero-Invert-On-Ones format (NRZI) (normal format).

1: Receives data in Non-Return-To-Zero format (NRZ).

43

5.0 Registers (Continued)

5.2 CONFIGURATION REGISTER (CR)

The Configuration Register controls the Configuration Switch Block and enables/disables both the A and B ports. The CR can

be used to create a number of Configuration Loopback paths.

The CR is conditionally writable because the TTCR can be writing a new value into the register if this feature is enabled.

Note that the A Request and B Indicate port are offered only on the DP83257, and not in the DP83256. For further informa-

Ð Ð

tion, refer to section 3.4, CONFIGURATION SWITCH.

ACCESS RULES

ADDRESS

READ

WRITE

01h

Always

Conditional

D7

D6

D5

TRS1

D4

D3

D2

D1

D0

BIE

AIE

TRS0

BIS1

BIS0

AIS1

AIS0

Bit

Symbol

Description

k l k l

INDICATE SELECTOR 0, 1 : The A Indicate Selector 0, 1 bits selects one of the four

Ð

D0, D1 AIS0, AIS1

A

Ð

k

l

Configuration Switch data buses for the A Indicate output port (AIP, AIC, AID 7:0 ).

Ð

AIS1

AIS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

k l k l

B INDICATE SELECTOR 0, 1 : The B Indicate Selector 0, 1 bits selects one of the four

Ð Ð

D2, D3 BIS0, BIS1

k

l

)

Configuration Switch data buses for the B Indicate output port (BIP, BIC, BID 7:0

Ð

BIS1

BIS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

Note: Even though this bit can be set and/or cleared in the DP83256, it will not affect any I/Os since the DP83256 does not offer a

Indicate port.

B

Ð

k

l

k

l

D4, D5 TRS0, TRS1 TRANSMIT REQUEST SELECTOR 0, 1 : The Transmit Request Selector 0, 1 bits select one of

the four Configuration Switch data buses for the input to the Transmitter Block.

TRS1 TRS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

k

l

Note: If the PLAYER device is in Active Transmit Mode (i.e. the Transmit Mode bits (TM 2:0 ) of the Current Transmit State

a

Register (CTSR) are set to 00) and the PHY Invalid Bus is selected, then the PLAYER device will transmit a maximum of four

a

Halt symbol pairs and then continuous Idle symbols due to the Repeat Filter when in the Repeat state.

D6

D7

AIE

BIE

A

INDICATE ENABLE:

Ð

0: Disables the A Indicate output port. The A Indicate port pins will be tri-stated when the port is

Ð

disabled.

k

l

1: Enables the A Indicate output port (AIP, AIC, AID 7:0 ).

Ð

B

INDICATE ENABLE:

Ð

0: Disables the B Indicate output port. The B Indicate port pins will be tri-stated when the port is

Ð

disabled.

k

l

1: Enables the B Indicate output port (BIP, BIC, BID 7:0 ).

Ð

Note: Even though this bit can be set and/or cleared in the DP83256, it will not affect any I/Os since the DP83256 does not offer a

B

Indicate port.

Ð

44

5.0 Registers (Continued)

5.3 INTERRUPT CONDITION REGISTER (ICR)

The Interrupt Condition Register records the occurrence of an internal error event, the detection of Line State, an unsuccessful

write by the Control Bus Interface, the expiration of an internal counter, or the assertion of one or more of the User Definable

Sense pins.

E

The Interrupt Condition Register will assert the Interrupt pin ( INT) when one or more bits within the register are set to 1 and

the corresponding mask bits in the Interrupt Condition Mask Register (ICMR) are also set to 1.

ACCESS RULES

ADDRESS

READ

WRITE

02h

Always

Conditional

D7

D6

D5

RCA

D4

D3

D2

D1

D0

UDI

RCB

LEMT

CWI

CCR

CPE

DPE

Bit Symbol

Description

D0 DPE

PHY REQUEST DATA PARITY ERROR: This bit will be set to 1 when:

Ð Ð

1. The PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register (CTSR) is set to 1 and

2. The Transmitter Block detects a parity error in the incoming PHY Request Data.

The source of the data can be from the PHY Invalid Bus, the Receive Bus, the A Bus, or the B Bus of the

Ð

Configuration Switch.

Note: Parity is only checked on data that goes into the transmitter block. This means that any data that is just routed through the configuration

switch without going into the transmit block is not checked.

D1 CPE

D2 CCR

Control Bus DATA PARITY ERROR: This bit will be set to 1 when the Control Bus Interface detects a parity error

k

l

in the incoming Control Bus Data (CBD 7:0 ), CBP during a write cycle.

Control Bus WRITE COMMAND REJECT: This bit will be set to 1 when an attempt to write into one of the

following read-only registers is made:

Current Receive State Register (Register 08, CRSR)

Current Noise Count Register (Register 0F, CNCR)

Current Noise Prescale Count Register (Register 10, CNPCR)

Current State Count Register (Register 13, CSCR)

Current State Prescale Count Register (Register 14, CSPCR)

Current Link Error Count Register (Register 16, CLECR)

Device ID Register (Register 18, IDR)

Current Injection Count Register (Register 19, CIJCR)

Scrub Timer Value Register (Register 25, STVR)

45

5.0 Registers (Continued)

Bit Symbol

Description

D3 CWI

CONDITIONAL WRITE INHIBIT: Set to 1 when bits within mentioned registers do not match bits in the

corresponding compare register. This bit ensures that new (i.e. unread) data is not inadvertently cleared while old

data is being cleared through the Control Bus Interface.

This bit is set to 1 to indicate that a bit in a condition write register was not written because it had changed since

the previous read. The following registers are affected:

Interrupt Condition Register (Register 02, ICR)

Current Transmit State Register (Register 04, CTSR)

Receive Condition Register A (Register 09, RCRA)

Receive Condition Register B (Register 0A, RCRB)

CMT Condition Register (Register 20, CMTCR)

The previous registers are affected when they differ from the value of the corresponding bit in the following

registers respectively:

Interrupt Condition Compare Register (Register 1A, ICCR)

Current Transmit State Compare Register (Register 1B, CTSCR)

Receive Condition Compare Register A (Register 1C, RCCRA)

Receive Condition Compare Register B (Register 1D, RCCRB)

CMT Condition Compare Register (Register 1F, CMTCCR)

This bit must be cleared by software. Note that this differs from the MACSI, BMAC and BSI device bits of the same

name.

The Configuration Register (Register 01, CR) can not be written to during scrubbing.

D4 LEMT

LINK ERROR MONITOR THRESHOLD: This bit is set to 1 when the internal 8-bit Link Error Monitor Counter

reaches zero. It will remain set and is cleared by software.

E

e

During the reset process (i.e. RST GND), the Link Error Monitor Threshold bit is set to 1 because the Link

Error Monitor Counter is initialized to zero.

D5 RCA

RECEIVE CONDITION A: This bit is set to 1 when:

1. One or more bits in the Receive Condition Register A (RCRA) is set to 1 and

2. The corresponding mask bits in the Receive Condition Mask Register A (RCMRA) are also set to 1.

In order to clear (i.e. set to 0) the Receive Condition A bit, the bits within the Receive Condition Register A that are

set to 1 must first be either cleared or masked.

D6 RCB

RECEIVE CONDITION B: This bit is set to 1 when:

1. One or more bits in the Receive Condition Register B (RCRB) is set to 1 and

2. The corresponding mask bits in the Receive Condition Mask Register A (RCMRB) are also set to 1.

In order to clear (i.e. set to 0) the Receive Condition B bit, the bits within the Receive Condition Register B that are

set to 1 must first be either cleared or masked.

D7 UDI

USER DEFINABLE INTERRUPT: This bit is set to 1 when one or any combination of the Sense Bits (SB0, SB1, or

SB2) in the User Definable Register (UDR) are set to 1.

In order to clear (i.e. set to 0) the User Definable Interrupt Bit, all Sense Bits must be set to 0.

46

5.0 Registers (Continued)

5.4 INTERRUPT CONDITION MASK REGISTER (ICMR)

The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt.

E e

The Interrupt pin will be asserted (i.e. INT GND) when one or more bits within the Interrupt Condition Register (ICR) are set

to 1 and the corresponding mask bits in this register are also set to 1.

This register is cleared (i.e. set to 0) and all interrupts are initially masked during the reset process.

ACCESS RULES

ADDRESS

READ

WRITE

03h

Always

D7

D6

D5

D4

LEMTM

D3

D2

D1

D0

UDIM

RCBM

RCAM

CWIM

CCRM

CPEM

DPEM

Bit Symbol

Description

D0 DPEM

PHY REQUEST DATA PARITY ERROR MASK: The mask bit for the PHY Request Data Parity Error bit

Ð Ð Ð

(DPE) of the Interrupt Condition Register (ICR).

D1 CPEM

D2 CCRM

D3 CWIM

Control Bus DATA PARITY ERROR MASK: The mask bit for the Control Bus Data Parity Error bit (CPE) of the

Interrupt Condition Register (ICR).

Control Bus WRITE COMMAND REJECT MASK: The mask bit for the Control Bus Write Command Reject bit

(CCR) of the Interrupt Condition Register (ICR).

CONDITIONAL WRITE INHIBIT MASK: The mask bit for the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR).

D4 LEMTM LINK ERROR MONITOR THRESHOLD MASK: The mask bit for the Link Error Monitor Threshold bit (LEMT) of

the Interrupt Condition Register (ICR).

D5 RCAM

D6 RCBM

D7 UDIM

RECEIVE CONDITION A MASK: The mask bit for the Receive Condition A bit (RCA) of the Interrupt Condition

Register (ICR).

RECEIVE CONDITION B MASK: The mask bit for the Receive Condition B bit (RCB) of the Interrupt Condition

Register (ICR).

USER DEFINABLE INTERRUPT MASK: The mask bit for the User Definable Interrupt bit (UDI) of the Interrupt

Condition Register (ICR).

47

5.0 Registers (Continued)

5.5 CURRENT TRANSMIT STATE REGISTER (CTSR)

The Current Transmit State Register can program the Transmitter Block to internally generate and transmit Idle, Master, Halt,

Quiet, or user programmable symbol pairs, in addition to the normal transmission of incoming PHY Request data. The Smoother

and PHY Request Data Parity are also enabled and disabled through this register.

When the Trigger Definition register (TDR) is used, the CTSR can automatically be set to a preprogrammed line state when a

trigger condition occurs. This capability can be used to implement both PC React and CF React.

Ð

The Transmit Modes have priority over the Repeat Filter and Smoother outputs. The Injection Symbols have priority over the

Transmit Modes.

k

l

e

is set to 1), and the Reserved bit (b7) is set to 1. All other bits of this register are cleared (i.e. set to 0) during the reset process.

E

e

During the reset process (i.e. RST GND) the Transmit Mode is set to Off (TM 2:0

010), the Smoother is enabled (i.e. SE

When the TDR register is used to respond to trigger conditions the CTSR will be blocked when the TDR register transmit mode

is copied into the CTSR. The Write Reject bit of the ICR will be set if any writes are attempted at this time.

Note: This register has no effect while the device is in Stop Mode.

ACCESS RULES

ADDRESS

READ

WRITE

04h

Always

Conditional

D7

D6

D5

SE

D4

D3

D2

D1

D0

RES

PRDPE

IC1

IC0

TM2

TM1

TM0

Bit

Symbol

Description

k

l

D0, D1, TM0, TM1, Transmit Mode 0, 1, 2 : These bits select one of the 6 transmission modes for the PMD Request Data

g

output port (TXD ).

D2

TM2

TM2 TM1 TM0

0

1

0

1

0

Active Transmit Mode (ATM): Normal transmission of incoming PHY Request data.

Idle Transmit Mode (ITM): Transmission of Idle symbol pairs (11111 11111).

Off Transmit Mode (OTM): Transmission of Quiet symbol pairs (00000 00000) and

deassertion of the PMD transmitter Enable pin (TXE).

Note: This is the default transmit mode after reset.

0

1

0

1

0

Reserved: Reserved for future use. Users are discouraged from using this transmit

mode. If selected, however, the transmitter will generate Quiet symbol pairs (00000

00000).

Master Transmit Mode (MTM): Transmission of Halt and Quiet symbol pairs (00100

00000).

1

0

1

0

1

Halt Transmit Mode (HTM): Transmission of Halt symbol pairs (00100 00100).

Quiet Transmit Mode (QTM): Transmission of Quiet symbol pairs (00000 00000).

Reserved: Reserved for future use. Users are discouraged from using this transmit

mode. If selected, however, the transmitter will generate Quiet symbol pairs

(00000 00000).

48

5.0 Registers (Continued)

Bit

Symbol

Description

k

l

D3, D4 IC0, IC1 Injection Control 0, 1 : These bits select one of the 4 injection modes. The injection modes have priority

over data from the Smoother, Repeat Filter, Encoder, and Transmit Modes.

a

IC0 is the only bit of the register that is automatically cleared by the PLAYER device after the One Shot

Injection is executed. The automatic clear of IC0 during the One Shot mode can be interpreted as a

acknowledgment that the One Shot has been completed.

IC1 IC0

0

No Injection: The normal transmission of incoming PHY Request data (i.e. symbols are not

injected).

0

1

One Shot: In one shot mode, the contents of Injection Symbol Register A (ISRA) and Injection

Symbol Register B (ISRB) are injected n symbol pairs after a JK, where n is the programmed

value of the Injection Count Register (IJCR). If IJCR is set to 0, the JK symbol pair is replaced by

a

ISRA and ISRB. Once the One Shot is executed, the PLAYER device automatically sets IC0 to

0, thereby returning to normal transmission of data.

1

0

1

Periodic: In Periodic mode, the contents of Injection Symbol Register A (ISRA) and Injection

Symbol Register B (ISRB) are injected every n-th symbol pair, where n is the programmed value

of the Injection Count Register (IJCR). If IJCR is set to 0, all data symbols are replaced with ISRA

and ISRB.

Note: The inserted symbol is not automatically aligned to a JK boundary.

Continuous: In Continuous mode, all data symbols are replaced with the contents of Injection

Symbol Register A (ISRA) and Injection Symbol Register B (ISRB).

D5

SE

SMOOTHER ENABLE:

0:

1:

Disables the Smoother.

Enables the Smoother.

When enabled, the Smoother can redistribute Idle symbol pairs which were added or deleted by the

local or upstream receivers.

Note: Once the counter has started, it will continue to count irrespective of the incoming symbols with the exception of a JK symbol pair.

D6

D7

PRDPE

RES

PHY REQUEST DATA PARITY ENABLE:

Ð

0:

1:

Disables PHY Request Data parity.

Ð

Enables PHY Request Data parity.

Ð

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset process. It may be set or cleared without any

a

effects to the functionality of the PLAYER device.

49

5.0 Registers (Continued)

5.6 INJECTION THRESHOLD REGISTER (IJTR)

k

l

The Injection Threshold Register, in conjunction with the Injection Control bits (IC 1:0 ) in the Current Transmit State Register

(CTSR), set the frequency at which the contents of the Injection Symbol Register A (ISRA) and Injection Symbol Register B

(ISRB) are inserted into the data stream. It contains the start value for the Injection Counter.

The Injection Threshold Register value is loaded into the Injection Counter when the counter reaches zero or during every

Control Bus Interface write-cycle of this register.

The Injection Counter is an 8-bit down-counter which decrements every 80 ns. It’s current value is read for CIJCR.

k

l

k

l

The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Control 1:0 bits (IC 1:0 ) of the

Current Transmit State Register (CTSR) are set to either 01 or 10). The Transmitter Block will replace a data symbol pair with

ISRA and ISRB when the counter reaches 0 and the Injection Mode is either One Shot or Periodic.

If the Injection Threshold Register is set to 0 during the One Shot mode, the JK will be replaced with ISRA and ISRB. If the

Injection Threshold Register is set to 0 during the Periodic mode, all data symbols are replaced with ISRA and ISRB.

E

e

The counter is initialized to 0 during the reset process (i.e. RST GND).

For further information, see the INJECTION CONTROL LOGIC section.

ACCESS RULES

ADDRESS

READ

WRITE

05h

Always

D7

D6

D5

D4

IJT4

D3

D2

D1

D0

IJT7

IJT6

IJT5

IJT3

IJT2

IJT1

IJT0

Bit

Symbol

Description

k

l

D0-D7 IJT0–IJT7 INJECTION THRESHOLD BIT 0-7 : Start value for the Injection Counter.

IJT0 is the Least Significant Bit (LSB).

50

5.0 Registers (Continued)

5.7 INJECTION SYMBOL REGISTER A (ISRA)

The Injection Symbol Register A, along with Injection Symbol Register B, contains the programmable value (already in 5B code)

that can be inserted to replace the data symbol pairs.

In One Shot mode, ISRA and ISRB are injected n bytes after a JK, where n is the programmed value of the Injection Threshold

Register. In the Periodic mode, ISRA and ISRB are injected every n-th symbol pair. In the Continuous mode, all data symbols are

replaced with ISRA and ISRB.

ACCESS RULES

ADDRESS

READ

WRITE

06h

Always

D7

D6

D5

D4

IJS4

D3

D2

D1

D0

RES

IJS3

IJS2

IJS1

IJS0

Bit

Symbol

Description

k

l

D0–D4 IJS0–IJS4 INJECTION SYMBOL BIT 0-4 : Symbol to be injected.

IJS0 is the Least Significant Bit (LSB) and goes out onto the media last.

D5–D7 RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using these bits. The reserved bits are set to 0 during the reset process. They may be set or cleared

a

without any effects to the functionality of the PLAYER device.

51

5.0 Registers (Continued)

5.8 INJECTION SYMBOL REGISTER B (ISRB)

The Injection Symbol Register B, along with Injection Symbol Register A, contains the programmable value (already in 5B code)

that will replace the data symbol pairs.

In One Shot mode, ISRA and ISRB are injected n bytes after a JK, where n is the programmed value of the Injection Threshold

Register. In the Periodic mode, ISRA and ISRB are injected every n-th symbol pair. In the Continuous mode, all data symbols are

replaced with ISRA and ISRB.

ACCESS RULES

ADDRESS

READ

WRITE

07h

Always

D7

D6

D5

D4

IJS9

D3

D2

D1

D0

RES

IJS8

IJS7

IJS6

IJS5

Bit

Symbol

Description

k

l

D0–D4 IJS0–IJS4 INJECTION SYMBOL BIT 0-4 : Symbol to be injected.

IJS0 is the Least Significant Bit (LSB) and goes out onto the media last.

D5–D7 RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using these bits. The reserved bits are set to 0 during the reset process. They may be set or cleared

a

without any effects to the functionality of the PLAYER device.

52

5.0 Registers (Continued)

5.9 CURRENT RECEIVE STATE REGISTER (CRSR)

The Current Receive State Register represents the current line state being detected by the Receiver Block. When the Receiver

Block recognizes a new Line State, the bits corresponding to the previous line state are cleared, and the bits corresponding to

the new line state are set.

E

e

During the reset process ( RST GND), the Receiver Block is forced to Line State Unknown (i.e. the Line State Unknown bit

(LSU) is set to 1).

a

Note: Users are discouraged from writing to this register. An attempt to write into this register will cause the PLAYER device to ignore the Control Bus write cycle

and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.

ACCESS RULES

ADDRESS

READ

WRITE

08h

Always

Write Reject

D7

D6

D5

RES

D4

D3

D2

D1

D0

RES

LSU

LS2

LS1

LS0

Bit

D0,

D1, D2 LS2

Symbol

Description

k

l

LS0, LS1, LINE STATE 0, 1, 2 : These bits represent the current Line State being detected by the Receiver Block.

Once the Receiver Block recognizes a new line state, the bits corresponding to the previous line state are

cleared, and the bits corresponding to the new line state are set.

LS2 LS1 LS0

0

1

0

1

0

Active Line State (ALS): Received a JK symbol pair (11000 10001), possibly followed

by data symbols.

Idle Line State (ILS): Received a minimum of two consecutive Idle symbol pairs

(11111 11111).

No Signal Detect (NSD): The Signal Detect (SD) has been deasserted, indicating that

a

the PLAYER device is not receiving data from the PMD receiver or that clock detect is

not being received from the Clock Recovery Module. SD is ignored during internal

loopback.

Note: NSD is the default value when the device is in Stop mode. However, while in Stop mode certain data

a

patterns entering the Receiver Block may cause the PLAYER to set LS0. Therefore, the user may see

either the NSD (010) or Reserved Value (011) during Stop mode.

0

1

0

1

0

Reserved: Reserved for future use.

Master Line State (MLS): Received a minimum of 8 consecutive Halt-Quiet symbol

pairs (00100 00000).

1

0

1

0

1

Halt Line State (HLS): Received a minimum of 8 consecutive Halt symbol pairs

(00100 00100).

Quiet Line State (QLS): Received a minimum of 8 consecutive Quiet symbol pairs

(00000 00000).

Noise Line State (NLS): Detected a minimum of 16 noise events. Refer to the Receiver

Block description for further information on noise events.

D3

LSU

LINE STATE UNKNOWN: The Receiver Block has not detected the minimum conditions to enter a known

k

l

line state. When the Line State Unknown bit is set, LS 2:0 represent the most recently known line state.

D4-D7 RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using these bits. The reserved bits are reset to 0 during the reset process. They may be set or cleared

a

without any effects to the functionality of the PLAYER device.

53

5.0 Registers (Continued)

5.10 RECEIVE CONDITION REGISTER A (RCRA)

The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block.

When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line

a

States are not cleared by the PLAYER device, thereby maintaining a record of the Line States detected.

The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register A is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register A (RCMRA) is

also set to 1.

ACCESS RULES

ADDRESS

READ

WRITE

09h

Always

Conditional

D7

D6

D5

NT

D4

D3

D2

D1

D0

LSUPI

LSC

NLS

MLS

HLS

QLS

NSD

Bit Symbol

Description

D0 NSD

NO SIGNAL DETECT: Indicates that the Signal Detect pin (TTLSD) has been deasserted and that the Clock

Recovery Module is not receiving data from the PMD receiver.

D1 QLS

D2 HLS

D3 MLS

D4 NLS

D5 NT

QUIET LINE STATE: Received a minimum of eight consecutive Quiet symbol pairs (00000 00000).

HALT LINE STATE: Received a minimum of eight consecutive Halt symbol pairs (00100 00100).

MASTER LINE STATE: Received a minimum of eight consecutive Halt-Quiet symbol pairs (00100 00000).

NOISE LINE STATE: Detected a minimum of sixteen noise events.

NOISE THRESHOLD: This bit is set to 1 when the internal Noise Counter reaches 0. It will remain set until a value

equal to or greater than one is loaded into the Noise Threshold Register or Noise Prescale Threshold Register.

E

e

During the reset process (i.e. RST GND), since the Noise Counter is initialized to 0, the Noise Threshold bit will

be set to 1.

D6 LSC

LINE STATE CHANGE: A line state change has been detected.

D7 LSUPI

LINE STATE UNKNOWN AND PHY INVALID: The Receiver Block has not detected the minimum conditions to

enter a known line state.

In addition, the most recently known line state was one of the following line states: No Signal Detect, Quiet Line

State, Halt Line State, Master Line State, or Noise Line State.

54

5.0 Registers (Continued)

5.11 RECEIVE CONDITION REGISTER B (RCRB)

The Receive Condition Register B maintains a historical record of the Lines States recognized by the Receiver Block.

When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line

States are not cleared, thereby maintaining a record of the Line States detected.

The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register B is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register B (RCMRB) is

also set to 1.

ACCESS RULES

ADDRESS

READ

WRITE

0Ah

Always

Conditional

D7

D6

D5

EBOU

D4

D3

D2

D1

D0

RES

SILS

CSE

LSUPV

ALS

ST

ILS

Bit Symbol

D0 ILS

Description

IDLE LINE STATE: Received a minimum of two consecutive Idle symbol pairs (11111 11111).

D1 ST

STATE THRESHOLD: This bit will be set to 1 when the internal State Counter reaches zero. It will remain set until

a value equal to or greater than one is loaded into the State Threshold Register or State Prescale Threshold

Register, and this register is cleared.

E

e

During the reset process (i.e. RST GND), since the State Counter is initialized to 0, the State Threshold bit is

set to 1.

D2 ALS

ACTIVE LINE STATE: Received a JK symbol pair (11000 10001), and possibly data symbols following.

D3 LSUPV

LINE STATE UNKNOWN AND PHY VALID: The Receiver Block has not detected the minimum conditions to

enter a known line state.

In addition, the most recently known line state was either Active Line State or Idle Line State.

D4 CSE

CONNECTION SERVICE EVENT/CASCADE SYNCHRONIZATION ERROR:

When one or more bits in the CMT Condition Register (CMTCR) are set and the corresponding bit(s) in the CMT

Condition Mask Register (CMTCMR) are set, the Connection service event bit will be set to a 1.

When a synchronization error occurs, the Cascade Synchronization Error bit is set to 1. A synchronization error

occurs if the Cascade Start signal (CS) is not asserted within approximately 80 ns of Cascade Ready (CR) release.

Note: Cascade mode and the CMT features can not be used at the same time.

Note: Cascade mode is only supported on the DP83257 device.

D5 EBOU

ELASTICITY BUFFER UNDERFLOW / OVERFLOW: The Elasticity Buffer has either overflowed or underflowed.

The Elasticity Buffer will automatically recover if the condition which caused the error is only transient, but the

event bit will remain set until cleared by software.

D6 SILS

D7 RES

SUPER IDLE LINE STATE: Received a minimum of eight Idle symbol pairs (11111 11111).

RESERVED: Reserved for future use.

Note: Users are discouraged from using these bits. The reserved bits are reset to 0 during the reset process. They may be set or cleared without

a

any effects to the functionality of the PLAYER device

55

5.0 Registers (Continued)

5.12 RECEIVE CONDITION MASK REGISTER A (RCMRA)

The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt.

The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register A (RCRA) is set to 1 and the corresponding mask bit(s) in this register is also set to 1.

Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.

ACCESS RULES

ADDRESS

READ

WRITE

0Bh

Always

D7

D6

D5

D4

D3

D2

D1

D0

LSUPIM

LSCM

NTM

NLSM

MLSM

HLSM

QLSM

NSDM

Bit Symbol

Description

D0 NSDM

NO SIGNAL DETECT MASK: The mask bit for the No Signal Detect bit (NSD) of the Receive Condition Register A

(RCRA).

D1 QLSM

D2 HLSM

D3 MLSM

D4 NLSM

D5 NTM

QUIET LINE STATE MASK: The mask bit for the Quiet Line State bit (QLS) of the Receive Condition Register A

(RCRA).

HALT LINE STATE MASK: The mask bit for the Halt Line State bit (HLS) of the Receive Condition Register A

(RCRA).

MASTER LINE STATE MASK: The mask bit for the Master Line State bit (MLS) of the Receive Condition Register

A (RCRA).

NOISE LINE STATE MASK: The mask bit for the Noise Line State bit (NLS) of the Receive Condition Register A

(RCRA).

NOISE THRESHOLD MASK: The mask bit for the Noise Threshold bit (NT) of the Receive Condition Register A

(RCRA).

D6 LSCM

LINE STATE CHANGE MASK: The mask bit for the Line State Change bit (LSC) of the Receive Condition

Register A (RCRA).

D7 LSUPIM LINE STATE UNKNOWN AND PHY INVALID MASK: The mask bit for the Line State Unknown and PHY Invalid

bit (LSUPI) of the Receive Condition Register A (RCRA).

56

5.0 Registers (Continued)

5.13 RECEIVE CONDITION MASK REGISTER B (RCMRB)

The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt.

The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register B (RCRA) is set to 1 and the corresponding mask bits in this register is also set to 1.

Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.

ACCESS RULES

ADDRESS

READ

WRITE

0Ch

Always

D7

D6

D5

D4

CSEM

D3

D2

D1

D0

RESM

SILSM

EBOUM

LSUPVM

ALSM

STM

ILSM

Bit

Symbol

Description

D0 ILSM

D1 STM

D2 ALSM

IDLE LINE STATE MASK: The mask bit for the Idle Line State bit (ILS) of the Receive Condition Register B

(RCRB).

STATE THRESHOLD MASK: The mask bit for the State Threshold bit (ST) of the Receive Condition Register B

(RCRB).

ACTIVE LINE STATE MASK: The mask bit for the Active Line State bit (ALS) of the Receive Condition Register

B (RCRB).

D3 LSUPVM LINE STATE UNKNOWN AND PHY VALID MASK: The mask bit for the Line State Unknown and PHY Valid bit

(LSUPV) of the Receive Condition Register B (RCRB).

D4 CSEM

CASCADE SYNCHRONIZATION ERROR MASK/CONNECTION SERVICE EVENT MASK:

The mask bit for the Cascade Synchronization Error/Connection service event bit (CSE) of the Receive Condition

Register B (RCRB).

D5 EBOUM

D6 SILSM

D7 RESM

ELASTICITY BUFFER OVERFLOW/UNDERFLOW MASK: The mask bit for the Elasticity Buffer Overflow/

Underflow bit (EBOU) of the Receive Condition Register B (RCRB).

SUPER IDLE LINE STATE MASK: The mask bit for the Super Idle Line State bit (SILS) of the Receive Condition

Register B (RCRB).

RESERVED MASK: The mask bit for the Reserved bit (RES) of the Receive Condition Register B (RCRB).

57

5.0 Registers (Continued)

5.14 NOISE THRESHOLD REGISTER (NTR)

The Noise Threshold Register contains the start value for the Noise Timer. This threshold register is used in conjunction with the

Noise Prescale Threshold register for setting the maximum allowable time between entry to ILS, HLS, MLS, ALS, or NSD line

states. The Noise timer is used to implement the TNE timing requirement of PCM. The Noise timer decrements by one for every

a

80 x (NPTR 1) ns in case of Noise events. As a result, the internal noise counter takes the following amount of time to reach

zero:

a

((NPTR 1) x NTR

a

NPTR) x 80 ns

The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of

the following conditions is true:

1. Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active

Line State, or Line State Unknown.

or

2. The current Line State is either Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect.

or

3. The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.

In addition, the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale

Counter reaches zero.

The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a

Line State change occurs and the new line state is either Noise Line State, Active Line State, or Line State Unknown.

When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition

Register A will be set.

The recommended default value for the NTR register is 40h and for the NPTR register is F9h which corresponds to 1.3 ms as

specified in the ANSI standard.

ACCESS RULES

ADDRESS

READ

WRITE

0Dh

Always

D7

D6

D5

D4

NT4

D3

D2

D1

D0

RES

NT6

NT5

NT3

NT2

NT1

NT0

Bit

Symbol

Description

k

l

D0-D6 NT0-NT6 NOISE THRESHOLD BIT 0-6 : Start value for the Noise Counter.

NT0 is the Least Significant Bit (LSB).

D7

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. Write data is ignored since the reserved bit is permanently set to 0.

58

5.0 Registers (Continued)

5.15 NOISE PRESCALE THRESHOLD REGISTER (NPTR)

The Noise Prescale Threshold Register contains the start value for the Noise Prescale Timer. This threshold register is used in

conjunction with the Noise Threshold register for setting the maximum allowable time between entry to ILS, HLS, MLS, ALS, or

NSD. The Noise timer is used to implement the TNE timing requirement of PCM. The Noise Prescale threshold controls how

often the Noise timer is decremented. When the Noise Prescale Timer reaches zero, it reloads the count with the contents of the

Noise Prescale Threshold Register and also causes the Noise Timer to decrement.

The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of

the following conditions is true:

1. Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active

Line State, or Line State Unknown.

or

2. The Current Line State is either Halt Line State. Idle Line State, Master Line State, Quiet Line State, or No Signal Detect

or

3. The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.

In addition, the value of the Noise Prescale Threshold Register is loaded into the Noise Prescale Counter if the Noise Prescale

Counter reaches zero.

The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a

Line State change occurs and the new line state is either Noise Line State, Active Line State, or Line State Unknown.

When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition

Register A will be set.

See the NTR register description for default value recommendations.

ACCESS RULES

ADDRESS

READ

WRITE

0Eh

Always

D7

D6

D5

D4

NPT4

D3

D2

D1

D0

NPT7

NPT6

NPT5

NPT3

NPT2

NPT1

NPT0

Bit

Symbol

Description

k

l

D0-D7 NPT0-NPT7 NOISE PRESCALE THRESHOLD BIT 0-7 : Start value for the Noise Prescale Timer.

NPT0 is the Least Significant Bit (LSB).

59

5.0 Registers (Continued)

5.16 CURRENT NOISE COUNT REGISTER (CNCR)

The Current Noise Count Register takes a snap-shot of the Noise Timer during every Control Bus Interface read cycle of this

register.

During a Control Bus Interface write cycle, the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register

(ICR) will be set to 1 and will ignore a write cycle.

ACCESS RULES

ADDRESS

READ

WRITE

0Fh

Always

Write Reject

D7

D6

D5

CNC5

D4

D3

D2

D1

D0

NCLSCD

CNC6

CNC4

CNC3

CNC2

CNC1

CNC0

Bit

Symbol

Description

k

l

D0–D6 CNC0–CNC6 CURRENT NOISE COUNT BIT 0–6 : Snapshot of the Noise Counter.

D7

NCLSCD

NOISE COUNTER LINE STATE CHANGE DETECTION

60

5.0 Registers (Continued)

5.17 CURRENT NOISE PRESCALE COUNT REGISTER (CNPCR)

The Current Noise Prescale Count Register takes a snap-shot of the Noise Prescale Timer during every Control Bus Interface

read cycle of this register.

During a Control Bus Interface write cycle, the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register

(ICR) will be set to 1 and will ignore a write cycle.

ACCESS RULES

ADDRESS

READ

WRITE

10h

Always

Write Reject

D7

D6

D5

CNPC5

D4

D3

D2

D1

D0

CNPC7

CNPC6

CNPC4

CNPC3

CNPC2

CNPC1

CNPC0

Bit

Symbol

Description

k

l

D0–D7 CNPC0–7 CURRENT NOISE PRESCALE COUNT BIT 0–7 : Snapshot of the Noise Prescale Timer.

61

5.0 Registers (Continued)

5.18 STATE THRESHOLD REGISTER (STR)

The State Threshold Register contains the start value for the State Timer. This timer is used in conjunction with the State

Prescale Timer to count the Line State duration. The State Timer will decrement every 80 ns if the State Prescale Timer is zero

and the current Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect. The State

Timer takes

a

SPTR) x 80 ns

((SPTR 1) x STR

to reach zero during a continuous line state condition.

The threshold values for the State Timer and State Prescale Timer are simultaneously loaded into both counters if one of the

following conditions is true:

1. Both the State Timer and State Prescale Timer reach zero and the current Line State is Halt Line State, Idle Line State,

Master Line State, Quiet Line State, or No Signal Detect.

or

2. A line state change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or

No Signal Detect.

or

3. The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.

In addition, the value of the State Prescale Threshold Register is loaded into the State Prescale Counter if the State Prescale

Timer reaches zero.

The State Timer and State Prescale Timer will reset by reloading the threshold values, if a Line State change occurs and the

new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect. On detection of ALS,

NLS, or LSU the timer will not decrement.

ACCESS RULES

ADDRESS

READ

WRITE

11h

Always

D7

D6

D5

D4

ST4

D3

D2

D1

D0

RES

ST6

ST5

ST3

ST2

ST1

ST0

Bit

Symbol

Description

k

l

D0-D6 ST0-ST6 STATE THRESHOLD BIT 0-6 : Start value for the State Timer.

ST0 is the Least Significant Bit (LSB).

D7

RES

RESERVED: Reserved for future use.

Note: Users are discouraged from using this bit. Write data is ignored since the reserved bit is permanently set to 0.

62

5.0 Registers (Continued)

5.19 STATE PRESCALE THRESHOLD REGISTER (SPTR)

The State Prescale Threshold Register contains the start value for the State Prescale Timer. The State Prescale Timer is a down

counter. It is used in conjunction with the State Timer to count the Line State duration.

The threshold values for the State Timer and State Prescale Timer are simultaneously loaded into both timers if one of the

following conditions is true:

1. Both the State Timer and State Prescale Timer reach zero and the current Line State is Halt Line State, Idle Line State,

Master Line State, Quiet Line State, or No Signal Detect.

or

2. A Line State change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or

No Signal Detect.

or

3. The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.

The State Prescale Timer will decrement every 80 ns if the current Line State is Halt Line State, Idle Line State, Master Line

State, Quiet Line State, or No Signal Detect.

ACCESS RULES

ADDRESS

READ

WRITE

12h

Always

D7

D6

D5

D4

SPT4

D3

D2

D1

D0

SPT7

SPT6

SPT5

SPT3

SPT2

SPT1

SPT0

Bit

Symbol

Description

k

l

D0–D7 SPT0–SPT7 STATE PRESCALE THRESHOLD BIT 0–7 : Start value for the State Prescale Timer.

SPT0 is the Least Significant Bit (LSB).

63

5.0 Registers (Continued)

5.20 CURRENT STATE COUNT REGISTER (CSCR)

The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read cycle of this

register.

During a Control Bus Interface write cycle, the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register

(ICR) will be set to 1 and will ignore a write cycle.

ACCESS RULES

ADDRESS

READ

WRITE

13h

Always

Write Reject

D7

D6

D5

CSC5

D4

D3

D2

D1

D0

SCLSCD

CSC6

CSC4

CSC3

CSC2

CSC1

CSC0

Bit

Symbol

Description

k

l

D0–D6 CSC0–CSC6 CURRENT STATE COUNT BIT 0–6 : Snapshot of the State Counter.

D7

SCLSCD

STATE COUNTER LINE STATE CHANGE DETECTION

64

5.0 Registers (Continued)

5.21 CURRENT STATE PRESCALE COUNT REGISTER (CSPCR)

The Current State Prescale Count Register takes a snap-shot of the State Prescale Counter during every Control Bus Interface

read cycle of this register.

During a Control Bus Interface write cycle, the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register

(ICR) will be set to 1 and will ignore a write cycle.

ACCESS RULES

ADDRESS

READ

WRITE

14h

Always

Write Reject

D7

D6

D5

CSPC5

D4

D3

D2

D1

D0

CSPC7

CSPC6

CSPC4

CSPC3

CSPC2

CSPC1

CSPC0

Bit

Symbol

Description

k

l

D0–D7 CSPC0–7 CURRENT STATE PRESCALE COUNT 0–7 : Snapshot of the State Prescale Counter.

65

5.0 Registers (Continued)

5.22 LINK ERROR THRESHOLD REGISTER (LETR)

The Link Error Threshold Register contains the start value for the Link Error Monitor Counter. It is an 8-bit down-counter which

decrements if link errors are detected.

When the Counter reaches 0, the Link Error Monitor Threshold Register value is loaded into the Link Error Monitor Counter and

the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition Register (ICR) is set to one.

The Link Error Monitor Threshold Register value is also loaded into the Link Error Monitor Counter during every Control Bus

Interface write cycle of LETR.

E

e

The counter is initialized to 0 during the reset process (i.e. RST GND).

ACCESS RULES

ADDRESS

READ

WRITE

15h

Always

D7

D6

D5

D4

LET4

D3

D2

D1

D0

LET7

LET6

LET5

LET3

LET2

LET1

LET0

Bit

Symbol

Description

k

l

D0–D7 LET0–LET7 LINK ERROR THRESHOLD BIT 0–7 : Start value for the Link Error Monitor Counter.

LET0 is the Least Significant Bit (LSB).

66

5.0 Registers (Continued)

5.23 CURRENT LINK ERROR COUNT REGISTER (CLECR)

The Current Link Error Count Register takes a snap-shot of the Link Error Monitor Counter during every Control Bus Interface

read cycle of this register.

During a Control Bus Interface write cycle, the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register

(ICR) will be set to 1 and will ignore a write cycle.

ACCESS RULES

ADDRESS

READ

WRITE

16h

Always

Write Reject

D7

D6

D5

LEC5

D4

D3

D2

D1

D0

LEC7

LEC6

LEC4

LEC3

LEC2

LEC1

LEC0

Bit

Symbol

Description

k

l

D0–D7 LEC0–LEC7 LINK ERROR COUNT BIT 0–7 : Snapshot of the Link Error Monitor Counter.

67

5.0 Registers (Continued)

5.24 USER DEFINABLE REGISTER (UDR)

a

The User Definable Register is used to monitor and control events which are external to the PLAYER device.

The value of the Sense Bits reflect the asserted/deasserted state of their corresponding Sense pins. On the other hand, the

Enable bits assert/deassert the Enable pins.

Note: SB2 and EB2 are only effective for the DP83257.

ACCESS RULES

ADDRESS

READ

WRITE

17h

Always

D7

D6

D5

D4

SB2

D3

D2

D1

D0

RES

EB2

RES

EB1

EB0

SB1

SB0

Bit Symbol

Description

e

D0 SB0

SENSE BIT 0: This bit is set to 1 if the Sense Pin 0 (SP0) is asserted (i.e. SP0

V ) for a minimum amount of

CC

time. Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control Bus Interface, even

if the signal is deasserted. This ensures that the Control Bus Interface will record the source of events which can

cause interrupts in a traceable manner.

e

D1 SB1

D2 EB0

SENSE BIT 1: This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (i.e. SP1

V ) for a minimum amount of

CC

time. Once the asserted signal is latched, Sense Bit 1 can only be cleared through the Control Bus Interface, even

if the signal is deasserted. This ensures that the Control Bus Interface will record the source of events which can

cause interrupts in a traceable manner.

ENABLE BIT 0: The Enable Bit 0 allows control of external logic through the Control Bus Interface. The User

Definable Enable Pin 0 (EP0) is asserted/deasserted by this bit.

e

EP0 is deasserted (i.e. EP0 GND).

0:

1:

e

EP0 is asserted (i.e. EP0

V

CC

).

D3 EB1

ENABLE BIT 1: This bit allows control of external logic through the Control Bus Interface. The User Definable

Enable Pin 0 (EP0) is asserted/deasserted by this bit.

e

EP1 is deasserted (i.e. EP1 GND).

0:

1:

e

EP1 is asserted (i.e. EP1

V

CC

).

e

D4 SB2

SENSE BIT 2: This bit is set to 1 if the Sense Pin 2 (SP2) is asserted (i.e. SP2

V ) for a minimum amount of

CC

time. Once the asserted signal is latched, Sense Bit 2 can only be cleared through the Control Bus Interface, even

if the signal is deasserted. This ensures that the Control Bus Interface will record the source of events which can

cause interrupts in a traceable manner.

Note: SB2 and EB2 are only effective for the DP83257.

D5 RES

D6 EB2

RESERVED: Reserved for future use. The reserved bit is set to 0 during the initialization process

E

e

(i.e. RST GND).

a

Note: Users are discouraged from using this bit. It may be set or cleared without any effects to the functionality of the PLAYER device.

ENABLE BIT2: The Enable Bit 2 allows control of external logic through the Control Bus Interface. The User

Definable Enable Pin 2 (EP2) is asserted/deasserted by this bit.

Note: SB2 and EB2 are only effective for the DP83257.

e

EP2 is deasserted (i.e. EP2 GND).

0:

1:

e

EP2 is asserted (i.e. EP2

V

CC

).

D7 RES

RESERVED: Reserved for future use. The reserved bit is set to 0 during the initialization process

E

e

(i.e. RST GND).

a

Note: Users are discouraged from using this bit. It may be set or cleared without any effects to the functionality of the PLAYER device.

68

5.0 Registers (Continued)

5.25 DEVICE ID REGISTER (IDR)

The Device ID Register contains the binary equivalent of the revision number for this device. It can be used to ensure proper

software and hardware versions are matched.

During a Control Bus Interface write cycle, the Control Bus Write Command Register bit (CCR) of the Interrupt Condition

Register (ICR) will be set to 1, and will ignore write cycle.

REVISION TABLE

IDR

DEVICE DESCRIPTION

(hex)

a

PLAYER Revision A

a

PLAYER Revision B

10

11

ACCESS RULES

ADDRESS

READ

WRITE

18h

Always

Write Reject

D7

D6

D5

D4

D3

D2

D1

D0

DID7

DID6

DID5

DID4

DID3

DID2

DID1

DID0

Bit

Symbol

Description

k

l

D0–D3 DID0–DID3 DEVICE ID BIT 0-3 : Circuit enhancement revision number. Bit 3 is the MSB. The initial revision of the

a

PLAYER is equal to 0 and enhancements will increment this number.

k

l

D4–D7 DID4–DID7 DEVICE ID BIT 4-7 : Architecture level of the PHY device. Bit 7 is the MSB. The original PLAYER

device was equal to 0 and the PLAYER is equal to 1. This number will only be incremented after a

a

significant architectural change.

69

5.0 Registers (Continued)

5.26 CURRENT INJECTION COUNT REGISTER (CIJCR)

The Current Injection Count Register takes a snap-shot of the Injection Counter during every Control Bus Interface read cycle of

this register.

During a Control Bus Interface write cycle, the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register

(ICR) will be set to 1 and will ignore a write cycle.

The Injection Counter is an 8-bit down-counter which decrements every 80 ns.

k

l

k

l

The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Control 1:0 bits (IC 1:0 ) of the

Current Transmit State Register (CTSR) are set to either 01 or 10).

The Injection Threshold Register (IJTR) value is loaded into the Injection Counter when the counter reaches zero and during

every Control Bus Interface write cycle of IJTR.

E

e

The counter is initialized to 0 during the reset process (i.e. RST GND).

ACCESS RULES

ADDRESS

READ

WRITE

19h

Always

Write Reject

D7

D6

D5

IJC5

D4

D3

D2

D1

D0

IJC7

IJC6

IJC4

IJC3

IJC2

IJC1

IJC0

Bit

Symbol

Description

k

l

D0–D7 IJC0–IJC7 INJECTION COUNT BIT 0-7 : Current value of the Injection Counter.

IJC0 is the Least Significant Bit (LSB).

70

5.0 Registers (Continued)

5.27 INTERRUPT CONDITION COMPARISON REGISTER (ICCR)

a

The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER

device before it can be written to by the Control Bus Interface.

The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison

e

Register (i.e. ICCR ICR) during a Control Bus Interface read-cycle of ICR.

a

During a Control Bus Interface write cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the

value of the corresponding bit in the interrupt Condition Comparison Register.

ACCESS RULES

ADDRESS

READ

WRITE

1Ah

Always

D7

D6

D5

D4

LEMTC

D3

D2

D1

D0

UDIC

RCBC

RCAC

CWIC

CCRC

CPEC

DPEC

Bit Symbol

Description

D0 DPEC

PHY REQUEST DATA PARITY ERROR COMPARISON: The comparison bit for the PHY Request Data Parity

Ð Ð

Error bit (DPE) of the Interrupt Condition Register (ICR).

D1 CPEC

D2 CCRC

D3 CWIC

D4 LEMTC

D5 RCAC

D6 RCBC

D7 UDIC

CONTROL BUS DATA PARITY ERROR COMPARISON: The comparison bit for the Control Bus Data Parity Error

bit (CPE) of the Interrupt Condition Register (ICR).

CONTROL BUS WRITE COMMAND REJECT COMPARISON: The comparison bit for the Control Bus Write

Command Reject bit (CCR) of the Interrupt Condition Register (ICR).

CONDITIONAL WRITE INHIBIT COMPARISON: The comparison bit for the Conditional Write Inhibit bit (CWI) of

the Interrupt Condition Register (ICR).

LINK ERROR MONITOR THRESHOLD COMPARISON: The comparison bit for the Link Error Monitor Threshold

bit (LEMT) of the Interrupt Condition Register (ICR).

RECEIVE CONDITION A COMPARISON: The comparison bit for the Receive Condition A bit (RCA) of the

Interrupt Condition Register (ICR).

RECEIVE CONDITION B COMPARISON: The comparison bit for the Receive Condition B bit (RCB) of the

Interrupt Condition Register (ICR).

USER DEFINABLE INTERRUPT COMPARISON: The comparison bit for the User Definable Interrupt bit (UDIC) of

the Interrupt Condition Register (ICR).

71

5.0 Registers (Continued)

5.28 CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR)

a

The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER

device before it can be written to by the Control Bus Interface.

The current state of the Current Transmit State Register (CTSR) is automatically written into the Current Transmit State

e

Comparison Register A (i.e. CTSCR CTSR) during a Control Bus Interface read cycle of CTSR.

a

During a Control Bus Interface write cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within the CTSR when the value of a bit in the CTSR

differs from the value of the corresponding bit in the Current Transmit State Comparison Register.

ACCESS RULES

ADDRESS

READ

WRITE

1Bh

Always

D7

D6

D5

SEC

D4

D3

D2

D1

D0

RESC

PRDPEC

IC1C

IC0C

TM2C

TM1C

TM0C

Bit

Symbol

Description

k

Current Transmit State Register (CTSR).

l

k

l

D0 TM0C

D1 TM1C

D2 TM2C

D3 IC0C

D4 IC1C

D5 SEC

TRANSMIT MODE

0

COMPARISON: The comparison bit for the Transmit Mode

0

1

2

bit (TM0) of the

bit (TM1) of the

bit (TM2) of the

k

Current Transmit State Register (CTSR).

l

COMPARISON: The comparison bit for the Transmit Mode

TRANSMIT MODE

1

k

Current Transmit State Register (CTSR).

l

COMPARISON: The comparison bit for the Transmit Mode

TRANSMIT MODE

2

k

Current Transmit State Register (CTSR).

l

k

l

INJECTION CONTROL

0

COMPARISON: The comparison bit for the Injection Control

0

1

bit (IC0) of the

bit (IC1) of the

k

Current Transmit State Register (CTSR).

l

COMPARISON: The comparison bit for the Injection Control

INJECTION CONTROL

1

SMOOTHER ENABLE COMPARISON: The comparison bit for the Smoother Enable bit (SE) of the Current

Transmit State Register (CTSR).

D6 PRDPEC PHY REQUEST DATA PARITY ENABLE COMPARISON: The comparison bit for the PHY Request Data

Ð

Parity Enable bit (PRDPE) of the Current Transmit State Register (CTSR).

D7 RESC

RESERVED COMPARISON: The comparison bit for the Reserved bit (RES) of the Current Transmit State

Register (CTSR).

72

5.0 Registers (Continued)

5.29 RECEIVE CONDITION COMPARISON REGISTER A (RCCRA)

a

The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER

device before it can be written to by the Control Bus Interface.

e

The current state of RCRA is automatically written into the Receive Condition Comparison Register A (i.e. RCCRA RCRA)

during a Control Bus Interface read cycle of RCRA.

a

During a Control Bus Interface write cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRA when the value of a bit in RCRA differs

from the value of the corresponding bit in the Receive Condition Comparison Register A.

ACCESS RULES

ADDRESS

READ

WRITE

1Ch

Always

D7

D6

D5

D4

D3

D2

D1

D0

LSUPIC

LSCC

NTC

NLSC

MLSC

HLSC

QLSC

NSDC

Bit Symbol

Description

D0 NSDC

NO SIGNAL DETECT COMPARISON: The comparison bit for the No Signal Detect bit (NSD) of the Receive

Condition Register A (RCRA).

D1 QLSC

D2 HLSC

D3 MLSC

D4 NLSC

D5 NTC

QUIET LINE STATE COMPARISON: The comparison bit for the Quiet Line State bit (QLS) of the Receive

Condition Register A (RCRA).

HALT LINE STATE COMPARISON: The comparison bit for the Halt Line State bit (HLS) of the Receive Condition

Register A (RCRA).

MASTER LINE STATE COMPARISON: The comparison bit for the Master Line State bit (MLS) of the Receive

Condition Register A (RCRA).

NOISE LINE STATE COMPARISON: The comparison bit for the Noise Line State bit (NLS) of the Receive

Condition Register A (RCRA).

NOISE THRESHOLD COMPARISON: The comparison bit for the Noise Threshold bit (NT) of the Receive

Condition Register A (RCRA).

D6 LSCC

LINE STATE CHANGE COMPARISON: The comparison bit for the Line State Change bit (LSC) of the Receive

Condition Register A (RCRA).

D7 LSUPIC LINE STATE UNKNOWN AND PHY INVALID COMPARISON: The comparison bit for the Line State Unknown

and PHY Invalid bit (LSUPI) of the Receive Condition Register A (RCRA).

73

5.0 Registers (Continued)

5.30 RECEIVE CONDITION COMPARISION REGISTER B (RCCRB)

a

The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER

device before it can be written to by the Control Bus Interface.

e

The current state of RCRB is automatically written into the Receive Condition Comparison Register B (i.e. RCCRB RCRB)

during a Control Bus Interface read cycle RCRB.

a

During a Control Bus Interface write cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs

from the value of the corresponding bit in the Receive Condition Comparison Register B.

ACCESS RULES

ADDRESS

READ

WRITE

1Dh

Always

D7

D6

D5

D4

CSEC

D3

D2

D1

D0

RESC

SILSC

EBOUC

LSUPVC

ALSC

STC

ILSC

Bit Symbol

Description

D0 ILSC

IDLE LINE STATE COMPARISON: The comparison bit for the Idle Line State bit (ILS) of the Receive Condition

Register B (RCRB).

D1 STC

STATE THRESHOLD COMPARISON: The comparison bit for the State Threshold bit (ST) of the Receive

Condition Register B (RCRB).

D2 ALSC

ACTIVE LINE STATE COMPARISON: The comparison bit for the Active Line State bit (ALS) of the Receive

Condition Register B (RCRB).

D3 LSUPVC LINE STATE UNKNOWN AND PHY VALID COMPARISON: The comparison bit for the Line State Unknown and

PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB).

D4 CSEC

CONNECTION SERVICE EVENT COMPARISON / CASCADE SYNCHRONIZATION ERROR: The comparison

bit for the Cascade Synchronization Error/Connection Service Event bit (CSE) of the Receive Condition Register

B (RCRB).

D5 EBOUC

D6 SILSC

D7 RESC

ELASTICITY BUFFER OVERFLOW / UNDERFLOW COMPARISON: The comparison bit for the Elasticity Buffer

Overflow/Underflow bit (EBOU) of the Receive Condition Register B (RCRB).

SUPER IDLE LINE STATE COMPARISON: The comparison bit for the Super Idle Line State bit (SILS) of the

Receive Condition Register B (RCRB).

RESERVED COMPARISON: The comparison bit for the Reserved bit (RES) of the Receive Condition Register B

(RCRB).

74

5.0 Registers (Continued)

5.31 MODE REGISTER 2 (MODE2)

a

The Mode Register 2 (MODE2) is used to configure the PLAYER device.

The register is used to software reset the chip, setup data parity, and enable scrubbing functions.

Note: This register can not be written to during reset.

ACCESS RULES

ADDRESS

READ

WRITE

1Eh

Always

Conditional

D7

D6

D5

CLKSEL

D4

D3

D2

D1

D0

ESTC

RES

CBPE

PHYRST

Bit

D0

Symbol

Description

PHYRST PLAYER RESET: This bit can be used as a master software reset of the PLAYER function within the

a

PLAYER device. The clock distribution and recovery sections of the chip are not affected by this reset.

a

The PLAYER automatically clears this bit 32 byte time after its assertion to indicate that the reset action

has been completed.

a

This bit can be set through a C-Bus write, but can only be cleared by the PLAYER

.

D1

CBPE

C-Bus Parity Enable: This bit disables or enables parity checking on C-Bus data. When this bit is set to 0, no

parity checking is done. When the bit is set to 1, parity checking is enabled during a C-Bus write cycle. Should

a mismatch occur, the C-Bus Data Parity Error (ICR.CPE) bit will be set and the corresponding C-Bus access

is discarded.

C-Bus data parity is always generated during a C-Bus read cycle.

D2–D4 RES

RESERVED: Reserved for future use.

D5

CLKSEL CLOCK SELECT: This bit controls the frequency of the CLK16 output. It resets to 0 which sets the CLK16

output to a 15.625 MHz frequency. When set to 1 a 31.25 MHz frequency is generated.

Note: When the value of this bit is changed, no glitches appear on the CLK16 output due to the frequency change.

D6

D7

RES

RESERVED: Reserved for future use.

ESTC

ENABLE SCRUBBING on TRIGGER CONDITIONS: When ESTC is set to 1 and a Trigger Condition occurs

(as set in the TDR register), the Trigger Transition Configuration Register (TTCR) is loaded into the

Configuration Register (CR) and scrubbing is started on all indicate ports that have changed.

Scrubbing is accomplished by sending out 2 Phy Invalid symbols followed by ‘‘scrub’’symbol pairs for a time

Ð

defined by the Scrub Timer Threshold register.

75

5.0 Registers (Continued)

5.32 CMT CONDITION COMPARISON REGISTER (CMTCCR)

a

The CMT Condition Comparison Register (CMTCR) ensures that the Control Bus must first read a bit modified by the PLAYER

device before it can be written to by the Control Bus Interface.

The current state of the CMT Condition Register (CMTCR) is automatically written into the CMT Condition Comparison Register

e

(CMTCR) (i.e. CMTCCR

CMTCR) during a Control Bus Interface read-cycle of CMTCR.

a

During a Control Bus Interface write cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Control Register (ICR) to 1 and disallow the setting or clearing of a bit within the CMTCR when the value of a bit in the CMTCR

differs from the value of the corresponding bit in the CMT Condition Comparison Register.

ACCESS RULES

ADDRESS

READ

WRITE

1Fh

Always

D7

D6

D5

D4

RES

D3

D2

D1

D0

TCOC

STEC

RES

Bit

Symbol

Description

D0-D5 RES

RESERVED: Reserved for future use.

D6

D7

STEC

TCOC

SCRUB TIMER EXPIRED COMPARISON: The comparison bit for the Scrub Timer Expire bit (STE) of the CMT

Condition Register (CMTCR).

TRIGGER CONDITION OCCURRED COMPARISON: The comparison bit for the Trigger Condition Occurred

(TCO) bit of the CMT Condition Register (CMTCR).

76

5.0 Registers (Continued)

5.33 CMT CONDITION REGISTER (CMTCR)

The CMT Condition Register maintains a history of all CMT events and actions performed. The corresponding CMT Condition

Mask Register (CMTCMR) can be used to generate an interrupt. When the bits in both the CMTCMR and CMTCR are set, the

Receive Condition Register B’s Connection Service Event (RCRB.CSE) bit will be set.

ACCESS RULES

ADDRESS

READ

WRITE

20h

Always

Conditional

D7

D6

D5

RES

D4

D3

D2

D1

D0

TCO

STE

RES

Bit

Symbol

Description

D0-D5 RES

RESERVED: Reserved for future use.

D6

STE

SCRUB TIMER EXPIRED: This bit is set to 1 when the Scrub Timer expires.

Note: When STE is set, the Configuration Register (CR) is protected.

D7

TCO

TRIGGER CONDITION OCCURRED: This bit is set to 1 when a trigger condition is met. When a trigger occurs,

the values in the Trigger Transmit Mode (TDR.TTM2-0) are loaded into the Current Transmit Mode Register

(CTSR.TM2-0).

Note: When TCO is set, the Current Transmit State Register (CTSR) is protected.

77

5.0 Registers (Continued)

5.34 CMT CONDITION MASK REGISTER (CMTCMR)

This is the mask register for the CMT Condition Register (CMTCR). When the bits in both the CMTCMR and CMTCR are set, the

Receive Condition Register B’s Connection Service Event (RCRB.CSE) bit will be set.

ACCESS RULES

ADDRESS

READ

WRITE

21h

Always

D7

D6

D5

D4

RES

D3

D2

D1

D0

TCOM

STEM

RES

Bit

Symbol

Description

D0-D5 RES

RESERVED: Reserved for future use.

D6

D7

STEM

SCRUB TIMER EXPIRED MASK: The mask bit for the Scrub Timer Expired (STE) bit of the CMT Condition

Register (CMTCR).

TCOM

TRIGGER CONDITION OCCURRED MASK: The mask bit for the Trigger Condition Occurred (TCO) bit of the

CMT Condition Register (CMTCR).

78

5.0 Registers (Continued)

5.35 RESERVED REGISTERS 22H–23H (RR22H–RR23H)

This register is reserved for future use.

DO NOT ACCESS THIS REGISTER

ACCESS RULES

ADDRESS

READ

WRITE

22h–23h

Always

DO NOT WRITE

79

5.0 Registers (Continued)

5.36 SCRUB TIMER THRESHOLD REGISTER (STTR)

E

This is the threshold value of the internal scrub timer. It has a resolution of 40.96 ms and a maximum value of 10 ms. When

the scrub timer reaches zero, the Scrub Timer Expired (CMTCR.STE) bit is set.

e

Scrubbing is initiated when MODE2.ESTC 1 and a trigger condition occurs.

Writing to STTR during scrubbing will not affect the scrubbing action.

ACCESS RULES

ADDRESS

READ

WRITE

24h

Always

D7

D6

D5

D4

STT4

D3

D2

D1

D0

STT7

STT6

STT5

STT3

STT2

STT1

STT0

Bit

Symbol

Description

k

l

D0–D7 STT0–STT7 SCRUB TIMER THRESHOLD BIT 0-7 : Scrub Timer threshold.

STT0 is the Least Significant Bit (LSB).

80

5.0 Registers (Continued)

5.37 SCRUB TIMER VALUE REGISTER (STVR)

This is a snap-shot of the current value of the upper 8 bits of the scrub timer.

During a Control Bus Interface write cycle, the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register

(ICR) will be set to 1 and will ignore a write cycle.

ACCESS RULES

ADDRESS

READ

WRITE

25h

Always

Write Reject

D7

D6

D5

STV5

D4

D3

D2

D1

D0

STV7

STV6

STV4

STV3

STV2

STV1

STV0

Bit

Symbol

Description

k

l

D0–D7 STV0–STV7 SCRUB TIMER VALUE BIT 0-7 : Snap-shot of the scrub timer.

STV0 is the Least Significant Bit (LSB).

81

5.0 Registers (Continued)

5.38 TRIGGER DEFINITION REGISTER (TDR)

This register determines which events cause a trigger transition and which transmit mode is entered when a trigger transition is

detected. The trigger transmit modes are the same as those found in the Current Transmit State Register (CTSR), and are

loaded from the TDR into the CTSR when any of the selected trigger conditions occur. When a trigger condition occurs

CMTCR.TCO is set.

The Trigger Definition Register is useful to implement the strict PC React time requirement.

Ð

ACCESS RULES

ADDRESS

READ

WRITE

26h

Always

D7

D6

D5

D4

TOMLS

D3

D2

D1

D0

TONT

TOQLS

TOHLS

TOSILS

TTM2

TTM1

TTM0

Bit Symbol

Description

k

l

D0, TTM0,

D1, TTM1,

TRIGGER TRANSMIT MODE 0, 1, 2 : These bits select one of 6 transmission modes to be loaded into the

Current Transmit State Register (CTSR) when a trigger condition is detected. The trigger condition is selected by

the upper 5 bits of this register.

D2

TTM2

TTM2 TTM1 TTM0

0

1

0

1

0

Active Transmit Mode (ATM): Normal transmission of incoming PHY Request data.

Idle Transmit Mode (ITM): Transmission of Idle symbol pairs (11111 11111).

Off Transmit Mode (OTM): Transmission of Quiet symbol pairs (00000 00000) and

deassertion of the PMD transmitter Enable pin (TXE).

0

1

0

1

0

Reserved: Reserved for future use. Users are discouraged from using this transmit

mode. If selected, however, the transmitter will generate Quiet symbol pairs

(00000 00000).

Master Transmit Mode (MTM): Transmission of Halt and Quiet symbol pairs

(00100 00000).

1

0

1

0

1

Halt Transmit Mode (HTM): Transmission of Halt symbol pairs (00100 00100).

Quiet Transmit Mode (QTM): Transmission of Quiet symbol pairs (00000 00000).

Reserved: Reserved for future use. Users are discouraged from using this transmit

mode. If selected, however, the transmitter will generate Quiet symbol pairs

(00000 00000).

D3

D4

D5

D6

D7

TOSILS TRIGGER ON SILS: Trigger when SILS is received.

TOMLS TRIGGER ON MLS: Trigger when MLS is received.

TOHLS

TOQLS

TONT

TRIGGER ON HLS: Trigger when HLS is received.

TRIGGER ON QLS (or NSD): Trigger when QLS is received.

e

TRIGGER ON Noise Threshold: Trigger when Noise Threshold is reached (Current Noise Register 0).

82

5.0 Registers (Continued)

5.39 TRIGGER TRANSITION CONFIGURATION REGISTER (TTCR)

The Trigger Transition Configuration Register holds the configuration switch setting to be loaded into the Configuration Register

(CR) when a trigger transition takes place. When scrubbing is enabled, scrubbing is performed for a period of time indicated by

the Scrub Timer Threshold Register (STTR).The register bit descriptions for the Configuration Register and, therefore, the

Trigger Transition Configuration Register are reprinted below.

ACCESS RULES

ADDRESS

READ

WRITE

27h

Always

D7

D6

D5

D4

TRS0

D3

D2

D1

D0

BIE

AIE

TRS1

BIS1

BIS0

AIS1

AIS0

Bit

Symbol

Description

k l k l

A INDICATE SELECTOR 0, 1 : The A Indicate Selector 0, 1 bits selects one of the four

Ð Ð

D0, D1 AIS0, AIS1

k

l

Configuration Switch data buses for the A Indicate output port (AIP, AIC, AID 7:0 ).

Ð

AIS1

AIS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

k l k l

B INDICATE SELECTOR 0, 1 : The B Indicate Selector 0, 1 bits selects one of the four

Ð Ð

D2, D3 BIS0, BIS1

k

l

Configuration Switch data buses for the B Indicate output port (BIP, BIC, BID 7:0 ).

Ð

BIS1

BIS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver

A

B

Request Bus

Ð

Note: Even though this bit can be set and/or cleared in the DP83256 (for single path stations), it will not affect any I/Os since the

DP83256 does not offer a B Indicate port.

Ð

k

l

k

l

D4, D5 TRS0, TRS1 TRANSMIT REQUEST SELECTOR 0, 1 : The Transmit Request Selector 0, 1 bits selects one of

the four Configuration Switch data buses for the input to the Transmitter Block.

TRS1 TRS0

0

1

0

1

0

1

PHY Invalid Bus

Receiver Bus

A

B

Request Bus

Ð

k

l

Note: If the PLAYER device is in Active Transmit Mode (i.e. the Transmit Mode bits (TM 2:0 ) of the Current Transmit State

a

Register (CTSR) are set to 00) and the PHY Invalid Bus is selected, then the PLAYER device will transmit continuous Idle

a

symbols due to the Repeat Filter.

D6

D7

AIE

BIE

A

INDICATE ENABLE:

Ð

0: Disables the A Indicate output port. The A Indicate port pins will be tri-stated when the port is

Ð

disabled.

k

l

1: Enables the A Indicate output port (AIP, AIC, AID 7:0 ).

Ð

B

INDICATE ENABLE:

Ð

0: Disables the B Indicate output port. The B Indicate port pins will be tri-stated when the port is

Ð

disabled.

k

l

1: Enables the B Indicate output port (BIP, BIC, BID 7:0 ).

Ð

Note: Even though this bit can be set and/or cleared in the DP83256 (for single path stations), it will not affect any I/Os since the

DP83256 does not offer a B Indicate port.

Ð

83

5.0 Registers (Continued)

5.40 RESERVED REGISTERS 28H-3AH (RR28H-RR3AH)

These registers are reserved for future use.

DO NOT ACCESS THESE REGISTERS

ACCESS RULES

ADDRESS

READ

WRITE

28h–3Ah

Always

DO NOT WRITE

84

5.0 Registers (Continued)

5.41 CLOCK GENERATION MODULE REGISTER (CGMREG)

This register is used to enable or disable the 125 MHz ECL Transmit clock outputs. These outputs are not required for use in a

standard FDDI board implementation and are disabled by default to reduce high frequency noise.

These TXC outputs are included for support of alternate FDDI PMDs, such as unshielded twisted pair copper cable.

DO NOT WRITE TO RESERVED REGISTER BITS. Writes to reserved register bits could prevent proper device operation.

Therefore, read the register first, and then write it back with the non-reserved bits set to the desired value.

ACCESS RULES

ADDRESS

READ

WRITE

3Bh

Always

D7

D6

D5

D4

D3

D2

D1

D0

RES

FLTREN

RES

TXCE

RES

Bit

Symbol

Description

D0-D2 RES

RESERVED BITS: DO NOT CHANGE THE VALUE OF THESE BITS. Changes to reserved register bits could

prevent proper device operation.

D3

TXCE

RES

TRANSMIT CLOCK ENABLE: When bit is set to 1, 125 MHz ECL TXC outputs are enabled. When this bit is

reset to 0, TXC outputs are disabled. TXC outputs are disabled on reset.

a

Note: TXC clocks are only available on the 160-pin DP83257 PLAYER device.

D4

D5

RESERVED BITS: DO NOT CHANGE THE VALUE OF THESE BITS. Changes to reserved register bits could

prevent proper device operation.

FLTREN FILTER ENABLE: When bit is set to 1, the internal loop filter node is connected to the LPFLTR pin for

diagnostic viewing. This bit is reset to 0 by default, which disconnects the filter node from the LPFLTR pin.

e

Note: In normal operation this bit should be disabled ( 0).

D6-D7 RES

RESERVED BITS: DO NOT CHANGE THE VALUE OF THESE BITS. Changes to reserved register bits could

prevent proper device operation.

85

5.0 Registers (Continued)

5.42 ALTERNATE PMD REGISTER (APMDREG)

This register is used to enable or disable the Alternate PMD inputs and ouputs. These signals are not required for use in FDDI

a

board implementations that do not require a scrambler that is external to the PLAYER device. The actual interface consists of

the signal pairs RXC OUT, RXD OUT, RXC IN, and RXD IN.

Ð

The interface is disabled by default and should only be enabled if it is being used. Note that Long Internal Loopback should not

be used when the Alternate PMD Interface is enabled.

DO NOT WRITE TO RESERVED REGISTER BITS. Writes to reserved register bits could prevent proper device operation.

Therefore, read the register first, and then write it back with the non-reserved bits set to the desired value.

a

Note: The Alternate PMD Interface pins are only available on the 100-pin DP83256-AP and 160-pin DP83257 PLAYER devices. The Alternate PMD Interface is

disabled on reset.

ACCESS RULES

ADDRESS

READ

WRITE

3Ch

Always

D7

D6

D5

D4

RES

D3

D2

D1

D0

RES

APMDEN

RES

Bit

Symbol

Description

D0–D2 RES

RESERVED BITS: DO NOT CHANGE THE VALUE OF THESE BITS. Changes to reserved register bits could

prevent proper device operation.

D3

APMDEN ALTERNATE PMD ENABLE: When bit is set to 1, the Alternate PMD Interface is enabled. When this bit is

reset to 0, the Alternate PMD Interface is disabled.

The Alternate PMD Interface consists of the following extra ECL signal pairs

RXC OUT, RXD OUT, RXC IN, and RXD IN.

Ð

In some alternate PMD implementations it may also be necessary to use the 125 MHz Transmit Clock

signals (TXC). The TXC outputs must be separately enabled by the TXCE bit in the CGMREG register.

a

Note: The Alternate PMD Interface pins are only available on the 100-pin DP83256-AP and 160-pin DP83257 PLAYER devices. The

Alternate PMD Interface is disabled on reset.

D4–D7 RES

RESERVED BITS: DO NOT CHANGE THE VALUE OF THESE BITS. Changes to reserved register bits could

prevent proper device operation.

86

5.0 Registers (Continued)

5.43 GAIN REGISTER (GAINREG)

The Gain Register contains the settings for the CGM’s on-chip programmable loop filter. For optimal jitter performance on the

a

revision A and B PLAYER device’s Filter Position 4 should be used. The user should check that the IDR register is equal to

revision A or B (10h or 11h) before changing the filter setting as later revisions will default to the correct setting which may be a

different filter position number.

Pseudo Code Programming Example:

Care must be taken when changing the settings of the on-chip programmable loop filter. The filter should only be set to the

recommended value and the additional bits in the Gain Register must not be altered. Alteration of the reserved bits in the Gain

a

Register may result in improper PLAYER device operation.

The following pseudo code outlines the proper procedure for setting the Gain Register loop filter settings to the correct value.

// Register names and constants are all in UPPERCASE

//

#define REV B 0x11

#define REV A 0x10

#define LOOP MASK 0x1F

#define NEW LOOP 0x40

k

À

4 REV B)

if (IDR

temp 4 GAIN REG

temp 4 temp & LOOP MASK

temp 4 temp NEW LOOP

l

GAIN REG 4 temp

Ó

À

else Do Nothing

Ó

ACCESS RULES

ADDRESS

READ

WRITE

3Dh

Always

D7

D6

FILT1

D5

D4

RES

D3

D2

D1

D0

FILT2

FILT0

RES

Bit

Symbol

Description

D0–D4

RES

RESERVED: Do not alter these bits. The device may cease to operate properly if these bits are

changed.

k

l

k

FILTER SELECTION 0, 1, 2 : The Filter Selection 0, 1, 2 bits select one of five on-chip CGM

l

FILT0,

FILT1,

FILT2

D5–D7

loop filters.

Note: Filter combinations that are not specified or recommended should not be used and may result in non-optimal device

performance.

FILT2

FILT1

FILT0

1

0

1

0

1

0

FP0: Filter Position 0.

FP1: Filter Position 1.

FP2: Filter Position 2. This is the filter selected after reset on the

a

revision A and B PLAYER devices.

0

1

0

FP3: Filter Position 3.

FP4: Filter Position 4. This is the recommended filter position for

a

the revision A and B PLAYER devices.

87

5.0 Registers (Continued)

5.44 RESERVED REGISTERS 3EH-3FH (RR3EH-RR3FH)

These registers are reserved for future use.

DO NOT ACCESS THESE REGISTERS

ACCESS RULES

ADDRESS

READ

WRITE

3Eh–3Fh

Always

DO NOT WRITE

88

6.0 Signal Descriptions

6.1 DP83256VF PIN DESCRIPTIONS

The pin descriptions for the DP83256VF are divided into 5 functional interfaces: PMD Interface, PHY Port Interface, Control Bus

Interface, Clock Interface, and Miscellaneous Interface.

For a Pinout Summary list, refer to Table 8-1 and Figure 8-1, DP83256VF 100-Pin JEDEC Metric PQFP Pinout.

PMD INTERFACE

a

The PMD Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependant (PMD)

sublayer.

Ý

Symbol Pin

I/O

Description

a

b

PMID

39

I

PMD Indicate Data: Differential, 100k ECL, 125 Mbps serial data input signals from the PMD receiver.

38

a

b

PMRD

33

32

O

I

PMD Request Data: Differential, 100k ECL, 125 Mbps serial data output signals to the PMD transmitter.

a

b

SD

37

36

Signal Detect: Differential 100k ECL input signals from the PMD receiver indicating that a signal is being

received by the PMD receiver.

TEL

47

I

PMD Transmitter Enable Level: A TTL input signal to select the PMD transmitter Enable (TXE) signal

level.

TXE

46

O

PMD Transmitter Enable: A TTL output signal to enable/disable the PMD transmitter. The output level

of the TXE pin is determined by three parameters: the Transmit Enable (TE) bit in the Mode Register, the

TM2-TM0 bits in the Current Transmit State Register, and the input to the TEL pin. The following rules

summarize the output of the TXE pin:

e

1. If TE 0 and TEL GND, then TXE V

CC

e

, then TXE GND

2. If TE 0 and TEL

V

CC

e

3. If TE 1 and OTM and TEL GND, then TXE V

e

CC

, then TXE GND

e

5. If TE 1 and not OTM and TEL GND, then TXE GND

4. If TE 1 and OTM and TEL

V

CC

e

6. If TE 1 and not OTM and TEL

e

V , then TXE V

CC CC

89

6.0 Signal Descriptions (Continued)

PHY PORT INTERFACE

a

The PHY Port Interface consists of I/O signals used to connect the PLAYER device to the Media Access Control (MAC)

sublayer or other PLAYER device. The DP83256 Device has two PHY Port Interfaces. The A Indicate path from one PHY

a

Ð

Port Interface and the B Request path from the second PHY Port Interface. Each path consists of an odd parity bit, a control

Ð

bit, and two 4-bit symbols.

Refer to section 3.3, the Configuration Switch, for more information.

Ý

Symbol Pin

I/O

Description

AIP

6

O

PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit wide Port A

k

l

Indicate signals (AIP, AIC, and AID 7:0 ).

k

l

PHY Port A Indicate Control: TTL output signal indicating that the two 4-bit symbols (AID 7:4 and

AIC

7

O

k

l

AID 3:0 ) are either control symbols (AIC 1) or data symbols (AIC 0).

e

AID7

AID6

AID5

AID4

8

9

PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control symbol.

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.

10

13

AID3

AID2

AID1

AID0

14

15

16

17

O

PHY Port A Indicate Data: TTL output signals representing the second 4-bit data/control symbol.

AID3 is the most significant bit and AID0 is the least significant bit of the second symbol.

BRP

70

I

PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit wide Port A

k

l

Request signals (BRP, BRC, and BRD 7:0 ).

BRC

69

PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols

k

l

k

l

e

(BRD 7:4 and BRD 3:0 ) are either control symbols (BRC 1) or data symbols (BRC 0).

PHY Port B Request Data: TTL input signals representing the first 4-bit data/control symbol.

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.

BRD7

BRD6

BRD5

BRD4

68

67

66

63

I

BRD3

BRD2

BRD1

BRD0

62

61

60

59

PHY Port B Request Data: TTL input signals representing the second 4-bit data/control symbol.

BRD3 is the most significant bit and BRD0 is the least significant bit of the second symbol.

90

6.0 Signal Descriptions (Continued)

CONTROL BUS INTERFACE

a

The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMT).

a

The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor or other

controller. It provides access to 64 8-bit internal registers.

a

In the PLAYER device the Control Bus address range has been expanded by 1-bit to 6 bits of address space.

Ý

Symbol Pin

I/O

Description

E

CE

73

I

Control Enable: An active-low, TTL, input signal which enables the Control Bus port for a read or write

k

l

k

cycle. R/ W, CBA 5:0 , CBP, and CBD 7:0 must be valid at the time CE is low.

l

E

Read/ Write: A TTL input signal which indicates a read Control Bus cycle(R/

Control Bus cycle (R/

E

e

W 1), or a write

R/

W

72

I

E

e

0).

W

E

or write cycle. During a read cycle, CBD 7:0 are valid as long as ACK is low ( ACK 0). During a

ACK

75

O

Acknowledge: An active low, TTL, open drain output signal which indicates the completion of a read

l

k

write cycle, a microprocessor must hold CBD 7:0 valid until ACK becomes low. Once ACK is low,

E

e

k

l

it will remain low as long as CE remains low ( CE 0).

E

e

E

INT

74

O

I

Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt condition has

occurred. The Interrupt Condition Register (ICR) should be read in order to find out the source of the

interrupt. Interrupts can be masked through the use of the Interrupt Condition Mask Register (ICMR).

CBA5

CBA4

CBA3

CBA2

CBA1

CBA0

83

82

81

80

77

76

Control Bus Address: TTL input signals used to select the address of the register to be read or written.

CBA5 is the most significant bit (MSB) and CBA0 is the least significant bit (LSB) of the address signals.

CBP

96

I/O Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control Bus data

k

l

(CBD 7:0 ).

a

E

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

E

During a write cycle, the signal must be valid when CE is low, and must be held valid until ACK

becomes low. If incorrect parity is used during a write cycle, the PLAYER device will inhibit the write

a

cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt Condition Register (ICR).

CBD7

CBD6

CBD5

CBD4

CBD3

CBD2

CBD1

CBD0

95

94

93

92

91

90

89

86

I/O Control Bus Data: Bidirectional, TTL signals containing the data to be read from or written to a register.

a

E

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

E

During a write cycle, the signal must be valid when CE is low, and must be held valid until ACK

becomes low.

91

6.0 Signal Descriptions (Continued)

CLOCK INTERFACE

a

The Clock Interface consists of 12.5 MHz and 25 MHz clocks supplied by the PLAYER device as well as reference and

feedback inputs.

Ý

Symbol

LBC1

I/O

Description

4

3

2

1

O

Local Byte Clock: TTL compatible, 12.5 MHz, 50% duty cycle clock outputs which are phase

locked to a crystal oscillator or reference signal. The PH SEL input determines whether the five

phase outputs are phase offset by 8 ns or 16 ns.

LBC2

LBC3

LBC4

LBC5

Ð

100

PH SEL

Ð

22

25

99

5

I

Phase Select: TTL compatible input used to select either a 8 ns or 16 ns phase offset between the 5

local byte clocks (LBC’s). The LBC’s are phase offset 8ns apart when PH SEL is at a logic LOW

level and 16 ns apart when at a logic HI level.

Ð

FBK IN

Ð

I

Feedback Input: TTL compatible input for use as the PLL’s phase comparator feedback input to

close the Phase Locked Loop. This input is intended to be driven from one of the Local Byte Clocks

a

(LBC’s) from the same PLAYER device.

LSC

O

Local Symbol Clock: TTL compatible 25 MHz output for driving the MACSI or BMAC devices. This

output’s negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and

60% LOW duty cycle.

CLK16

Clock 16/32: TTL compatible clock with a selectable frequency of approximately 15.625 MHz or

31.25 MHz. The frequency can be selected using the Clock Select (CLKSEL) bit of the Mode 2

Register (MODE2).

Note: No glitches appear at the output when switching frequencies.

XTAL IN

Ð

27

I

External Crystal Oscillator Input: This input in conjunction with the XTAL OUT output, is

Ð

designed for use of an external crystal oscillator network as the frequency reference for the clock

generation module’s internal VCO. A diagram of the required circuit, which includes only a 12.5 MHz

crystal and 2 loading capacitors, is shown inFigure 3-19.

This input is selected when the REF SEL input is at a logic LOW level. When not being used, this

Ð

input should be tied to ground.

XTAL OUT

Ð

26

24

23

30

O

I

External Crystal Oscillator Output: This output in conjunction with the XTAL IN input, is designed

Ð

for use of an external crystal oscillator network as the frequency reference for the clock generation

module’s internal VCO. A diagram of the required circuit, which includes only a 12.5 MHz crystal and

2 loading capacitors, is shown inFigure 3-19.

REF IN

Ð

Reference Input: TTL compatible input for use as the PLL’s phase comparator reference frequency.

This input is for use in dual attach station or concentrator configurations where there are multiple

a

PLAYER devices at a given site requiring synchronization.

This input is selected when the REF SEL input is at a logic HI level.

Ð

REF SEL

Ð

I

Reference Select: TTL compatible input which selects either the crystal oscillator inputs XTAL IN

Ð

and XTAL OUT or the REF IN inputs as the reference frequency inputs for the PLL.

Ð Ð

The crystal oscillator inputs are selected when REF SEL is at a logic LOW level and the REF IN

Ð

input is selected as the reference when REF SEL is at a logic HI level.

Ð

LPFLTR

O

Loop Filter: This is a diagnostic output that allows monitoring of the clock generation module’s filter

node. This output is disabled by default and does not need to be connected to any external device. It

can be enabled using the FLTREN bit of the Clock generation module register (CGMREG).

Note: In normal operation this pin should be disabled.

92

6.0 Signal Descriptions (Continued)

MISCELLANEOUS INTERFACE

The Miscellaneous Interface consist of a reset signal, user definable sense signals, and user definable enable signals.

Ý

Symbol Pin

I/O

Description

E

RST

71

I

Reset: An active low, TTL, input signal which clears all registers. The signal must be kept asserted for a

E

a

minimum amount of time. Once the RST signal is asserted, the PLAYER device should be allowed

the specified amount of time to reset internal logic. Note that bit zero of the Mode Register will be set to

zero (i.e. Stop Mode). See section 4.2, Stop Mode of Operation for more information

SP0

40

I

User Definable Sense Pin 0: A TTL input signal from a user defined source. Sense Bit 0 (SB0) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns. Once

the asserted signal is latched, Sense Bit 0 can only be cleared through the Control Bus Interface, even if

the signal is deasserted. This ensures that the Control Bus Interface will record the source of events

which can cause interrupts.

SP1

42

User Definable Sense Pin 1: A TTL input signal from a user defined source. Sense Bit 1 (SB1) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns. Once

the asserted signal is latched, Sense Bit 1 can only be cleared through the Control Bus Interface, even if

the signal is deasserted. This ensures that the Control Bus Interface will record the source of events

which can cause interrupts.

EP0

EP1

41

43

O

User Definable Enable Pin 0: A TTL output signal allowing control of external logic through the Control

Bus Interface. EP0 is asserted/deasserted through Enable Bit 0 (EB0) of the User Definable Register

(UDR). When Enable Bit 0 is set to zero, EP0 is deasserted. When Enable Bit 0 is set to one, EP0 is

asserted.

User Definable Enable Pin 1: A TTL output signal allowing control of external logic through the Control

Bus Interface. EP1 is asserted/deasserted through Enable Bit 1 (EB1) of the User Definable Register

(UDR). When Enable Bit 1 is set to zero, EP1 is deasserted. When Enable Bit 1 is set to one, EP1 is

asserted.

93

6.0 Signal Descriptions (Continued)

POWER AND GROUND

a

All power pins should be connected to a single 5V power supply using the recommended filtering. All ground pins should be

connected to a common 0V ground supply. Bypassing and filtering requirements are given in a separate User Information

Document.

Ý

Symbol

ANALOG

I/O

Description

a

Power: Positive 5V power supply for the PLAYER device’s CGM VCO.

V

CC

20

Ð

a

Ground: Power supply return for the PLAYER device’s CGM VCO.

GND ANALOG

Ð

21

88

87

V

CC

CORE

Power: Positive 5V power supply for the core PLAYER section logic gates.

Ground: Power supply return for the core PLAYER section logic gates.

Ð

GND CORE

Ð

a

Power: Positive 5V power supply for the PLAYER device’s ECL logic gates.

V

CC

ECL

31,

34,

44,

56

Ð

a

Ground: Power supply return for the PLAYER device’s ECL logic gates.

GND ECL

Ð

35,

45,

55

a

Power: Positive 5V power supply for the PLAYER device’s ESD protection circuitry.

V

ESD

28

29

CC

Ð

a

Ground: Power supply return for the PLAYER device’s ESD protection circuitry.

GND ESD

Ð

V

CC

IO

11,

65,

79,

98

Power: Positive 5V power supply for the input/output buffers.

Ð

GND IO

Ð

12,

64,

78,

97

Ground: Power supply return for the input/output buffers.

SPECIAL CONNECT PINS

These are pins that have special connection requirements.

No Connect (N/C) pins should not be connected to anything. This means not to power, not to ground, and not to each other.

Reserved 0 (RES 0) pins must be connected to ground. These pins are not used to supply device power so they do not need

Ð Ð

to be filtered or bypassed.

Reserved 1 (RES 1) pins must be connected to power. These pins are not used to supply device power so they do not need

Ð Ð

to be filtered or bypassed.

Ý

Symbol Pin

I/O

Description

N/C

49, 54

No Connect: Pins should not be connected to anything. This means not to power, not to ground, and

not to each other.

RES

0

1

18, 19,

48, 50,

51, 52,

53, 57,

58, 84

Reserved 0: Pins must be connected to ground. These pins are not used to supply device power so

they do not need to be filtered or bypassed.

Ð

RES

85

Reserved 1: Pins must be connected to power. These pins are not used to supply device power so they

do not need to be filtered or bypassed.

94

6.0 Signal Descriptions (Continued)

6.2 DP83256VF-AP SIGNAL DESCRIPTIONS

The pin descriptions for the DP83256VF-AP are divided into five functional interfaces; PMD Interface, PHY Port Interface,

Control Bus Interface, Clock Interface, and Miscellaneous Interface.

For a Pinout Summary List, refer to Table 8-2 and Figure 8-2, DP83256VF-AP 100-Pin JEDEC Metric PQFP Pinout.

PMD INTERFACE

a

The PMD Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependant (PMD)

sublayer.

a

The DP83256VF-AP PLAYER device actually has two PMD interfaces. The Primary PMD Interface and the Alternate PMD

Interface.

The Primary PMD Interface should be used for all PMD implementations that do not require an external scrambler/descrambler

function, clock recovery function, or clock generation function, such as a Fiber Optic or Shielded Twisted Pair (SDDI) PMD. The

second, Alternate PMD Interface can be used to support Unshielded Twisted Pair (UTP) PMDs that require external scrambling,

with no external clock recovery or clock generation functions required.

a

Section 3.8 describes how the PLAYER can be connected to the PMD and how the Alternate PMD can be enabled.

Note that when the Alternate PMD Interface is not being used, the pins that make up the interface must be connected in the

specific way described in the following Alternate PMD Interface table.

Primary PMD Interface

Ý

Symbol Pin

I/O

Description

a

b

PMID

42

I

PMD Indicate Data: Differential, 100k ECL, 125 Mbps serial data input signals from the PMD Receiver

a

into the Clock Recovery Module (CRM) of the PLAYER

.

41

a

b

PMRD

34

33

O

I

PMD Request Data: Differential, 100k ECL, 125 Mbps serial data output signals to the PMD transmitter.

a

b

SD

40

39

Signal Detect: Differential 100k ECL input signals from the PMD receiver indicating that a signal is being

received by the PMD receiver.

95

6.0 Signal Descriptions (Continued)

Alternate PMD Interface

Ý

Symbol

I/O

Description

a

b

PMID

42

I

PMD Indicate Data: Differential, 100k ECL, 125 Mbps serial data input signals from the PMD

a

Receiver into the Clock Recovery Module (CRM) of the PLAYER

.

41

a

b

RXC OUT

Ð

RXC OUT

36

35

O

I

Recovered Clock Out: 125 MHz clock recovered by the Clock Recovery Module (CRM) from the

PMID data input.

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used they should be left Not Connected (N/C).

a

b

RXD OUT

Ð

RXD OUT

52

51

Recovered Data Out: 125 Mbps data recovered by the Clock Recovery Module (CRM) from the

PMID data input.

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used they should be left Not Connected (N/C).

a

b

a

Receive Clock In: Clock inputs to the Player section of the PLAYER . These inputs must be

synchronized with the RXD IN inputs.

Ð

RXC IN

Ð

RXC IN

48

47

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used, pin 76 should be left Not Connected (N/C) and pin 75 should be

connected directly to ground (Reserved 0).

Ð

a

b

a

Receive Data In: Data inputs to the Player section of the PLAYER . These inputs must be

synchronized with the RXC IN inputs.

Ð

RXD IN

Ð

RXD IN

50

49

I

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used, pin 78 should be left Not Connected (N/C) and pin 77 should be

connected directly to ground (Reserved 0).

Ð

a

b

PMRD

34

33

O

PMD Request Data: Differential, 100k ECL, 125 Mbps serial data output signals to the PMD

transmitter.

a

b

TXC

31

30

Transmit Clock: 125 MHz, 100k ECL compatible differential outputs synchronized to the outgoing

PMRD data.

These signals can be enabled using the Transmit Clock Enable (TXCE) bit in the Clock Generation

Module Register (CGMREG).

When these two pins are not used they should be left Not Connected (N/C).

a

b

SD

40

39

I

Signal Detect: Differential, 100k ECL, input signals from the PMD receiver indicating that a signal

is being received by the PMD receiver.

96

6.0 Signal Descriptions (Continued)

PHY PORT INTERFACE

a

The PHY Port Interface consists of I/O signals used to connect the PLAYER device to the Media Access Control (MAC)

sublayer or other PLAYER device. The DP83256 Device has two PHY Port Interfaces. The A Indicate path from one PHY

a

Ð

Port Interface and the B Request path from the second PHY Port Interface. Each path consists of an odd parity bit, a control

Ð

bit, and two 4-bit symbols.

Refer to section 3.3, the Configuration Switch, for more information.

Ý

Symbol Pin

I/O

Description

AIP

6

O

PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit wide Port A

k

l

Indicate signals (AIP, AIC, and AID 7:0 ).

k

l

PHY Port A Indicate Control: TTL output signal indicating that the two 4-bit symbols (AID 7:4 and

AIC

7

O

k

l

AID 3:0 ) are either control symbols (AIC 1) or data symbols (AIC 0).

e

AID7

AID6

AID5

AID4

8

9

PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control symbol.

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.

10

13

AID3

AID2

AID1

AID0

14

15

16

17

O

PHY Port A Indicate Data: TTL output signals representing the second 4-bit data/control symbol.

AID3 is the most significant bit and AID0 is the least significant bit of the second symbol.

BRP

70

I

PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit wide Port A

k

l

Request signals (BRP, BRC, and BRD 7:0 ).

k

l

PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols (BRD 7:4 and

BRC

69

k

l

BRD 3:0 ) are either control symbols (BRC 1) or data symbols (BRC 0).

e

BRD7

BRD6

BRD5

BRD4

68

67

66

63

PHY Port B Request Data: TTL input signals representing the first 4-bit data/control symbol.

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.

BRD3

BRD2

BRD1

BRD0

62

61

60

59

I

PHY Port B Request Data: TTL input signals representing the second 4-bit data/control symbol.

BRD3 is the most significant bit and BRD0 is the least significant bit of the second symbol.

97

6.0 Signal Descriptions (Continued)

CONTROL BUS INTERFACE

a

The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMT).

a

The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor or other

controller. It provides access to 64 8-bit internal registers.

a

In the PLAYER device the Control Bus address range has been expanded by 1-bit to 6 bits of address space.

Ý

Symbol Pin

I/O

Description

E

CE

73

I

Control Enable: An active-low, TTL, input signal which enables the Control Bus port for a read or write

k

l

k

cycle. R/ W, CBA 5:0 , CBP, and CBD 7:0 must be valid at the time CE is low.

l

E

Read/ Write: A TTL input signal which indicates a read Control Bus cycle (R/

Control Bus cycle (R/

E

e

W 1), or a write

R/

W

72

I

E

e

0).

W

E

or write cycle. During a read cycle, CBD 7:0 are valid as long as ACK is low ( ACK 0). During a

ACK

75

O

Acknowledge: An active low, TTL, open drain output signal which indicates the completion of a read

l

k

write cycle, a microprocessor must hold CBD 7:0 valid until ACK becomes low. Once ACK is low,

E

e

k

l

it will remain low as long as CE remains low ( CE 0).

E

e

E

INT

74

O

I

Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt condition has

occurred. The Interrupt Condition Register (ICR) should be read in order to find out the source of the

interrupt. Interrupts can be masked through the use of the Interrupt Condition Mask Register (ICMR).

CBA5

CBA4

CBA3

CBA2

CBA1

CBA0

83

82

81

80

77

76

Control Bus Address: TTL input signals used to select the address of the register to be read or written.

CBA5 is the most significant bit (MSB) and CBA0 is the least significant bit (LSB) of the address signals.

CBP

96

I/O Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control Bus data

k

l

(CBD 7:0 ).

a

E

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

E

During a write cycle, the signal must be valid when CE is low, and must be held valid until ACK

becomes low. If incorrect parity is used during a write cycle, the PLAYER device will inhibit the write

a

cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt Condition Register (ICR).

CBD7

CBD6

CBD5

CBD4

CBD3

CBD2

CBD1

CBD0

95

94

93

92

91

90

89

86

I/O Control Bus Data: Bidirectional, TTL signals containing the data to be read from or written to a register.

a

E

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

E

During a write cycle, the signal must be valid when CE is low, and must be held valid until ACK

becomes low.

98

6.0 Signal Descriptions (Continued)

CLOCK INTERFACE

a

The Clock Interface consists of 12.5 MHz and 25 MHz clocks supplied by the PLAYER device as well as reference and

feedback inputs.

Ý

Symbol

LBC1

I/O

Description

4

3

2

1

O

Local Byte Clock: TTL compatible, 12.5 MHz, 50% duty cycle clock outputs which are phase

locked to a crystal oscillator or reference signal. The PH SEL input determines whether the five

phase outputs are phase offset by 8 ns or 16 ns.

LBC2

LBC3

LBC4

LBC5

Ð

100

PH SEL

Ð

22

25

99

5

I

Phase Select: TTL compatible input used to select either a 8 ns or 16 ns phase offset between the 5

local byte clocks (LBC’s). The LBC’s are phase offset 8 ns apart when PH SEL is at a logic LOW

level and 16 ns apart when at a logic HI level.

Ð

FBK IN

Ð

I

Feedback Input: TTL compatible input for use as the PLL’s phase comparator feedback input to

close the Phase Locked Loop. This input is intended to be driven from one of the Local Byte Clocks

a

(LBC’s) from the same PLAYER device.

LSC

O

Local Symbol Clock: TTL compatible 25 MHz output for driving the MACSI or BMAC devices. This

output’s negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and

60% LOW duty cycle.

CLK16

Clock 16/32: TTL compatible clock with a selectable frequency of approximately 15.625 MHz or

31.25 MHz. The frequency can be selected using the Clock Select (CLKSEL) bit of the Mode 2

Register (MODE2).

Note: No glitches appear at the output when switching frequencies.

XTAL IN

Ð

27

I

External Crystal Oscillator Input: This input in conjunction with the XTAL OUT output, is

Ð

designed for use of an external crystal oscillator network as the frequency reference for the clock

generation module’s internal VCO. A diagram of the required circuit, which includes only a 12.5 MHz

crystal and 2 loading capacitors, is shown inFigure 3-19.

This input is selected when the REF SEL input is at a logic LOW level. When not being used, this

Ð

input should be tied to ground.

XTAL OUT

Ð

26

24

23

O

I

External Crystal Oscillator Output: This output in conjunction with the XTAL IN input, is designed

Ð

for use of an external crystal oscillator network as the frequency reference for the clock generation

module’s internal VCO. A diagram of the required circuit, which includes only a 12.5 MHz crystal and

2 loading capacitors, is shown inFigure 3-19.

REF IN

Ð

Reference Input: TTL compatible input for use as the PLL’s phase comparator reference frequency.

This input is for use in dual attach station or concentrator configurations where there are multiple

a

PLAYER devices at a given site requiring synchronization.

This input is selected when the REF SEL input is at a logic HI level.

Ð

REF SEL

Ð

I

Reference Select: TTL compatible input which selects either the crystal oscillator inputs XTAL IN

Ð

and XTAL OUT or the REF IN inputs as the reference frequency inputs for the PLL.

Ð Ð

The crystal oscillator inputs are selected when REF SEL is at a logic LOW level and the REF IN

Ð

input is selected as the reference when REF SEL is at a logic HI level.

Ð

99

6.0 Signal Descriptions (Continued)

MISCELLANEOUS INTERFACE

The Miscellaneous Interface consist of a reset signal and user definable enable signals.

Ý

Symbol Pin

I/O

Description

E

RST

71

I

Reset: An active low, TTL, input signal which clears all registers. The signal must be kept asserted for a

E

a

minimum amount of time. Once the RST signal is asserted, the PLAYER device should be allowed

the specified amount of time to reset internal logic. Note that bit zero of the Mode Register will be set to

zero (i.e. Stop Mode). See section 4.2, Stop Mode of Operation for more information

EP0

41

O

User Definable Enable Pin 0: A TTL output signal allowing control of external logic through the Control

Bus Interface. EP0 is asserted/deasserted through Enable Bit 0 (EB0) of the User Definable Register

(UDR). When Enable Bit 0 is set to zero, EP0 is deasserted. When Enable Bit 0 is set to one, EP0 is

asserted.

EP1

43

User Definable Enable Pin 1: A TTL output signal allowing control of external logic through the Control

Bus Interface. EP1 is asserted/deasserted through Enable Bit 1 (EB1) of the User Definable Register

(UDR). When Enable Bit 1 is set to zero, EP1 is deasserted. When Enable Bit 1 is set to one, EP1 is

asserted.

100

6.0 Signal Descriptions (Continued)

POWER AND GROUND

a

All power pins should be connected to a single 5V power supply using the recommended filtering. All ground pins should be

connected to a common 0V ground supply. Bypassing and filtering requirements are given in a separate User Information

Document.

Ý

Symbol

ANALOG

I/O

Description

V

20

Power: Positive 5V power supply for the Clock Generation Module VCO.

Ground: Power supply return for the Clock Generation Module VCO.

Power: Positive 5V power supply for the core PLAYER section logic gates.

Ground: Power supply return for the core PLAYER section logic gates.

CC

Ð

GND ANALOG

Ð

21

88

87

V

CC

CORE

Ð

GND CORE

Ð

a

Power: Positive 5V power supply for the PLAYER device’s ECL logic gates.

V

CC

ECL

32,

37,

45,

56

Ð

a

Ground: Power supply return for the PLAYER device’s ECL logic gates.

GND ECL

Ð

38,

46,

55

a

Power: Positive 5V power supply for the PLAYER device’s ESD protection circuitry.

V

ESD

28

29

CC

Ð

a

Ground: Power supply return for the PLAYER device’s ESD protection circuitry.

GND ESD

Ð

V

CC

IO

11,

65,

79,

98

Power: Positive 5V power supply for the input/output buffers.

Ð

GND IO

Ð

12,

64,

78,

97

Ground: Power supply return for the input/output buffers.

SPECIAL CONNECT PINS

These are pins that have special connection requirements.

No Connect (N/C) pins should not be connected to anything. This means not to power, not to ground, and not to each other.

Reserved 0 (RES 0) pins must be connected to ground. These pins are not used to supply device power so they do not need

Ð Ð

to be filtered or bypassed.

Reserved 1 (RES 1) pins must be connected to power. These pins are not used to supply device power so they do not need

Ð Ð

to be filtered or bypassed.

Ý

Symbol Pin

I/O

Description

49, 53,

54

N/C

No Connect: Pins should not be connected to anything. This means not to power, not to ground, and

not to each other.

RES

0

1

18, 19,

48, 50,

51, 52,

57, 58,

84

Reserved 0: Pins must be connected to ground. These pins are not used to supply device power so

they do not need to be filtered or bypassed.

Ð

RES

85

Reserved 1: Pins must be connected to power. These pins are not used to supply device power so they

do not need to be filtered or bypassed.

101

6.0 Signal Descriptions (Continued)

6.3 DP83257VF SIGNAL DESCRIPTIONS

The pin descriptions for the DP83257VF are divided into five functional interfaces; PMD Interface, PHY Port Interface, Control

Bus Interface, Clock Interface, and Miscellaneous Interface.

For a Pinout Summary List, refer to Table 8-3 and Figure 8-3, DP83257VF 160-Pin JEDEC Metric PQFP Pinout.

PMD INTERFACE

a

The PMD Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependant (PMD)

sublayer.

a

The DP83257 PLAYER device actually has two PMD interfaces. The Primary PMD Interface and the Alternate PMD Interface.

The Primary PMD Interface should be used for all PMD implementations that do not require an external scrambler/descrambler

function, clock recovery function, or clock generation function, such as a Fiber Optic or Shielded Twisted Pair (SDDI) PMD. The

second, Alternate PMD Interface can be used to support Unshielded Twisted Pair (UTP) PMDs that require external scrambling,

with no external clock recovery or clock generation functions required.

a

Section 3.8 describes how the PLAYER can be connected to the PMD and how the Alternate PMD can be enabled.

Note that when the Alternate PMD Interface is not being used, the pins that make up the interface must be connected in the

specific way described in the following Alternate PMD Interface table.

Primary PMD Interface

Ý

Symbol Pin

I/O

Description

a

b

PMID

62

I

PMD Indicate Data: Differential, 100k ECL, 125 Mbps serial data input signals from the PMD Receiver

a

into the Clock Recovery Module (CRM) of the PLAYER

.

61

a

b

PMRD

54

53

O

I

PMD Request Data: Differential, 100k ECL, 125 Mbps serial data output signals to the PMD transmitter.

a

b

SD

60

59

Signal Detect: Differential 100k ECL input signals from the PMD receiver indicating that a signal is being

received by the PMD receiver.

TEL

74

I

PMD Transmitter Enable Level: A TTL input signal to select the PMD transmitter Enable (TXE) signal

level.

TXE

73

O

PMD Transmitter Enable: A TTL output signal to enable/disable the PMD transmitter. The output level

of the TXE pin is determined by three parameters: the Transmit Enable (TE) bit in the Mode Register, the

TM2–TM0 bits in the Current Transmit State Register, and the input to the TEL pin. The following rules

summarize the output of the TXE pin:

e

1. If TE 0 and TEL GND, then TXE V

CC

e

, then TXE GND

2. If TE 0 and TEL

V

CC

e

3. If TE 1 and OTM and TEL GND, then TXE V

e

CC

, then TXE GND

e

5. If TE 1 and not OTM and TEL GND, then TXE GND

4. If TE 1 and OTM and TEL

V

CC

e

6. If TE 1 and not OTM and TEL

e

V , then TXE V

CC CC

102

6.0 Signal Descriptions (Continued)

Alternate PMD Interface

Ý

Symbol

I/O

Description

a

b

PMID

62

I

PMD Indicate Data: Differential, 100k ECL, 125 Mbps serial data input signals from the PMD

a

Receiver into the Clock Recovery Module (CRM) of the PLAYER

.

61

a

b

RXC OUT

Ð

RXC OUT

56

55

O

I

Recovered Clock Out: 125 MHz clock recovered by the Clock Recovery Module (CRM) from the

PMID data input.

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used they should be left Not Connected (N/C).

a

b

RXD OUT

Ð

RXD OUT

83

82

Recovered Data Out: 125 Mbps data recovered by the Clock Recovery Module (CRM) from the

PMID data input.

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used they should be left Not Connected (N/C).

a

b

a

Receive Clock In: Clock inputs to the Player section of the PLAYER . These inputs must be

synchronized with the RXD IN inputs.

Ð

RXC IN

Ð

RXC IN

76

75

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used, pin 76 should be left Not Connected (N/C) and pin 75 should be

connected directly to ground (Reserved 0).

Ð

a

b

a

Receive Data In: Data inputs to the Player section of the PLAYER . These inputs must be

synchronized with the RXC IN inputs.

Ð

RXD IN

Ð

RXD IN

78

77

I

Ð

These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD

Register (APMDREG) is set to a 1 and are off by default after Reset.

When these two pins are not used, pin 78 should be left Not Connected (N/C) and pin 77 should be

connected directly to ground (Reserved 0).

Ð

a

b

PMRD

54

53

O

PMD Request Data: Differential, 100k ECL, 125 Mbps serial data output signals to the PMD

transmitter.

a

b

TXC

51

50

Transmit Clock: 125 MHz, 100k ECL compatible differential outputs synchronized to the outgoing

PMRD data.

These signals can be enabled using the Transmit Clock Enable (TXCE) bit in the Clock Generation

Module Register (CGMREG).

When these two pins are not used they should be left Not Connected (N/C).

a

b

SD

60

59

I

Signal Detect: Differential, 100k ECL, input signals from the PMD receiver indicating that a signal

is being received by the PMD receiver.

TEL

74

PMD Transmitter Enable Level: A TTL input signal to select the PMD transmitter Enable (TXE)

signal level.

TXE

73

O

PMD Transmitter Enable: A TTL output signal to enable/disable the PMD transmitter. The output

level of the TXE pin is determined by three parameters: the Transmit Enable (TE) bit in the Mode

Register, the TM2–TM0 bits in the Current Transmit State Register, and the input to the TEL pin.

The following rules summarize the output of the TXE pin:

e

1. If TE 0 and TEL GND, then TXE V

CC

e

, then TXE GND

2. If TE 0 and TEL

V

CC

e

3. If TE 1 and OTM and TEL GND, then TXE V

e

CC

, then TXE GND

e

5. If TE 1 and not OTM and TEL GND, then TXE GND

4. If TE 1 and OTM and TEL

V

CC

e

6. If TE 1 and not OTM and TEL

e

V , then TXE V

CC CC

103

6.0 Signal Descriptions (Continued)

PHY PORT INTERFACE

a

The PHY Port Interface consists of I/O signals used to connect the PLAYER device to the Media Access Control (MAC)

sublayer or other PLAYER device. The DP83257 Device has two PHY Port Interfaces. The A Request and A Indicate paths

a

Ð

from one PHY Port Interface and the B Request and B Indicate paths from the second PHY Port Interface. Each path

Ð Ð

consists of an odd parity bit, a control bit, and two 4-bit symbols.

Refer to section 3.3, the Configuration Switch, for more information.

Ý

Symbol Pin

I/O

Description

AIP

6

O

PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit wide Port A

k

l

Indicate signals (AIP, AIC, and AID 7:0 ).

k

l

PHY Port A Indicate Control: A TTL output signal indicating that the two 4-bit symbols (AID 7:4 and

AIC

8

O

k

l

AID 3:0 ) are either control symbols (AIC 1) or data symbols (AIC 0).

e

AID7

AID6

AID5

AID4

10

12

14

18

PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control symbol.

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.

AID3

AID2

AID1

AID0

20

22

24

26

O

PHY Port A Indicate Data: TTL output signals representing the second 4-bit data/control symbol.

AID3 is the most significant bit and AID0 is the least significant bit of the second symbol.

ARP

7

I

PHY Port A Request Parity: A TTL input signal representing odd parity for the 10-bit wide Port A

k

l

Request signals (ARP, ARC, and ARD 7:0 ).

ARC

9

PHY Port A Request Control: A TTL input signal indicating that the two 4-bit symbols

k

l

k

l

e

(ARD 7:4 and ARD 3:0 ) are either control symbols (ARC 1) or data symbols (ARC 0).

PHY Port A Request Data: TTL input signals representing the first 4-bit data/control symbol.

ARD7 is the most significant bit and ARD4 is the least significant bit of the first symbol.

ARD7

ARD6

ARD5

ARD4

11

13

15

19

ARD3

ARD2

ARD1

ARD0

21

23

25

27

I

PHY Port A Request Data: TTL input signals representing the second 4-bit data/control symbol.

ARD3 is the most significant bit and ARD0 is the least significant bit of the second symbol.

BIP

114

O

PHY Port B Indicate Parity: A TTL output signal representing odd parity for the 10-bit wide Port A

k

l

Indicate signals (BIP, BIC, and BID 7:0 ).

k

l

PHY Port B Indicate Control: A TTL output signal indicating that the two 4-bit symbols (BID 7:4 and

BIC

112

k

l

BID 3:0 ) are either control symbols (BIC 1) or data symbols (BIC 0).

e

BID7

BID6

BID5

BID4

110

108

106

102

PHY Port B Indicate Data: TTL output signals representing the first 4-bit data/control symbol.

BID7 is the most significant bit and BID4 is the least significant bit of the first symbol.

BID3

BID2

BID1

BID0

100

98

O

PHY Port B Indicate Data: TTL output signals representing the second 4-bit data/control symbol.

BID3 is the most significant bit and BID0 is the least significant bit of the second symbol.

96

94

BRP

115

I

PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit wide Port A

k

l

Request signals (BRP, BRC, and BRD 7:0 ).

BRC

113

PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols

k

l

k

(BRD 7:4 and BRD 3:0 ) are either control symbols (BRC 1) or data symbols (BRC 0).

l

e

104

6.0 Signal Descriptions (Continued)

Ý

Symbol Pin

I/O

Description

BRD7

BRD6

BRD5

BRD4

111

109

I

PHY Port B Request Data: TTL input signals representing the first 4-bit data/control symbol.

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.

107

103

BRD3

BRD2

BRD1

BRD0

101

99

I

PHY Port B Request Data: TTL input signals representing the second 4-bit data/control symbol.

BRD3 is the most significant bit and BRD0 is the least significant bit of the second symbol.

97

95

105

6.0 Signal Descriptions (Continued)

CONTROL BUS INTERFACE

a

The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMT).

a

The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor or other

controller. It provides access to 64 8-bit internal registers.

a

In the PLAYER device the Control Bus address range has been expanded by 1-bit to 6 bits of address space.

Ý

Symbol Pin

I/O

Description

E

CE

118

I

Control Enable: An active-low, TTL, input signal which enables the Control Bus port for a read or write

k

l

k

cycle. R/ W, CBA 5:0 , CBP, and CBD 7:0 must be valid at the time CE is low.

l

E

Read/ Write: A TTL input signal which indicates a read Control Bus cycle (R/

Control Bus cycle (R/

E

e

W 1), or a write

R/

W

117

I

E

e

0).

W

E

or write cycle. During a read cycle, CBD 7:0 are valid as long as ACK is low ( ACK 0). During a

ACK

120

O

Acknowledge: An active low, TTL, open drain output signal which indicates the completion of a read

l

k

write cycle, a microprocessor must hold CBD 7:0 valid until ACK becomes low. Once ACK is low,

E

e

k

l

it will remain low as long as CE remains low ( CE 0).

E

e

E

INT

119

O

I

Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt condition has

occurred. The Interrupt Condition Register (ICR) should be read in order to find out the source of the

interrupt. Interrupts can be masked through the use of the Interrupt Condition Mask Register (ICMR).

CBA5

CBA4

CBA3

CBA2

CBA1

CBA0

135

134

133

132

129

128

Control Bus Address: TTL input signals used to select the address of the register to be read or written.

CBA5 is the most significant bit (MSB) and CBA0 is the least significant bit (LSB) of the address signals.

CBP

148

I/O Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control Bus data

l

(CBD 7:0 ).

a

E

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

E

During a write cycle, the signal must be valid when CE is low, and must be held valid until ACK

becomes low. If incorrect parity is used during a write cycle, the PLAYER device will inhibit the write

a

cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt Condition Register (ICR).

CBD7

CBD6

CBD5

CBD4

CBD3

CBD2

CBD1

CBD0

147

146

145

144

143

142

141

138

I/O Control Bus Data: Bidirectional, TTL signals containing the data to be read from or written to a register.

a

E

During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.

E

During a write cycle, the signal must be valid when CE is low, and must be held valid until ACK

becomes low.

106

6.0 Signal Descriptions (Continued)

CLOCK INTERFACE

a

The Clock Interface consists of 12.5 MHz and 25 MHz clocks supplied by the PLAYER device as well as reference and

feedback inputs.

Ý

Symbol

LBC1

I/O

Description

4

3

2

1

O

Local Byte Clock: TTL compatible, 12.5 MHz, 50% duty cycle clock outputs which are phase

locked to a crystal oscillator or reference signal. The PH SEL input determines whether the five

phase outputs are phase offset by 8 ns or 16 ns.

LBC2

LBC3

LBC4

LBC5

Ð

160

PH SEL

Ð

34

37

159

5

I

Phase Select: TTL compatible input used to select either a 8 ns or 16 ns phase offset between the 5

local byte clocks (LBC’s). The LBC’s are phase offset 8 ns apart when PH SEL is at a logic LOW

level and 16 ns apart when at a logic HI level.

Ð

FBK IN

Ð

I

Feedback Input: TTL compatible input for use as the PLL’s phase comparator feedback input to

close the Phase Locked Loop. This input is intended to be driven from one of the Local Byte Clocks

a

(LBC’s) from the same PLAYER device.

LSC

O

Local Symbol Clock: TTL compatible 25 MHz output for driving the MACSI or BMAC devices. This

output’s negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and

60% LOW duty cycle.

CLK16

Clock 16/32: TTL compatible clock with a selectable frequency of approximately 15.625 MHz or

31.25 MHz. The frequency can be selected using the Clock Select (CLKSEL) bit of the Mode 2

Register (MODE2).

Note: No glitches appear at the output when switching frequencies.

XTAL IN

Ð

46

I

External Crystal Oscillator Input: This input in conjunction with the XTAL OUT output, is

Ð

designed for use of an external crystal oscillator network as the frequency reference for the clock

generation module’s internal VCO. A diagram of the required circuit, which includes only a 12.5 MHz

crystal and 2 loading capacitors, is shown inFigure 3-19.

This input is selected when the REF SEL input is at a logic LOW level. When not being used, this

Ð

input should be tied to ground.

XTAL OUT

Ð

45

36

O

I

External Crystal Oscillator Output: This output in conjunction with the XTAL IN input, is designed

Ð

for use of an external crystal oscillator network as the frequency reference for the clock generation

module’s internal VCO. A diagram of the required circuit, which includes only a 12.5 MHz crystal and

2 loading capacitors, is shown inFigure 3-19.

REF IN

Ð

Reference Input: TTL compatible input for use as the PLL’s phase comparator reference frequency.

This input is for use in dual attach station or concentrator configurations where there are multiple

a

PLAYER devices at a given site requiring synchronization.

This input is selected when the REF SEL input is at a logic HI level.

Ð

REF SEL

Ð

35

49

I

Reference Select: TTL compatible input which selects either the crystal oscillator inputs XTAL IN

Ð

and XTAL OUT or the REF IN inputs as the reference frequency inputs for the PLL.

Ð Ð

The crystal oscillator inputs are selected when REF SEL is at a logic LOW level and the REF IN

Ð

input is selected as the reference when REF SEL is at a logic HI level.

Ð

LPFLTR

O

Loop Filter: This is a diagnostic output that allows monitoring of the clock generation module’s filter

node. This output is disabled by default and does not need to be connected to any external device. It

can be enabled using the FLTREN bit of the Clock generation module register (CGMREG).

Note: In normal operation this pin should be disabled.

107

6.0 Signal Descriptions (Continued)

MISCELLANEOUS INTERFACE

The Miscellaneous Interface consist of a reset signal, user definable sense signals, and user definable enable signals.

Ý

Symbol Pin

I/O

Description

E

RST

116

I

Reset: An active low, TTL, input signal which clears all registers. The signal must be kept asserted for a

E

a

minimum amount of time. Once the RST signal is asserted, the PLAYER device should be allowed

the specified amount of time to reset internal logic. Note that bit zero of the Mode Register will be set to

zero (i.e. Stop Mode). See section 4.2, Stop Mode of Operation for more information

SP0

63

I

User Definable Sense Pin 0: A TTL input signal from a user defined source. Sense Bit 0 (SB0) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns. Once

the asserted signal is latched, Sense Bit 0 can only be cleared through the Control Bus Interface, even if

the signal is deasserted. This ensures that the Control Bus Interface will record the source of events

which can cause interrupts.

SP1

SP2

65

67

User Definable Sense Pin 1: A TTL input signal from a user defined source. Sense Bit 1 (SB1) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns. Once

the asserted signal is latched, Sense Bit 1 can only be cleared through the Control Bus Interface, even if

the signal is deasserted. This ensures that the Control Bus Interface will record the source of events

which can cause interrupts.

User Definable Sense Pin 2: A TTL input signal from a user defined source. Sense Bit 2 (SB2) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns. Once

the asserted signal is latched, Sense Bit 2 can only be cleared through the Control Bus Interface, even if

the signal is deasserted. This ensures that the Control Bus Interface will record the source of events

which can cause interrupts.

EP0

EP1

64

66

O

User Definable Enable Pin 0: A TTL output signal allowing control of external logic through the Control

Bus Interface. EP0 is asserted/deasserted through Enable Bit 0 (EB0) of the User Definable Register

(UDR). When Enable Bit 0 is set to zero, EP0 is deasserted. When Enable Bit 0 is set to one, EP0 is

asserted.

User Definable Enable Pin 1: A TTL output signal allowing control of external logic through the Control

Bus Interface. EP1 is asserted/deasserted through Enable Bit 1 (EB1) of the User Definable Register

(UDR). When Enable Bit 1 is set to zero, EP1 is deasserted. When Enable Bit 1 is set to one, EP1 is

asserted.

EP2

CS

68

69

O

I

User Definable Enable Pin 2: A TTL output signal allowing control of external logic through the Control

Bus Interface. EP2 is asserted/deasserted through Enable Bit 2 (EB2) of the User Definable Register

(UDR). When Enable Bit 2 is set to zero, EP2 is deasserted. When Enable Bit 2 is set to one, EP2 is

asserted.

a

Cascade Start: A TTL input signal used to synchronize cascaded PLAYER devices in point-to-point

applications.

a

The signal is asserted when all of the cascaded PLAYER devices have the Cascade Mode (CM) bit of

a

the Mode Register (MR) set to one, and all of the Cascade Ready (CR) pins of the cascaded PLAYER

devices have been released.

When Cascade Mode is not being used, this input should be tied to Ground.

For further information, refer to section 4.4, Cascade Mode of Operation.

a

Cascade Ready: An Open Drain output signal used to synchronize cascaded PLAYER devices in

point-to-point applications.

CR

70

O

a

The signal is released (i.e. an Open Drain line is released) when all the cascaded PLAYER devices

have the Cascade Mode (CM) bit of the Mode Register (MR) is set to one and a JK symbol pair has been

received.

When Cascade Mode is not being used, this input should be left Not Connected (N/C).

For further information, refer to section 4.4, Cascade Mode of Operation.

108

6.0 Signal Descriptions (Continued)

POWER AND GROUND

a

All power pins should be connected to a single 5V power supply using the recommended filtering. All ground pins should be

connected to a common 0V ground supply. Bypassing and filtering requirements are given in a separate User Information

Document.

Ý

Symbol

ANALOG

I/O

Description

a

Power: Positive 5V power supply for the PLAYER device’s CGM VCO.

V

CC

32

Ð

a

Ground: Power supply return for the PLAYER device’s CGM VCO.

GND ANALOG

Ð

33

V

CORE

140

139

Power: Positive 5V power supply for the core PLAYER logic gates.

Ground: Power supply return for the core PLAYER logic gates.

CC

Ð

GND CORE

Ð

a

Power: Positive 5V power supply for the PLAYER device’s ECL logic gates.

V

CC

ECL

52, 57,

71, 89

Ð

a

Ground: Power supply return for the PLAYER device’s ECL logic gates.

GND ECL

Ð

58, 72,

88

a

Power: Positive 5V power supply for the PLAYER device’s ESD protection circuitry.

V

ESD

47

48

CC

Ð

a

Ground: Power supply return for the PLAYER device’s ESD protection circuitry.

GND ESD

Ð

V

CC

IO

16, 105,

131, 158

Power: Positive 5V power supply for the input/output buffers.

Ð

GND IO

Ð

17, 104,

130, 157

Ground: Power supply return for the input/output buffers.

SPECIAL CONNECT PINS

These are pins that have special connection requirements.

No Connect (N/C) pins should not be connected to anything. This means not to power, not to ground, and not to each other.

Reserved 0 (RES 0) pins must be connected to ground. These pins are not used to supply device power so they do not need

Ð Ð

to be filtered or bypassed.

Reserved 1 (RES 1) pins must be connected to power. These pins are not used to supply device power so they do not need

Ð Ð

to be filtered or bypassed.

Ý

Symbol

I/O

Description

N/C

38, 39,

No Connect: Pins should not be connected to anything. This means not to power, not

to ground, and not to each other.

40, 41, 42, 43, 44,

79,

80, 81, 87,

121, 122, 123, 124, 125,

126, 127,

149,

150, 151, 152, 153,154,

155, 156

RES

0

1

28, 29,

Reserved 0: Pins must be connected to ground. These pins are not used to supply

device power so they do not need to be filtered or bypassed.

Ð

30, 31,

84, 85, 86,

90, 91, 92, 93,

136

137

Reserved 1: Pins must be connected to power. These pins are not used to supply

device power so they do not need to be filtered or bypassed.

109

7.0 Electrical Characteristics

7.1 ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Supply Voltage

Input Voltage

Conditions

Min

Typ

Max

7.0

a

Units

b

V

CC

0.5

V

b

DC

V

0.5

IN

CC

a

CC

Output Voltage

OUT

V

ESD to other V

CC

Ð

Maximum Voltage

Differential

0.3

V

b

Storage Temperature

Signal Output Current

ESD Protection

65

150

C

§

b

ECL

50

mA

2000

V

7.2 RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Supply Voltage

Conditions

Min

Typ

Max

5.25

70

Units

V

T

4.75

0

V

CC

Operating Temperature

C

§

A

a

FREF

Reference Input Frequency

12.5–50 ppm

12.5

50 ppm

MHz

7.3 RECOMMENDED EXTERNAL COMPONENTS

Symbol

Parameter

Crystal Specifications

Center Frequency

Frequency Calibration

Frequency Stability

Aging

Conditions

Min

Typ

Max

Units

XTAL

12.5

MHz

ppm

mF

b

10

5

Over Temperature

Less Than

b

5

Recommended Power Supply Bypassing Capacitor Value

0.1

Note: Capacitors should be placed between each supply pair as close to the

device as possible.

7.4 DC ELECTRICAL CHARACTERISTICS

The DC characteristics are specified over the Recommended Operating Conditions, unless otherwise specified.

DC Electrical Characteristics for All TTL-Compatible Inputs

The following signals are covered: PHY Port Request Signals (ARD, ARC, ARP, BRD, BRC, BRP), Phase Select (PH SEL),

Ð

Reference Select (REF SEL), Sense Pins (SP), Cascade Start (CS), PMD Transmitter Enable Level (TEL), Device Reset

Ð

E

E E

RST), and Control Bus Interface Inputs (R/ W, CE, CBA).

(

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

Input High Voltage

Input Low Voltage

Input Clamp Voltage

Input Low Current

Input High Current

2.0

IH

0.8

V

IL

e b

IN

b

1.5

I

18 mA

V

IC

e

b

a

I

V

GND

10

mA

IL

IH

IN

V

CC

110

7.0 Electrical Characteristics (Continued)

DC Electrical Characteristics for All TTL-Compatible Non-TRI-STATE Outputs

The following signals are covered: Clock 16/32 (CLK16), Enable Pins (EP), and PMD Transmitter Enable (TXE).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e b

b

V

Output High Voltage

Output Low Voltage

I

2 mA

V

CC

0.5

V

OH

e

4 mA

0.5

OL

DC Electrical Characteristics for All TTL-Compatible TRI-STATE Outputs

The following signals are covered: PHY Port Indicate Signals (AID, AIC, AIP, BID, BIC, BIP).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

e b

b

V

Output High Voltage

Output Low Voltage

TRI-STATE Leakage

I

2 mA

V

CC

0.5

OH

e

4 mA

0.5

60

V

OL

e

(Note 1)

I

V

mA

OZ3

OUT

CC

e

b

500

I

TRI-STATE Leakage

V

mA

OZ4

OUT

(Note 1)

GND

Note 1: Output buffer has a p-channel pullup device.

DC Electrical Characteristics for All TTL-Compatible Input/Outputs

The following signals are covered: Control Bus Interface I/O (CBD, CBP).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

Input High Voltage

Input Low Voltage

Input Clamp Voltage

Input Low Current

Input High Current

Output High Voltage

Output Low Voltage

TRI-STATE Leakage

2.0

IH

0.8

V

IL

e b

IN

b

1.5

I

18 mA

V

IC

e

b

a

I

V

GND

10

mA

V

IL

IH

IN

V

CC

e b

b

V

I

2 mA

4 mA

V

CC

0.5

OH

OL

OH

OL

e

V

I

0.5

10

V

e

I

V

mA

OZ1

OZ2

OUT

CC

b

V

10

GND

111

7.0 Electrical Characteristics (Continued)

DC Electrical Characteristics for All FDDI Clock Outputs

The following signals are covered: Local Byte Clocks (LBC1–LBC5), and Local Symbol Clock (LSC).

These outputs are designed to drive capacitive loads from 20 pF to 60 pF.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e b

b

2

V

Output High Voltage

Output Low Voltage

I

400 mA

V

CC

V

OH

e

8 mA

0.5

OL

DC Electrical Characteristics for All Clock Reference Inputs

The following signals are covered: Reference In (REF IN) and Feedback In (FBK IN).

Ð Ð

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

Input High Voltage

Input Low Voltage

Input Clamp Voltage

Input Low Current

Input High Current

2.0

V

IH

0.8

IL

e b

IN

b

1.5

I

18 mA

V

IC

e

b

a

I

V

GND

10

mA

IL

IH

IN

V

CC

DC Electrical Characteristics for Crystal Inputs and Outputs

The following signals are covered: Crystal In (XTAL IN) and Crystal Out (XTAL OUT).

Ð Ð

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e

I

Output Low Current

V

1V

4

mA

OL

OUT

(Note A)

e

b

4

I

Output High Current

Small Signal Gain

V

1V

mA

OH

OUT

(Note A)

CC

e

XTAL IN

Ð

100 mV

45

Centered about V

(Note A)

TH

V

TH

Input Threshold

Voltage

(Note A)

2.2

7.0

V

XTAL IN to

Ð

XTAL OUT Delay

(Note A)

ns

Ð

Output Impedance

(Note A)

270

10

X

Internal Resistor

Variation

kX

Note A: This parameter is presented as a typical value to provide enough information to design an appropriate crystal network.

DC Electrical Characteristics for All Open Drain Outputs

E

The following signals are covered: Interrupt ( INT), Acknowledge ( ACK), and Cascade Ready (CR).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

e

V

OL

Output Low Voltage

TRI-STATE Leakage

I

8 mA

0.5

10

OL

e

I

V

OUT

V

CC

mA

OZ

112

7.0 Electrical Characteristics (Continued)

DC Electrical Characteristics for All 100K ECL Compatible Inputs

The following signals are covered: PMD Indicate Data (PMID), Receive Clock In (RXC IN), Receive Data In (RXD IN), and

Ð

Signal Detect (SD).

Symbol

Parameter

Conditions

(Note 1)

Min

150

b

Typ

Max

Units

mV

V

Input Voltage Differential

Common Mode Voltage

DIFF

e

(Notes 1, 2)

b

V

DIFF

300 mV

V

CC

2.0

V

CC

0.5

CM

e

b

200

I

Input Current

V

IN

V or GND

CC

200

mA

IN

Note 1: Both inputs of each differential pair are tested together. These specifications guarantee that the inputs are compatible with standard 100K ECL voltage

level outputs.

Note 2: V

is measured from the crossover point of the 300 mV differential test input.

CM

DC Electrical Characteristics for 100K ECL Compatible Outputs

The following signals are covered: PMD Request Data (PMRD) and Transmit Clock (TXC).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e

b

V

Output High Voltage

Output Low Voltage

V

1.810

0.880

V

1.025

1.810

V

0.880

1.620

V

OH

IL

CC

V

IH

CC

OL

CC

DC Electrical Characteristics for Alternate PMD ECL Outputs

The following signals are covered: Receive Clock Out (RXC OUT) and Receive Data Out (RXD OUT).

Ð Ð

Symbol

Parameter

Conditions

Min

Typ

Max

Units

e

b

V

Output High Voltage

Output Low Voltage

V

1.810

0.880

V

1.155

1.810

V

0.880

1.550

V

OH

IL

CC

V

IH

CC

OL

CC

(Note 3)

a

b

a

Note 3: It is recommended that RXC OUT and RXC OUT always be used together as a differential pair. It is recommended that RXD OUT and

Ð Ð

RXD OUT always be used together as a differential pair.

Ð

b

Ð

Supply Current Electrical Characteristics

Symbol

Parameter

Total Supply

Conditions

Min

Typ

Max

Units

mA

e

I

LBC1

12.5 MHz

350*

CC

ECL

I

ECL Supply Current

200*

20*

mA

CC

Ð

ANALOG

I

ANALOG Supply Current

mA

CC

Ð

a

*Note: The PLAYER device has multiple pairs of differential ECL outputs that need to be terminated. The additional current needed for this termination is not

a

included in the PLAYER ’s total supply current, but can be calculated as follows:

e

b

V

max

V

0.88V

1.62V

OH

CC

Ð

max

V

OL

Ð

CC

b

2V, therefore the external load current

Since the outputs are differential, the average output level is V

1.25V. The test load per output is 50X at V

CC

through the 50X resistor is:

e

b

0.015A

15 mA

b

2) /50

CC

[

]

I

(V

1.25)

(V

LOAD

CC

As a result, the termination for each pair of active ECL outputs typically consumes 30 mA, time averaged.

113

7.0 Electrical Characteristics (Continued)

7.5 AC ELECTRICAL CHARACTERISTICS

The AC Electrical characteristics are specified over the Recommended Operating Conditions, unless otherwise specified.

AC Characteristics for the Control Bus Interface

E

The following signals are covered: Control Bus Interface (R/ W, CE, INT, ACK, CBA, CBD, and CBP).

E

Symbol

T1

Descriptions

Min

15

Max

Units

ns

CE Setup to LBC

LBC Period

T2

80

T3

LBC1 to ACK Low

CE Low to ACK Low

45

540

60

T4

290

T5

LBC1 Low to CBD(7–0) and CBP Valid

LBC1 to CBD(7–0) and CBP Active

CE Low to CBD(7–0) and CBP Active

CE Low to CBD(7–0) and CBP Valid

LBC Pulse Width High

T6

5

T7

225

265

35

475

515

45

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20a

T20b

T20c

T21

T22

LBC Pulse Width Low

35

45

CE High to ACK High

45

R/W, CBA(5–0), CBD(7–0) and CBP Setup to CE Low

CE High to R/W, CBA(5–0), CBD(7–0) and CBP Hold Time

R/W, CBA(5–0), CBD(7–0) and CBP to LBC1 Setup Time

ACK Low to CE High Lead Time

CE Minimum Pulse Width High

CE High to CBD(7–0) and CBP TRI-STATE

ACK High to CE Low

5

0

20

0

20

55

0

CBD(7–0) Valid to ACK Low Setup

LBC1 to R/W Hold Time

20

10

20

LBC1 to CBA Hold Time

LBC1 to CBD and CBP Hold Time

LBC1 to INT Low

55

25

LBC1 to EP Change

5

Asynchronous Definitions

a

T4 (min)

T4 (max)

T7 (min)

T7 (max)

T8 (min)

T8 (max)

T1

(3 * T2)

(6 * T2)

(2 * T2)

(5 * T2)

(2 * T2)

(5 * T2)

T3

T6

T9

T1

a

T5

e

T10 40 ns.

Note: Min/Max numbers are based on T2

80 ns and T9

114

7.0 Electrical Characteristics (Continued)

TL/F/11708–29

FIGURE 7-1. Asynchronous Control Bus Write Cycle Timing

TL/F/11708–30

FIGURE 7-2. Asynchronous Control Bus Read Cycle Timing

115

7.0 Electrical Characteristics (Continued)

TL/F/11708–31

FIGURE 7-3. Control Bus Synchronous Writes

TL/F/11708–32

FIGURE 7-4. Control Bus Synchronous Reads

TL/F/11708–50

FIGURE 7-5. Control Bus Interrupt Timing

116

7.0 Electrical Characteristics (Continued)

AC Characteristics for the Clock Interface Signals (Timing and Relationships)

Symbol

Parameter

Conditions

Min

5.0

Typ

8

Max

11.0

19.0

27.0

35.0

Units

ns

e

T

LBC1–LBC2 Timing

LBC1–LBC3 Timing

LBC1–LBC4 Timing

LBC1–LBC5 Timing

PH SEL

Ð

LOW

Phase1

Phase2

Phase3

Phase4

PH SEL

Ð

13.0

21.0

29.0

16

24

32

ns

PH SEL

Ð

ns

PH SEL

Ð

ns

e

T

LBC1–LBC2 Timing

LBC1–LBC3 Timing

LBC1–LBC4 Timing

LBC1–LBC5 Timing

PH SEL

Ð

HIGH

45.0

13.0

61.0

29.0

5.0

48

16

64

32

8

51.0

19.0

67.0

35.0

12.0

ns

Phase1

Phase2

Phase3

Phase4

Phase5

PH SEL

Ð

PH SEL

Ð

PH SEL

Ð

e

LBC5 Rising-

PH SEL

Ð

PH SEL

LOW or

HIGH

LBC1 Falling Timing

Ð

b

a

T23

T24

LSC Falling to LBC1

REF IN to FBK IN

(Note 1)

In Lock

3

2

6

2

ns

Ð

Note 1: LSC loading must always be less than or equal to LBC1 loading.

TL/F/11708–33

FIGURE 7-6. Clock Signal Relationships

117

7.0 Electrical Characteristics (Continued)

TL/F/11708–51

FIGURE 7-7. Typical Clock Signal Relationships Based on Phase Select (PH SEL) Setting

Ð

118

7.0 Electrical Characteristics (Continued)

AC Characteristics for the Clock Interface Signals (Periods and Pulse Widths)

Symbol

T2

Parameter

LBC Period

Conditions

Min

Typ

Max

Units

ns

80

T9

LBC Pulse Width High

LBC Pulse Width Low

35

45

ns

T10

ns

T25

T26

LSC Pulse Width High

LSC Pulse Width Low

12

21

19

28

ns

e

T27

T28

CLK16 Period

MODE2.CLKSEL

0

64

32

ns

CLK16 Pulse Width

MODE2.CLKSEL

(Note 1)

27

37

e

T27

T28

CLK16 Period

MODE2.CLKSEL

1

32

16

ns

CLK16 Pulse Width

MODE2.CLKSEL

(Note 1)

11

35

21

45

T29

REF IN Pulse Width High

Ð

ns

Note 1: This parameter is not tested, but is assured by correlation with characterization data.

TL/F/11708–34

FIGURE 7-8. Clock Pulse Widths

AC Characteristics for Port A Interface and Port B Interface

The following signals are covered: PHY Port A (AID, AIP, AIC, ARD, ARP, ARC) and PHY Port B (BID, BIP, BIC, BRD, BRP,

BRC).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T30

LBC1 to Indicate Data Changes from

TRI-STATE to Valid Data

70

ns

T31

LBC1 to Indicate Data Changes from

Active to TRI-STATE

70

45

ns

T32

T33

T34

T35

LBC1 to Indicate Data Sustain

LBC1 to Valid Indicate Data

9

ns

Request Data to LBC1 Setup Time

Request Data to LBC1 Hold Time

15

3

TL/F/11708–35

FIGURE 7-9. PHY Port Interface Timing

119

7.0 Electrical Characteristics (Continued)

AC Characteristics for the PMD Interface

The following signals are covered: PMD Indicate Data (PMID), Signal Detect (SD), and PMD Request Data (PMRD).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

g

PMID to PMRD Latency

T36

Looped Back through

Configuration Switch.

5

LBC

Cycles

e

LBC1

12.5 MHz

In Lock

(Note 1)

T37

T38

T39

SD Minimum Pulse Width

PMRD Rise Time

120

ns

(Note 2)

1.5

PMRD Fall Time

e

Note 1: This only applies when the Alternate PMD Interface is disabled, APMDREG.APMDEN

Note 2: This parameter is not tested, but is assured by correlation with characterization data.

0.

TL/F/11708–36

FIGURE 7-10. Primary PMD Timing Diagrams

120

7.0 Electrical Characteristics (Continued)

AC Characteristics for the Alternate PMD Interface

The following input signals are covered: PMD Indicate Data (PMID), Signal Detect (SD), Receive Data In (RXD IN), Receive

Ð

Clock In (RXC IN).

Ð

The following output signals are covered: PMD Request Data (PMRD), Transmit Clock (TXC), Recovered Data Out

(RXD OUT), Recovered Clock Out (RXC OUT).

Ð Ð

Note: The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYER Device and the 100 pin DP83256-AP Device. The Transmit Clock is

a

enabled by the CGMREG.TXCE bit. The rest of the Alternate PMD Interface is enabled by the APMDREG.APMDEN bit.

Symbol

T40

Parameter

Conditions

Min

Typ

Max

Units

ns

a

RXC OUT to RXD OUT Change Time

g

1.0

5.0

Ð

g

PMID to RXD OUT Latency

T41

In Lock

16

ns

Ð

a

RXD IN to RXC IN Setup Time

g

T42

4.0

0.5

4.0

ns

Ð

a

RXD IN to RXC IN Hold Time

g

T43

ns

Ð

a

TXC to PMRD Change Time

g

T44

7.0

ns

T42

SD Minimum Pulse Width

120

3.5

ns

g

RXC OUT Pulse Width High

T45

T46

T47

T48

T49

T50

T51

T52

T38

T39

(Note 1)

4.5

1.5

4.5

1.5

ns

Ð

g

RXC OUT Rise Time

Ð

g

RXC OUT Fall Time

Ð

g

RXD OUT Rise Time

Ð

g

RXD OUT Fall Time

Ð

g

TXC Pulse Width High

3.5

g

TXC Rise Time

g

TXC Fall Time

PMRD Rise Time

PMRD Fall Time

Note 1: This parameter is not tested, but is assured by correlation with characterization data.

TL/F/11708–52

FIGURE 7-11. ECL Rise and Fall Times

121

7.0 Electrical Characteristics (Continued)

TL/F/11708–53

FIGURE 7-12. Alternate PMD Timing Diagrams

122

7.0 Electrical Characteristics (Continued)

AC Characteristics for the PMD Interface Inputs (ANSI Specifications)

The following input signals are covered: PMD Indicate Data (PMID), Receive Data In (RXD IN), Receive Clock In (RXC IN).

a

enabled by the CGMREG.TXCE bit. The rest of the Alternate PMD Interface is enabled by the APMDREG.APMDEN bit.

Ð Ð

Note: The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYER Device and the 100 pin DP83256-AP Device. The Transmit Clock is

All comments in square brackets are section references to the ANSI documents where these specifications can be found.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

b

[

]

T53

CRM Window Recognition Region

(PMID Inputs)

PMD E.2

3

ns

b

]

T54

T55

PMID Receive Clock Tolerance

(Lock Acquisition Range)

PHY 5.2.4

100

ppm

Receive Clock Acquisition Time

From 1st Data

and SD Active

ms

[

]

PHY 5.2.6

T56

Receive Clock Acquisition Time

From Line State

Change

15

ms

[

]

PHY 5.2.6

TL/F/11708–54

TL/F/11708–55

FIGURE 7-13. Alternate PMD Input Timing DiagramsÐANSI Specifications

123

7.0 Electrical Characteristics (Continued)

AC Characteristics for the PMD Interface Outputs (ANSI Specifications)

The following output signals are covered: PMD Request Data (PMRD), Transmit Clock (TXC), Recovered Data Out

(RXD OUT), Recovered Clock Out (RXC OUT).

Ð Ð

Note: The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYER Device and the 100 pin DP83256-AP Device. The Transmit Clock is

a

enabled by the CGMREG.TXCE bit. The rest of the Alternate PMD Interface is enabled by the APMDREG.APMDEN bit.

Comments in square brackets are section references to the ANSI documents where these specifications can be found.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T57

PMRD Total Transmit Jitter

(Note 1)

0.72

ns p-p

a

[

Duty Cycle Distortion (DCD)

Data Dependent Jitter (DDJ)

[

]

PMD 8.1

]

Random Jitter (RJ)

T58

Total Recovered Clock (RXC OUT) Jitter

a

(Note 1)

2.5

ns p-p

Ð

Static Alignment Error Accuracy (SAE)

[

Clock Data Dependent Jitter (C DDJ)

[

]

PMD E.2

a

Ð

]

Random Jitter (C RJ)

Ð

Note 1: This parameter is not tested, but is assured through characterization data and periodic testing of sample units.

124

7.0 Electrical Characteristics (Continued)

AC Characteristics for User Definable Pins

The following signals are covered: Sense Pins (SP).

For Enable Pins (EP) timing see AC Characteristics for the Control Bus Interface.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

T59

SP Minimum Pulse Width

120

ns

TL/F/11708–56

FIGURE 7-14. SP Minimum Pulse Width

AC Characteristics for Miscellaneous Interface

E

The following signal is covered: Reset ( RST).

Symbol

T60

Parameter

Conditions

Min

300

Typ

Max

Units

E

Minimum Reset ( RST) Pulse Width

ns

ms

T61

Maximum Power Up Reset Cycle Duration

(Notes 1, 2)

10

E

Maximum Hardware Reset ( RST) Cycle Duration

T62

0.5

Note 1: This parameter is not tested, but is assured by correlation with characterization data.

Note 2: User must wait this long before trying to access the device after power up. It is recommended that a Hardware Reset be used sometime after the Power Up

Reset cycle is complete to insure proper device reset.

TL/F/11708–57

FIGURE 7-15. Reset Timing

125

7.0 Electrical Characteristics (Continued)

AC TEST CIRCUITS

TL/F/11708–37

Note: S is closed for T

1

and T

PZL

PLZ

S

is closed for T

2

1

PZH

PHZ

and S are open otherwise

2

FIGURE 7-16. Switching Test Circuit for All TRI-STATE Output Signals

TL/F/11708–38

FIGURE 7-17. Switching Test Circuit for All TTL Output Signals

TL/F/11708–39

FIGURE 7-18. Switching Test Circuit for All Open Drain Output Signals (INT, ACK, and CR)

TL/F/11708–40

FIGURE 7-19. Switching Test Circuit for All ECL Input and Output Signals

126

7.0 Electrical Characteristics (Continued)

TEST WAVEFORMS

TL/F/11708–41

FIGURE 7-20. ECL Output Test Waveform

TL/F/11708–42

Note: All CMOS Inputs and outputs are TTL compatible.

FIGURE 7-21. TTL Output Test Waveform

TL/F/11708–43

FIGURE 7-22. TRI-STATE Output Test Waveform

127

8.0 Connection Diagrams

8.1 DP83256VF CONNECTION DIAGRAM

For a Pinout Summary List, refer to Table 8-1.

TL/F/11708–44

FIGURE 8-1. DP83256VF 100-Pin JEDEC Metric PQFP Pinout

128

8.0 Connection Diagrams (Continued)

TABLE 8-1. DP83256 100-Pin PQFP Pinout Summary

Pin No.

1

Signal Name

Local Byte Clock 4

Local Byte Clock 3

Local Byte Clock 2

Local Byte Clock 1

Clock 16/32

Symbol

LBC4

LBC3

LBC2

LBC1

CLK16

AIP

I/O

O

Pin Type

TTL

2

TTL

3

TTL

4

TTL

5

TTL

6

PHY Port A Indicate Parity

PHY Port A Indicate Control

TTL

7

AIC

TTL

k

l

8

PHY Port A Indicate Data

I/O Power

7

6

5

AID7

AID6

AID5

TTL

9

TTL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

TTL

a

V

CC

IO

5V

0V

Ð

I/O Ground

GND IO

Ð

k

l

PHY Port A Indicate Data

4

3

2

1

0

AID4

AID3

AID2

AID1

AID0

O

TTL

a

Reserved

0

RES

0

0V

5V

0 V

Ð

ANALOG Power

ANALOG Ground

Phase Select

Reference Select

Reference Input

Feedback Input

Crystal Output

Crystal Input

V

ANALOG

CC

Ð

a

GND ANALOG

Ð

PH SEL

Ð

I

TTL

REF SEL

Ð

REF IN

Ð

I

FBK IN

Ð

I

XTAL OUT

Ð

O

I

XTAL IN

Ð

a

ESD Power

V

CC

ESD

5V

0V

Ð

ESD Ground

GND ESD

Ð

Loop Filter

LPFLTR

O

a

ECL Power

V

CC

ECL

5V

Ð

b

a

b

a

PMD Request Data

ECL Power

PMRD

O

ECL

a

V

CC

ECL

5V

0V

Ð

ECL Ground

GND ECL

Ð

b

a

b

a

Signal Detect

SD

I

ECL

b

PMID

PMD Indicate Data

129

8.0 Connection Diagrams (Continued)

TABLE 8-1. DP83256 100-Pin PQFP Pinout Summary (Continued)

Pin No.

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

Signal Name

Symbol

I/O

Pin Type

ECL

a

PMD Indicate Data

Sense Pin 0

Enable Pin 0

Sense Pin 1

Enable Pin 1

ECL Power

PMID

I

SP0

EP0

SP1

EP1

TTL

O

I

TTL

O

TTL

a

V

CC

ECL

5V

0V

Ð

ECL Ground

GND ECL

Ð

PMD Transmitter Enable

TXE

TEL

O

I

TTL

PMD Transmitter Enable Level

a

Reserved

0

RES

0

0V

Ð

No Connect

N/C

a

Reserved

Ð

0

RES

0

0V

Ð

Reserved

Ð

Reserved

Ð

Reserved

Ð

No Connect

N/C

GND ECL

a

ECL Ground

ECL Power

0V

5V

0V

Ð

V

CC

ECL

Ð

Reserved

0

RES

0

Ð

0

Ð

k

l

PHY Port B Request Data

I/O Ground

0

1

2

3

4

BRD0

BRD1

BRD2

BRD3

BRD4

I

TTL

a

GND IO

Ð

0V

5V

I/O Power

V IO

CC

Ð

k

l

PHY Port B Request Data

5

6

7

BRD5

BRD6

BRD7

BRC

I

TTL

I

TTL

PHY Port B Request Control

PHY Port B Request Parity

I

TTL

BRP

O

I

TTL

E

Device Reset

RST

TTL

E

Read/ Write

E

R/

E

W

I

TTL

Chip Enable

CE

I

TTL

E

Interrupt

INT

O

I

Open Drain

TTL

E

ACK

Acknowledge

k

l

Control Bus Address

0

CBA0

130

8.0 Connection Diagrams (Continued)

TABLE 8-1. DP83256 100-Pin PQFP Pinout Summary (Continued)

Pin No.

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Signal Name

Control Bus Address

I/O Logic Ground

Symbol

I/O

Pin Type

k

l

1

CBA1

I

TTL

a

GND IO

Ð

0V

5V

I/O Logic Power

V IO

CC

Ð

k

l

Control Bus Address

2

3

4

5

CBA2

CBA3

CBA4

CBA5

I

TTL

a

Reserved

0

1

RES

0

1

0V

5V

Ð

k

l

Control Bus Data

Core Ground

0

CBD0

I/O

TTL

a

GND CORE

Ð

0V

5V

Core Power

V

CORE

Ð

CC

k

l

Control Bus Data

1

2

3

4

5

6

7

CBD1

CBD2

CBD3

CBD4

CBD5

CBD6

CBD7

CBP

I/O

TTL

Control Bus Data Parity

I/O Ground

a

GND IO

Ð

0V

5V

I/O Power

V IO

CC

Ð

Local Symbol Clock

Local Byte Clock5

LSC

O

TTL

LBC5

131

8.0 Connection Diagrams (Continued)

8.2 DP83256VF-AP CONNECTION DIAGRAM

For a Pinout Summary List, refer to Table 8-2.

TL/F/11708–58

FIGURE 8-2. DP83256VF-AP 100-Pin JEDEC Metric PQFP Pinout

132

8.0 Connection Diagrams (Continued)

TABLE 8-2. DP83256VF-AP 100-Pin PQFP Pinout Summary

Pin No.

1

Signal Name

Local Byte Clock 4

Local Byte Clock 3

Local Byte Clock 2

Local Byte Clock 1

Clock 16/32

Symbol

LBC4

LBC3

LBC2

LBC1

CLK16

AIP

I/O

O

Pin Type

TTL

2

TTL

3

TTL

4

TTL

5

TTL

6

PHY Port A Indicate Parity

PHY Port A Indicate Control

TTL

7

AIC

TTL

k

l

8

PHY Port A Indicate Data

I/O Power

7

6

5

AID7

AID6

AID5

TTL

9

TTL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

TTL

a

V

CC

IO

5V

0V

Ð

I/O Ground

GND IO

Ð

k

l

PHY Port A Indicate Data

4

3

2

1

0

AID4

AID3

AID2

AID1

AID0

O

TTL

a

Reserved

0

RES

0

0V

5V

0 V

Ð

ANALOG Power

ANALOG Ground

Phase Select

V

ANALOG

CC

Ð

a

GND ANALOG

Ð

PH SEL

Ð

I

TTL

Reference Select

Reference Input

Feedback Input

Crystal Output

Crystal Input

REF SEL

Ð

REF IN

Ð

I

FBK IN

Ð

I

XTAL OUT

Ð

O

I

XTAL IN

Ð

a

ESD Power

V

CC

ESD

5V

0V

Ð

ESD Ground

GND ESD

Ð

b

a

b

Transmit Clock

ECL Power

TXC

O

ECL

a

5V

V

CC

ECL

Ð

b

a

b

a

PMD Request Data

PMRD

O

ECL

b

a

Receive Clock Out

ECL Power

RXC OUT

Ð

a

RXC OUT

Ð

a

V

CC

ECL

5V

0V

Ð

ECL Ground

GND ECL

Ð

133

8.0 Connection Diagrams (Continued)

TABLE 8-2. DP83256VF-AP 100-Pin PQFP Pinout Summary (Continued)

Pin No.

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

Signal Name

Symbol

I/O

Pin Type

ECL

b

a

b

a

Signal Detect

SD

I

ECL

b

a

b

a

PMD Indicate Data

PMD Indicate Date

Enable Pin 0

PMID

I

ECL

I

ECL

EP0

EP1

O

TTL

Enable Pin 1

TTL

a

ECL Power

V

CC

ECL

5V

0V

Ð

ECL Ground

GND ECL

Ð

b

a

b

a

b

a

Receive Clock In

RXC IN

Ð

I

ECL

RXC IN

Ð

b

Receive Data In

RXD IN

Ð

I

a

RXD IN

Ð

I

b

a

b

a

Receive Data Out

No Connect

RXD OUT

Ð

O

RXD OUT

Ð

N/C

No Connect

a

ECL Ground

GND ECL

Ð

0V

5V

0V

ECL Power

V

CC

ECL

Ð

Reserved

0

RES

0

Ð

0

Ð

k

l

PHY Port B Request Data

I/O Ground

0

1

2

3

4

BRD0

BRD1

BRD2

BRD3

BRD4

I

TTL

a

GND IO

Ð

0V

5V

I/O Power

V IO

CC

Ð

k

l

PHY Port B Request Data

5

6

7

BRD5

BRD6

BRD7

BRC

I

TTL

I

TTL

PHY Port B Request Control

PHY Port B Request Parity

I

TTL

BRP

O

I

TTL

E

Device Reset

RST

TTL

E

Read/ Write

E

R/

E

W

I

TTL

Chip Enable

CE

I

TTL

E

Interrupt

INT

O

I

Open Drain

TTL

E

ACK

Acknowledge

k

l

Control Bus Address

0

CBA0

134

8.0 Connection Diagrams (Continued)

TABLE 8-2. DP83256VF-AP 100-Pin PQFP Pinout Summary (Continued)

Pin No.

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Signal Name

Control Bus Address

I/O Logic Ground

Symbol

I/O

Pin Type

k

l

1

CBA1

I

TTL

a

GND IO

Ð

0V

5V

I/O Logic Power

V IO

CC

Ð

k

l

Control Bus Address

2

3

4

5

CBA2

CBA3

CBA4

CBA5

I

TTL

a

Reserved

0

1

RES

0

1

0V

5V

Ð

k

l

Control Bus Data

Core Ground

0

CBD0

I/O

TTL

a

GND CORE

Ð

0V

5V

Core Power

V

CORE

Ð

CC

k

l

Control Bus Data

1

2

3

4

5

6

7

CBD1

CBD2

CBD3

CBD4

CBD5

CBD6

CBD7

CBP

I/O

TTL

Control Bus Data Parity

I/O Ground

a

GND IO

Ð

0V

5V

I/O Power

V IO

CC

Ð

Local Symbol Clock

Local Byte Clock5

LSC

O

TTL

LBC5

135

8.0 Connection Diagrams (Continued)

8.3 DP83257VF CONNECTION DIAGRAM

For a Pinout Summary List, refer to Table 8-3.

TL/F/11708–45

FIGURE 8-3. DP83257VF 160-Pin JEDEC Metric PQFP Pinout

136

8.0 Connection Diagrams (Continued)

TABLE 8-3. DP83257 160-Pin PQFP Pinout Summary

Pin No.

1

Signal Name

Local Byte Clock 4

Symbol

LBC4

LBC3

LBC2

LBC1

CLK16

AIP

I/O

O

I

Pin Type

TTL

2

Local Byte Clock 3

3

Local Byte Clock 2

4

Local Byte Clock 1

5

Clock 16/32

6

PHY Port A Indicate Parity

PHY Port A Request Parity

PHY Port A Indicate Control

PHY Port A Request Control

7

ARP

8

AIC

O

I

9

ARC

k

l

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

PHY Port A Indicate Data

7

AID7

ARD7

AID6

ARD6

AID5

ARD5

O

I

k

l

PHY Port A Request Data

7

k

l

PHY Port A Indicate Data

6

O

I

k

l

PHY Port A Request Data

6

k

l

PHY Port A Indicate Data

PHY Port A Request Data

I/O Power

5

O

I

k

l

5

a

V

CC

IO

5V

0V

Ð

I/O Ground

GND IO

Ð

k

l

PHY Port A Indicate Data

PHY Port A Request Data

4

AID4

ARD4

AID3

O

I

TTL

k

l

4

k

l

PHY Port A Indicate Data

PHY Port A Request Data

3

O

I

k

l

3

ARD3

AID2

k

l

PHY Port A Indicate Data

PHY Port A Request Data

2

O

I

k

l

2

ARD2

AID1

k

l

PHY Port A Indicate Data

1

O

I

k

l

PHY Port A Request Data

1

ARD1

AID0

k

l

PHY Port A Indicate Data

0

O

I

k

l

PHY Port A Request Data

0

ARD0

a

Reserved

0

RES

0

0V

5V

0V

Ð

ANALOG Power

ANALOG Ground

Phase Select

V

ANALOG

CC

Ð

GND ANALOG

Ð

PH SEL

Ð

I

TTL

Reference Select

Reference Input

Feedback Input

No Connect

REF SEL

Ð

REF IN

Ð

FBK IN

Ð

N/C

137

8.0 Connection Diagrams (Continued)

TABLE 8-3. DP83257 160-Pin PQFP Pinout Summary (Continued)

Pin No.

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

Signal Name

No Connect

Symbol

N/C

I/O

Pin Type

No Connect

Crystal Output

Crystal Input

ESD Power

ESD Ground

Loop Filter

N/C

XTAL OUT

Ð

O

I

XTAL IN

Ð

a

V

CC

ESD

5V

0V

Ð

GND ESD

Ð

LPFLTR

O

b

a

b

Transmit Clock

ECL Power

TXC

ECL

a

5V

V

CC

ECL

Ð

b

a

PMD Request Data

PMRD

O

ECL

a

b

a

Receive Clock Out

ECL Power

RXC OUT

Ð

a

RXC OUT

Ð

a

V

CC

ECL

5V

0V

Ð

ECL Ground

GND ECL

Ð

b

a

b

a

Signal Detect

SD

I

ECL

b

a

b

a

PMD Indicate Data

Sense Pin 0

PMID

I

ECL

I

ECL

SP0

EP0

SP1

EP1

SP2

EP2

CS

I

TTL

Enable Pin 0

Sense Pin 1

O

I

TTL

Enable Pin 1

Sense Pin 2

O

I

TTL

Enable Pin 2

Cascade Start

Cascade Ready

ECL Power

O

I

TTL

CR

O

Open Drain

a

V

CC

ECL

5V

0V

Ð

ECL Ground

GND ECL

Ð

PMD Transmitter Enable

TXE

TEL

O

I

TTL

ECL

PMD Transmitter Enable Level

b

a

b

a

Receive Clock In

RXC IN

Ð

I

RXC IN

Ð

I

138

8.0 Connection Diagrams (Continued)

TABLE 8-3. DP83257 160-Pin PQFP Pinout Summary (Continued)

Pin No.

77

Signal Name

Symbol

I/O

Pin Type

ECL

b

a

b

Receive Data In

No Connect

RXD IN

Ð

I

a

78

RXD IN

Ð

ECL

79

N/C

80

No Connect

81

No Connect

b

a

82

Receive Data Out

RXD OUT

Ð

O

ECL

a

83

RXD OUT

Ð

a

84

Reserved

0

RES

0

0V

Ð

85

86

87

No Connect

N/C

GND ECL

a

88

ECL Ground

ECL Power

0V

5V

0V

Ð

89

V

CC

ECL

Ð

90

Reserved

0

RES

0

Ð

91

0

Ð

92

0

Ð

93

0

Ð

k

l

94

PHY Port B Indicate Data

PHY Port B Request Data

0

BID0

O

I

TTL

k

l

95

0

BRD0

BID1

k

l

96

PHY Port B Indicate Data

PHY Port B Request Data

1

O

I

k

l

97

1

BRD1

BID2

k

l

98

PHY Port B Indicate Data

PHY Port B Request Data

2

O

I

k

l

99

2

BRD2

BID3

k

l

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

PHY Port B Indicate Data

3

O

I

k

l

PHY Port B Request Data

3

BRD3

BID4

k

l

PHY Port B Indicate Data

PHY Port B Request Data

I/O Ground

4

O

I

k

l

4

BRD4

a

GND IO

Ð

0V

5V

I/O Power

V

IO

CC

Ð

k

l

PHY Port B Indicate Data

PHY Port B Request Data

5

BID5

O

I

TTL

k

l

5

BRD5

BID6

BRD6

BID7

BRD7

BIC

k

l

PHY Port B Indicate Data

PHY Port B Request Data

6

O

I

k

l

6

k

l

PHY Port B Indicate Data

PHY Port B Request Data

7

O

I

k

l

7

PHY Port B Indicate Control

O

I

PHY Port B Request Control

PHY Port B Indicate Parity

BRC

BIP

O

139

8.0 Connection Diagrams (Continued)

TABLE 8-3. DP83257 160-Pin PQFP Pinout Summary (Continued)

Pin No.

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

Signal Name

Symbol

I/O

Pin Type

TTL

PHY Port B Request Parity

BRP

I

E

Device Reset

RST

TTL

E

Read/ Write

E

R/

E

W

I

TTL

Chip Enable

CE

I

TTL

E

Interrupt

INT

O

Open Drain

E

ACK

Acknowledge

No Connect

N/C

k

l

Control Bus Address

I/O Logic Ground

0

1

CBA0

CBA1

I

TTL

a

GND IO

Ð

0V

5V

I/O Logic Power

V IO

CC

Ð

k

l

Control Bus Address

2

3

4

5

CBA2

CBA3

CBA4

CBA5

I

TTL

a

Reserved

0

1

RES

0

1

0V

5V

Ð

k

l

Control Bus Data

Core Ground

0

CBD0

I/O

TTL

a

GND CORE

Ð

0V

5V

Core Power

V

CORE

CC

Ð

k

l

Control Bus Data

1

2

3

4

5

6

7

CBD1

CBD2

CBD3

CBD4

CBD5

CBD6

CBD7

CBP

I/O

TTL

Control Bus Data Parity

No Connect

N/C

No Connect

N/C

No Connect

N/C

140

8.0 Connection Diagrams (Continued)

TABLE 8-3. DP83257 160-Pin PQFP Pinout Summary (Continued)

Pin No.

152

153

154

155

156

157

158

159

160

Signal Name

No Connect

Symbol

N/C

I/O

Pin Type

No Connect

N/C

No Connect

N/C

No Connect

N/C

No Connect

N/C

a

I/O Ground

GND IO

Ð

0V

5V

I/O Power

V IO

CC

Ð

Local Symbol Clock

Local Byte Clock5

LSC

O

TTL

LBC5

141

9.0 Package Information

The information contained in this section describes the two packages used for the PLAYER device.

a

Land pattern information is provided to assist in surface mount layout using each of the available PLAYER device packages.

Mechanical drawings of each of the packages are also provided.

9.1 LAND PATTERNS

TL/F/11708–46

FIGURE 9-1. Layout Land Patterns

TABLE 9-1. Layout Land Pattern Dimensions

Device

A (mm)

B (mm)

P (mm)

X (mm)

DP83256VF and DP83256VF-AP

14mm x 14mm x 2.0mm

14.60

18.45

0.50

0.35

100-lead JEDEC FPQFP

DP83257VF

28.90

33.40

0.65

0.45

28mm x 28mm x 3.42mm

160-lead JEDEC MQFP

9.2 MECHANICAL DRAWINGS

a

The following two pages contain the mechanical drawings for each of the available PLAYER device packages.

142

Physical Dimensions millimeters

Plastic Quad Flatpak (VJU)

Order Number DP83256VF and DP83256VF-AP

NS Package Number VJU100A

143

Physical Dimensions millimeters (Continued)

Plastic Quad Flatpak (V)

Order Number DP83257VF

NS Package Number VUL160A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

National Semiconductor

Corporation

National Semiconductor

Europe

National Semiconductor

Hong Kong Ltd.

National Semiconductor

Japan Ltd.

a

1111 West Bardin Road

Arlington, TX 76017

Tel: 1(800) 272-9959

Fax: 1(800) 737-7018

Fax:

(

49) 0-180-530 85 86

@

13th Floor, Straight Block,

Ocean Centre, 5 Canton Rd.

Tsimshatsui, Kowloon

Hong Kong

Tel: (852) 2737-1600

Fax: (852) 2736-9960

Tel: 81-043-299-2309

Fax: 81-043-299-2408

Email: cnjwge tevm2.nsc.com

a

Deutsch Tel:

English Tel:

Fran3ais Tel:

Italiano Tel:

(

49) 0-180-530 85 85

49) 0-180-532 78 32

49) 0-180-532 93 58

49) 0-180-534 16 80

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	DP83257VF
厂家：	National Semiconductor
描述：	PLAYERa+⑩ Device (FDDI Physical Layer Controller) PLAYERa + ⑩设备（ FDDI的物理层控制器）微控制器和处理器串行IO控制器通信控制器外围集成电路信息通信管理数据传输时钟
文件：	总144页 (文件大小：988K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP83257VF [NSC]

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