DS25CP102QSQ [NSC]

Automotive 3.125 Gbps 2X2 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization; 汽车3.125 Gbps的LVDS 2×2交叉点开关与发送预加重和接收均衡


型号：	DS25CP102QSQ
厂家：	National Semiconductor
描述：	Automotive 3.125 Gbps 2X2 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization 汽车3.125 Gbps的LVDS 2×2交叉点开关与发送预加重和接收均衡开关
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July 18, 2008

DS25CP102Q

Automotive 3.125 Gbps 2X2 LVDS Crosspoint Switch with

Transmit Pre-Emphasis and Receive Equalization

General Description

Features

The DS25CP102Q is a 3.125 Gbps 2x2 LVDS crosspoint

switch optimized for high-speed signal routing and switching

over lossy FR-4 printed circuit board backplanes and bal-

anced cables. Fully differential signal paths ensure excep-

tional signal integrity and noise immunity. The non-blocking

architecture allows connections of any input to any output or

outputs.

AECQ-100 Grade 3

■

DC - 3.125 Gbps low jitter, low skew, low power operation

Pin configurable, fully differential, non-blocking

architecture

Pin selectable transmit pre-emphasis and receive

equalization eliminate data dependant jitter

■

Wide Input Common Mode Voltage Range allows DC-

coupled interface to CML and LVPECL drivers

■

The DS25CP102Q features two levels (Off and On) of trans-

mit pre-emphasis (PE) and two levels (Off and On) of receive

equalization (EQ).

On-chip 100Ω input and output termination minimizes

insertion and return losses, reduces component count and

minimizes board space

■

Wide input common mode range allows the switch to accept

signals with LVDS, CML and LVPECL levels; the output levels

are LVDS. A very small package footprint requires a minimal

space on the board while the flow-through pinout allows easy

board layout. Each differential input and output is internally

terminated with a 100Ω resistor to lower device insertion and

return losses, reduce component count and further minimize

board space.

8 kV ESD on LVDS I/O pins protects adjoining

components

Small 4 mm x 4 mm LLP-16 space saving package

■

Applications

Automotive display applications

■

Clock and data buffering and muxing

OC-48 / STM-16

SD/HD/3GHD SDI Routers

Typical Application

30063370

300633

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Ordering Code

NSID

Function

Available Equalization

Levels

Available Pre-Emphasis

Levels

DS25CP102QSQ

Crosspoint Switch

Off / On

Block Diagram

Connection Diagram

30063301

30063302

Pin Descriptions

Pin Name

Pin Number I/O, Type

Pin Description

IN0+, IN0- ,

IN1+, IN1-

1, 2,

3, 4

I, LVDS

Inverting and non-inverting high speed LVDS input pins.

OUT0+, OUT0-,

OUT1+, OUT1-

12, 11,

10, 9

O, LVDS

Inverting and non-inverting high speed LVDS output pins.

SEL0, SEL1

EN0, EN1

7, 8

14, 13

I, LVCMOS

Power

Switch configuration pins. There is a 20k pulldown resistor on this pin.

Output enable pins. There is a 20k pulldown resistor on this pin.

Transmit Pre-Emphasis select pin. There is a 20k pulldown resistor on this pin.

Receive Equalizaton select pin. There is a 20k pulldown resistor on this pin.

Power supply pin.

VDD

GND

5, DAP

Power

Ground pin and Device Attach Pad (DAP) ground.

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Package Thermal Resistance

Absolute Maximum Ratings (Note 4)

ꢀθ_JA

+41.8°C/W

+6.9°C/W

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ꢀθ_JC

ESD Susceptibility

HBM (Note 1)

Supply Voltage

−0.3V to +4V

−0.3V to (V_CC+ 0.3V)

−0.3V to +4V

≥8 kV

≥250V

LVCMOS Input Voltage

LVDS Input Voltage

MM (Note 2)

CDM (Note 3)

≥1250V

LVDS Differential Input Voltage

LVDS Output Voltage

0V to 1.0V

−0.3V to (V_CC+ 0.3V)

0V to 1.0V

Note 1: Human Body Model, applicable std. JESD22-A114C

Note 2: Machine Model, applicable std. JESD22-A115-A

LVDS Differential Output Voltage

Note 3: Field Induced Charge Device Model, applicable std.

JESD22-C101-C

LVDS Output Short Circuit Current

Duration

5 ms

Recommended Operating

Conditions

Junction Temperature

Storage Temperature Range

Lead Temperature Range

Soldering (4 sec.)

Maximum Package Power Dissipation at 25°C

SQA Package

+105°C

−65°C to +150°C

Min

3.0

Typ

Max Units

+260°C

Supply Voltage (V_CC

)

3.3

3.6

Receiver Differential Input

Voltage (V_ID)

1.91W

23.9 mW/°C above +25°C

Derate SQA Package

Operating Free Air

Temperature (T_A)

−40

+25

+85

°C

DC Electrical Characteristics (Notes 5, 6, 7)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions

LVCMOS DC SPECIFICATIONS

Min

Typ

Max

Units

V_IH

V_IL

I_IH

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

2.0

GND

V_CC

0.8

V_IN= 3.6V

V_CC= 3.6V

175

250

μA

I_IL

Low Level Input Current

V_IN= GND

V_CC= 3.6V

±10

μA

V_CL

Input Clamp Voltage

I_CL= −18 mA, V_CC= 0V

−0.9

−1.5

LVDS INPUT DC SPECIFICATIONS

V_ID

Input Differential Voltage

V_CM= +0.05V or V_CC-0.05V

V_ID= 100 mV

V_TH

V_TL

Differential Input High Threshold

Differential Input Low Threshold

Common Mode Voltage Range

+100

−100

0.05

V_CMR

V_CC-

0.05

±10

V_IN= +3.6V or 0V

V_CC= 3.6V or 0V

±1

μA

I_IN

Input Current

C_IN

R_IN

1.7

Input Capacitance

Any LVDS Input Pin to GND

Between IN+ and IN-

100

Input Termination Resistor

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS OUTPUT DC SPECIFICATIONS

V_OD

Differential Output Voltage

250

-35

350

450

R_L= 100Ω

Change in Magnitude of V_ODfor Complimentary

Output States

ΔV_OD

V_OS

Offset Voltage

1.05

-35

1.2

1.375

Change in Magnitude of V_OSfor Complimentary

Output States

ΔV_OS

I_OS

Output Short Circuit Current (Note 8)

OUT to GND

-35

-55

OUT to V_CC

C_OUT

R_OUT

Output Capacitance

Any LVDS Output Pin to GND

Between OUT+ and OUT-

1.2

100

Output Termination Resistor

SUPPLY CURRENT

I_CC

Supply Current

Supply Current with Outputs Disabled

PE = OFF, EQ = OFF

EN0 = EN1 = 0

I_CCZ

Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V_ODand

ΔV_OD

Note 7: Typical values represent most likely parametric norms for V_CC= +3.3V and T_A= +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 8: Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only.

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AC Electrical Characteristics (Note 11)

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)

Symbol

LVDS OUTPUT AC SPECIFICATIONS

t_PLHDDifferential Propagation Delay Low to

Parameter

Conditions

Min

Typ

Max

Units

365

345

500

High

R_L= 100Ω

t_PHLD

Differential Propagation Delay High to

Low

t_SKD1

t_SKD2

t_SKD3

t_LHT

Pulse Skew |t_PLHD− t_PHLD| (Note 12)

Channel to Channel Skew (Note 13)

Part to Part Skew , (Note 14)

Rise Time

150

120

R_L= 100Ω

t_HLT

Fall Time

t_ON

Output Enable Time

Output Disable Time

Select Time

ENn = LH to output active

ENn = HL to output inactive

SELn LH or HL to output

μs

t_OFF

t_SEL

3.5

JITTER PERFORMANCE WITH EQ = Off, PE = Off (Figure 5)

t_RJ1

t_RJ2

V_ID= 350 mV

2.5 Gbps

0.5

Random Jitter (RMS Value)

No Test Channels

(Note 15)

V_CM= 1.2V

3.125 Gbps

2.5 Gbps

Clock (RZ)

t_DJ1

t_DJ2

V_ID= 350 mV

V_CM= 1.2V

Deterministic Jitter (Peak to Peak)

No Test Channels

(Note 16)

3.125 Gbps

2.5 Gbps

K28.5 (NRZ)

V_ID= 350 mV

V_CM= 1.2V

t_TJ1

t_TJ2

UI_P-P

0.03

0.05

0.08

0.11

Total Jitter (Peak to Peak)

No Test Channels

(Note 17)

3.125 Gbps

PRBS-23 (NRZ)

JITTER PERFORMANCE WITH EQ = Off, PE = On (Figure 6 Figure 9)

t_RJ1B

t_RJ2B

V_ID= 350 mV

V_CM= 1.2V

2.5 Gbps

0.5

Random Jitter (RMS Value)

Test Channel B

(Note 15)

3.125 Gbps

2.5 Gbps

Clock (RZ)

t_DJ1B

t_DJ2B

V_ID= 350 mV

V_CM= 1.2V

Deterministic Jitter (Peak to Peak)

Test Channel B

(Note 16)

3.125 Gbps

2.5 Gbps

K28.5 (NRZ)

V_ID= 350 mV

V_CM= 1.2V

t_TJ1B

t_TJ2B

UI_P-P

0.03

0.04

0.06

0.09

Total Jitter (Peak to Peak)

Test Channel B

(Note 17)

3.125 Gbps

PRBS-23 (NRZ)

JITTER PERFORMANCE WITH EQ = On, PE = Off (Figure 7 Figure 9)

t_RJ1D

t_RJ2D

V_ID= 350 mV

V_CM= 1.2V

2.5 Gbps

0.5

Random Jitter (RMS Value)

Test Channel D

(Note 15)

3.125 Gbps

2.5 Gbps

Clock (RZ)

t_DJ1D

t_DJ2D

V_ID= 350 mV

V_CM= 1.2V

Deterministic Jitter (Peak to Peak)

Test Channel D

(Note 16)

3.125 Gbps

2.5 Gbps

K28.5 (NRZ)

V_ID= 350 mV

V_CM= 1.2V

t_TJ1D

t_TJ2D

UI_P-P

0.07

0.11

Total Jitter (Peak to Peak)

Test Channel D

(Note 17)

3.125 Gbps

PRBS-23 (NRZ)

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

JITTER PERFORMANCE WITH EQ = On, PE = On (Figure 8 Figure 9)

t_RJ1BD

t_RJ2BD

Random Jitter (RMS Value)

Input Test Channel D

Output Test Channel B

(Note 15)

V_ID= 350 mV

V_CM= 1.2V

Clock (RZ)

2.5 Gbps

0.5

3.125 Gbps

2.5 Gbps

t_DJ1BD

t_DJ2BD

Deterministic Jitter (Peak to Peak)

Input Test Channel D

Output Test Channel B

(Note 16)

V_ID= 350 mV

V_CM= 1.2V

3.125 Gbps

2.5 Gbps

K28.5 (NRZ)

t_TJ1BD

t_TJ2BD

Total Jitter (Peak to Peak)

Input Test Channel D

Output Test Channel B

(Note 17)

V_ID= 350 mV

V_CM= 1.2V

UI_P-P

0.08

0.10

0.15

0.16

3.125 Gbps

PRBS-23 (NRZ)

Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 10: Typical values represent most likely parametric norms for V_CC= +3.3V and T_A= +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 11: Specification is guaranteed by characterization and is not tested in production.

Note 12: t_SKD1, |t_PLHD− t_PHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

Note 13: t_SKD2, Channel to Channel Skew, is the difference in propagation delay (t_PLHDor t_PHLD) among all output channels in Broadcast mode (any one input to

all outputs).

Note 14: t_SKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to

devices at the same V_CCand within 5°C of each other within the operating temperature range.

Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.

Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted

algebraically.

Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.

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DC Test Circuits

30063320

FIGURE 1. Differential Driver DC Test Circuit

AC Test Circuits and Timing Diagrams

30063321

FIGURE 2. Differential Driver AC Test Circuit

30063322

FIGURE 3. Propagation Delay Timing Diagram

30063323

FIGURE 4. LVDS Output Transition Times

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Pre-Emphasis and Equalization Test Circuits

30063329

FIGURE 5. Jitter Performance Test Circuit

30063327

FIGURE 6. Pre-Emphasis Performance Test Circuit

30063326

FIGURE 7. Equalization Performance Test Circuit

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30063330

FIGURE 8. Pre-Emphasis and Equalization Performance Test Circuit

30063328

FIGURE 9. Test Channel Block Diagram

stant of 3.7 and Loss Tangent of 0.02). The edge coupled

differential striplines have the following geometries: Trace

Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.

Test Channel Loss Characteristics

The test channel was fabricated with Polyclad PCL-FR-370-

Laminate/PCL-FRP-370 Prepreg materials (Dielectric con-

Test Channel

Length

Insertion Loss (dB)

(inches)

500 MHz

-1.2

750 MHz

-1.7

1000 MHz

-2.0

1250 MHz

-2.4

1500 MHz

-2.7

1560 MHz

-2.8

-2.6

-3.5

-4.1

-4.8

-5.5

-5.6

-4.3

-5.7

-7.0

-8.2

-9.4

-9.7

-1.6

-2.2

-2.7

-3.2

-3.7

-3.8

-3.4

-4.5

-5.6

-6.6

-7.7

-7.9

-7.8

-10.3

-12.4

-14.5

-16.6

-17.0

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Functional Description

The DS25CP102Q is a 3.125 Gbps 2x2 LVDS digital cross-

point switch optimized for high-speed signal routing and

switching over lossy FR-4 printed circuit board backplanes

and balanced cables.

TABLE 1. Switch Configuration Truth Table

SEL0 OUT1

IN0

SEL1

OUT0

IN0

IN1

IN0

IN1

TABLE 2. Output Enable Truth Table

EN1

EN0

OUT1

OUT0

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

In addition, the DS25CP102Q has a pre-emphasis control pin

for switching the transmit pre-emphasis to ON and OFF set-

ting and an equalization control pin for switching the receive

equalization to ON and OFF setting. The following are the

transmit pre-emphasis and receive equalization truth tables.

Transmit Pre-Emphasis Truth Table

OUTPUTS OUT0 and OUT1

CONTROL Pin (PE) State

Pre-Emphasis Level

OFF

Transmit Pre-Emphasis Level Selection

Receive Equalization Truth Table

INPUTS IN0 and IN1

CONTROL Pin (EQ) State

Equalization Level

OFF

Receive Equalization Level Selection

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ferential drivers (i.e. LVPECL, LVDS, CML). The following

three figures illustrate typical DC-coupled interface to com-

mon differential drivers. Note that the DS25CP102Q inputs

are internally terminated with a 100Ω resistor.

Input Interfacing

The DS25CP102Q accepts differential signals and allows

simple AC or DC coupling. With a wide common mode range,

the DS25CP102Q can be DC-coupled with all common dif-

Typical LVDS Driver DC-Coupled Interface to DS25CP102Q Inpu³t^0063331

30063332

Typical CML Driver DC-Coupled Interface to DS25CP102Q Input

30063333

Typical LVPECL Driver DC-Coupled Interface to DS25CP102Q Input

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and assumes that the receivers have high impedance inputs.

While most differential receivers have a common mode input

range that can accomodate LVDS compliant signals, it is rec-

ommended to check respective receiver's data sheet prior to

implementing the suggested interface implementation.

Output Interfacing

The DS25CP102Q outputs signals that are compliant to the

LVDS standard. Its outputs can be DC-coupled to most com-

mon differential receivers. The following figure illustrates typ-

ical DC-coupled interface to common differential receivers

30063334

Typical DS25CP102Q Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver

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Typical Performance

30063350

30063352

Total Jitter as a Function of Data Rate

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and EQ Level

30063358

Total Jitter as a Function of Input Common Mode Voltage

30063357

Supply Current as a Function of Data Rate and PE Level

30063351

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and PE Level

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30063360

30063362

A 3.125 Gbps NRZ PRBS-7 without PE or EQ

A 3.125 Gbps NRZ PRBS-7 with PE

After 40" Differential FR-4 Stripline

H: 50 ps / DIV, V: 100 mV / DIV

After 2" Differential FR-4 Stripline

H: 50 ps / DIV, V: 100 mV / DIV

A 3.125 Gbps NRZ PRBS-7 without PE or³E⁰⁰⁶Q³³⁶¹

After 40" Differential FR-4 Stripline

H: 50 ps / DIV, V: 100 mV / DIV

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Physical Dimensions inches (millimeters) unless otherwise noted

Order Number DS25CP102QSQ

NS Package Number SQA16A

(See AN-1187 for PCB Design and Assembly Recommendations)

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Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products

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WEBENCH

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Analog University

App Notes

Clock Conditioners

Data Converters

Displays

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Distributors

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www.national.com/interface

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Green Compliance

Packaging

Ethernet

Interface

Quality and Reliability www.national.com/quality

LVDS

Reference Designs

Feedback

www.national.com/refdesigns

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LDOs

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www.national.com/switchers

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PowerWise

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Serial Digital Interface (SDI) www.national.com/sdi

Temperature Sensors

Wireless (PLL/VCO)

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