DS25CP104ATSQ_技术文档

May 13, 2009

DS25CP104A / DS25CP114

3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit

Pre-Emphasis and Receive Equalization

General Description

Features

The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4

LVDS crosspoint switches optimized for high-speed signal

routing and switching over lossy FR-4 printed circuit board

backplanes and balanced cables. Fully differential signal

paths ensure exceptional signal integrity and noise immunity.

The non-blocking architecture allows connections of any input

to any output or outputs. The switch configuration can be ac-

complished via external pins or the System Management Bus

(SMBus) interface.

DC - 3.125 Gbps low jitter, low skew, low power operation

■

Pin and SMBus configurable, fully differential, non-

blocking architecture

Pin (two levels) and SMBus (four levels) selectable pre-

emphasis and equalization eliminate ISI jitter

■

Wide Input Common Mode Range enables easy interface

to CML and LVPECL drivers

■

LOS circuitry detects open inputs fault condition

■

On-chip 100Ω input and output termination minimizes

insertion and return losses, reduces component count and

minimizes board space. The DS25CP114 eliminates the

on-chip input termination for added design flexibility.

8 kV ESD on LVDS I/O pins protects adjoining

components

■

The DS25CP104A and DS25CP114 feature four levels (Off,

Low, Medium, High) of transmit pre-emphasis (PE) and four

levels (Off, Low, Medium, High) of receive equalization (EQ)

settable via the SMBus interface. Off and Medium PE levels

and Off and Low EQ levels are settable with the external pins.

In addition, the SMBus circuitry enables the loss of signal

(LOS) monitors that can inform a system of the presence of

an open inputs condition (e.g. disconnected cable).

■

Small 6 mm x 6 mm LLP-40 space saving package

Applications

Wide input common mode range allows the switch to accept

signals with LVDS, CML and LVPECL levels; the output levels

are LVDS. A very small package footprint requires a minimal

space on the board while the flow-through pinout allows easy

board layout. On the DS25CP104A each differential input and

output is internally terminated with a 100Ω resistor to lower

return losses, reduce component count and further minimize

board space. For added design flexibility the 100Ω input ter-

minations on the DS25CP114 have been eliminated. This

enables a designer to build custom crosspoint configurations

and distribution circuits that require a limited multidrop sig-

naling topology.

SD/HD/3G HD SDI Routers

■

OC-48 / STM-16

InfiniBand and FireWire

■

Typical Application

30073603

300736

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Device Information

Device

Function

Termination Option

Available Signal

Conditioning

DS25CP104A

DS25CP114

4x4 Crosspoint Switch

4 Levels: PE and EQ

4 Levels : PE and EQ

Internal 100Ω for LVDS inputs

None: Requires external

termination

Ordering Information

NSID

Package

Tape & Reel QTY

Package Number

SQA40A

DS25CP104ATSQ

DS25CP104ATSQX

DS25CP114TSQ

DS25CP114TSQX

40 Lead LLP Package

250

2500

250

SQA40A

2500

SQA40A

Block Diagrams

30073601

DS25CP104A

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2

30073611

DS25CP114

3

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Connection Diagram

30073602

DS25CP104A / DS25CP114 Pin Diagram

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4

Pin Descriptions

Number

Pin Name

I/O, Type

Pin Description

IN0+, IN0- ,

IN1+, IN1-,

IN2+, IN2-,

IN3+, IN3-

1, 2,

4, 5,

6, 7,

9, 10

I, LVDS

Inverting and non-inverting high speed LVDS input pins. These 4

input pairs have a 100 Ohm differential input termination on the

CP104A device. The CP114 eliminates the input termination for

added design flexibility.

OUT0+, OUT0-,

OUT1+, OUT1-,

OUT2+, OUT2-,

OUT3+, OUT3-

29, 28,

27, 26,

24, 23,

22, 21

O, LVDS

Inverting and non-inverting high speed LVDS output pins. Each

output pair has an internal 100 Ohm termination to improve device

return loss characteristics.

EQ0, EQ1,

EQ2, EQ3

40, 39,

11, 12

I, LVCMOS

Receive equalization level select pins. These pins are functional

regardless of the EN_smb pin state.

PE0, PE1,

PE2, PE3

31, 20,

19, 18

Transmit pre-emphasis level select pins. These pins are functional

regardless of the EN_smb pin state.

EN_smb

17

System Management Bus (SMBus) enable pin. The pin has an

internal pull down. When the pin is set to a [1], the device is in the

SMBus mode. All SMBus registers are reset when this pin is

toggled. There is a 20k pulldown device on this pin.

S00/SCL

S01/SDA

37

36

I, LVCMOS

For EN_smb = [0], these pins select which LVDS input is routed

to the OUT0.

I/O, LVCMOS

In the SMBus mode, when the EN_smb = [1], these pins are

SMBus clock input and data input pins respectively.

S10/ADDR0,

S11/ADDR1

35,

34

I, LVCMOS

For EN_smb = [0], these pins select which LVDS input is routed

to the OUT1.

In the SMBus mode, when the EN_smb = [1], these pins are the

User-Set SMBus Slave Address inputs.

S20/ADDR2,

S21/ADDR3

33,

32

For EN_smb = [0], these pins select which LVDS input is routed

to the OUT2.

In the SMBus mode, when the EN_smb = H, these pins are the

User-Set SMBus Slave Address inputs.

S30, S31

PWDN

13, 14

38

For EN_smb = [0], these pins select which LVDS input is routed

to the OUT3.

In the SMBus mode, when the EN_smb = [1], these pins are non-

functional and should be tied to either logic H or L.

For EN_smb = [0], this is the power down pin. When the PWDN is

set to a [0], the device is in the power down mode. The SMBus

circuitry can still be accessed provided the EN_smb pin is set to a

[1].

In the SMBus mode, the device is powered up by either setting the

PWDN pin to [1] OR by writing a [1] to the Control Register D[7]

bit ( SoftPWDN). The device will be powered down by setting the

PWDN pin to [0] AND by writing a [0] to the Control Register D[7]

bit ( SoftPWDN).

VDD

GND

3, 8,

15,25, 30

Power

Power supply pins.

16, DAP Power

Ground pin and a pad (DAP - die attach pad).

Note: Center DAP connection must be made to GND for optimum electrical and thermal performance.

5

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Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Package Thermal Resistance

ꢀθ_JA

+26.9°C/W

+3.8°C/W

ꢀθ_JC

ESD Susceptibility

HBM (Note 1)

Supply Voltage

−0.3V to +4V

−0.3V to (V_CC+ 0.3V)

−0.3V to +4V

LVCMOS Input Voltage

LVCMOS Output Voltage

LVDS Input Voltage

LVDS Differential Input Voltage

(DS25CP104A)

LVDS Differential Input Voltage

(DS25CP114)

LVDS Output Voltage

≥8 kV

≥250V

≥1250V

MM (Note 2)

CDM (Note 3)

Note 1: Human Body Model, applicable std. JESD22-A114C

Note 2: Machine Model, applicable std. JESD22-A115-A

1.0V

Note 3: Field Induced Charge Device Model, applicable std.

JESD22-C101-C

V_CC+ 0.6V

−0.3V to (V_CC+ 0.3V)

0V to 1.0V

LVDS Differential Output Voltage

LVDS Output Short Circuit Current

Duration

Junction Temperature

Storage Temperature Range

Lead Temperature Range

Soldering (4 sec.)

Recommended Operating

Conditions

5 ms

+150°C

−65°C to +150°C

Min

3.0

0

Typ

3.3

Max Units

Supply Voltage (V_CC

)

3.6

1

V

Receiver Differential Input

Voltage (V_ID)

+260°C

(DS25CP104A only)

Operating Free Air

Temperature (T_A)

Maximum Package Power Dissipation at 25°C

SQA Package

−40

+25

+85

3.6

°C

V

4.65W

Derate SQA Package

37.2 mW/°C above +25°C

SMBus (SDA, SCL)

DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 8)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVCMOS DC SPECIFICATIONS

V_IH

V_IL

I_IH

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

2.0

V_CC

0.8

V

GND

V

V_IN= 3.6V

V_CC= 3.6V

0

175

0

±10

250

±10

μA

EN_smb pin

40

I_IL

Low Level Input Current

V_IN= GND

V_CC= 3.6V

V_CL

V_OL

Input Clamp Voltage

I_CL= −18 mA, V_CC= 0V

I_OL= 4 mA SDA pin

−0.9

−1.5

0.4

V

Low Level Output Voltage

LVDS INPUT DC SPECIFICATIONS

V_ID

V_TH

V_TL

Input Differential Voltage(Note 9)

Differential Input High Threshold

Differential Input Low Threshold

0

1

V

V_CM= +0.05V or V_CC-0.05V

V_ID= 100 mV

0

+100

mV

−100

0.05

V_CC

-

V_CMR

I_IN

Input Common Mode Voltage Range

Input Current(Note 7)

V

0.05

V_IN= +3.6V or 0V

V_CC= 3.6V or 0V

±1

±10

μA

C_IN

R_IN

Input Capacitance

Any LVDS Input Pin to GND

Between IN+ and IN-

1.7

pF

100

Input Termination Resistor(Note 10)

Ω

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6

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS OUTPUT DC SPECIFICATIONS

V_OD

Differential Output Voltage

250

-35

350

450

35

mV

V

R_L= 100Ω

Change in Magnitude of V_ODfor Complimentary

Output States

ΔV_OD

V_OS

Offset Voltage

1.05

-35

1.2

1.375

35

Change in Magnitude of V_OSfor Complimentary

Output States

ΔV_OS

mV

OUT to GND

-35

7

-55

55

mA

pF

Ω

I_OS

Output Short Circuit Current (Note 11)

OUT to V_CC

C_OUT

R_OUT

Output Capacitance

Any LVDS Output Pin to GND

Between OUT+ and OUT-

1.2

100

Output Termination Resistor

SUPPLY CURRENT

I_CC1Supply Current

I_CC2

PWDN = 0

40

50

mA

Supply Current

PWDN = 1

145

175

PE = Off, EQ = Off

Broadcast (1:4) Mode

I_CC3

Supply Current

PWDN = 1

157

190

mA

PE = Off, EQ = Off

Quad Buffer (4:4) Mode

Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V_ODand

ΔV_OD

.

Note 7: I_INis applied to both pins of the LVDS input pair at the same time.

Note 8: Typical values represent most likely parametric norms for V_CC= +3.3V and T_A= +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 9: Input Differential Voltage (V_ID) The DS25CP104A limits input amplitude to 1 volt. The DS25CP114 supports any V_IDwithin the supply voltage to GND

range.

Note 10: Input Termination Resistor (R_IN) The DS25CP104A provides an integrated 100 ohm input termination for each high speed LVDS pair. The DS25CP114

eliminates this internal termination.

Note 11: Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only.

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AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 12, 13)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS OUTPUT AC SPECIFICATIONS (Note 14)

t_PLHD

t_PHLD

Differential Propagation Delay Low to

High

480

460

650

ps

R_L= 100Ω

Differential Propagation Delay High to

Low

t_SKD1

t_SKD2

t_SKD3

t_LHT

Pulse Skew |t_PLHD− t_PHLD| , (Note 15)

Channel to Channel Skew , (Note 16)

Part to Part Skew , (Note 17)

Rise Time

20

40

50

80

6

100

125

200

150

20

ps

R_L= 100Ω

t_HLT

Fall Time

t_ON

Power Up Time

Time from PWDN =LH to OUTn active

Time from PWDN =HL to OUTn inactive

μs

ns

t_OFF

t_SEL

Power Down Time

8

25

Select Time

Time from Sn =LH or HL to new signal

at OUTn

8

12

JITTER PERFORMANCE WITH EQ = Off, PE = Off (Note 14)(Figure 5)

t_RJ1

t_RJ2

V_ID= 350 mV

V_CM= 1.2V

1.25 GHz

0.5

1.1

ps

Random Jitter (RMS Value)

No Test Channels

(Note 18)

1.5625 GHz

2.5 Gbps

Clock (RZ)

t_DJ1

t_DJ2

V_ID= 350 mV

V_CM= 1.2V

10

22

ps

Deterministic Jitter (Peak to Peak)

No Test Channels

(Note 19)

3.125 Gbps

2.5 Gbps

10

27

ps

K28.5 (NRZ)

V_ID= 350 mV

V_CM= 1.2V

t_TJ1

t_TJ2

UI_P-P

0.07

0.13

0.11

0.16

Total Jitter (Peak to Peak)

No Test Channels

(Note 20)

3.125 Gbps

PRBS-23 (NRZ)

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8

Symbol

Parameter

Conditions

Min

Typ

Max

Units

JITTER PERFORMANCE WITH EQ = Off, PE = Low(Note 14) (Figure 6 Figure 9)

t_RJ1A

t_RJ2A

V_ID= 350 mV

V_CM= 1.2V

Clock (RZ)

1.25 GHz

0.5

10

1.1

22

ps

Random Jitter (RMS Value)

Test Channels A

(Note 18)

1.5625 GHz

2.5 Gbps

t_DJ1A

t_DJ2A

V_ID= 350 mV

V_CM= 1.2V

K28.5 (NRZ)

Deterministic Jitter (Peak to Peak)

Test Channels A

(Note 19)

3.125 Gbps

10

27

JITTER PERFORMANCE WITH EQ = Off, PE = Medium (Note 14) (Figure 6 Figure 9)

t_RJ1B

t_RJ2B

V_ID= 350 mV

V_CM= 1.2V

1.25 GHz

0.5

1.1

ps

Random Jitter (RMS Value)

Test Channels B

(Note 18)

1.5625 GHz

2.5 Gbps

Clock (RZ)

t_DJ1B

t_DJ2B

V_ID= 350 mV

V_CM= 1.2V

12

30

ps

Deterministic Jitter (Peak to Peak)

Test Channels B

(Note 19)

3.125 Gbps

2.5 Gbps

12

30

ps

K28.5 (NRZ)

V_ID= 350 mV

V_CM= 1.2V

t_TJ1B

t_TJ2B

UI_P-P

0.08

0.10

0.15

Total Jitter (Peak to Peak)

Test Channels B

(Note 20)

3.125 Gbps

PRBS-23 (NRZ)

JITTER PERFORMANCE WITH EQ = Off, PE = High (Note 14) (Figures 6, 9)

t_RJ1C

t_RJ2C

V_ID= 350 mV

V_CM= 1.2V

Clock (RZ)

1.25 GHz

0.5

30

1.1

60

ps

Random Jitter (RMS Value)

Test Channels C

(Note 18)

1.5625 GHz

2.5 Gbps

t_DJ1C

t_DJ2C

V_ID= 350 mV

V_CM= 1.2V

K28.5 (NRZ)

Deterministic Jitter (Peak to Peak)

Test Channels C

(Note 19)

3.125 Gbps

30

65

9

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

JITTER PERFORMANCE WITH PE = Off, EQ = Low (Note 14) (Figure 7 Figure 9)

t_RJ1D

t_RJ2D

V_ID= 350 mV

V_CM= 1.2V

1.25 GHz

0.5

1.1

ps

Random Jitter (RMS Value)

Test Channels D

(Note 18)

1.5625 GHz

2.5 Gbps

Clock (RZ)

t_DJ1D

t_DJ2D

V_ID= 350 mV

V_CM= 1.2V

20

40

ps

Deterministic Jitter (Peak to Peak)

Test Channels D

(Note 19)

3.125 Gbps

2.5 Gbps

20

40

ps

K28.5 (NRZ)

V_ID= 350 mV

V_CM= 1.2V

t_TJ1D

t_TJ2D

UI_P-P

0.08

0.09

0.15

0.20

Total Jitter (Peak to Peak)

Test Channels D

(Note 20)

3.125 Gbps

PRBS-23 (NRZ)

JITTER PERFORMANCE WITH PE = Off, EQ = Medium (Note 14) (Figures 7, 9)

t_RJ1E

t_RJ2E

V_ID= 350 mV

V_CM= 1.2V

Clock (RZ)

1.25 GHz

1.5625 GHz

2.5 Gbps

0.5

35

1.1

60

ps

Random Jitter (RMS Value)

Test Channels E

(Note 18)

t_DJ1E

t_DJ2E

Residual Deterministic Jitter (Peak to

Peak)

Test Channels E

(Note 19)

V_ID= 350 mV

V_CM= 1.2V

K28.5 (NRZ)

3.125 Gbps

28

55

ps

JITTER PERFORMANCE WITH PE = Off, EQ = High (Note 14) (Figures 7, 9)

t_RJ1F

t_RJ2F

V_ID= 350 mV

V_CM= 1.2V

Clock (RZ)

1.25 GHz

1.5625 GHz

2.5 Gbps

1.3

1.4

30

1.8

2.4

75

ps

Random Jitter (RMS Value)

Test Channels F

(Note 18)

t_DJ1F

t_DJ2F

Residual Deterministic Jitter (Peak to

Peak)

Test Channels F

(Note 19)

V_ID= 350 mV

V_CM= 1.2V

K28.5 (NRZ)

3.125 Gbps

35

90

ps

JITTER PERFORMANCE WITH PE = Medium, EQ = Low (Note 14) (Figures 7, 9)

t_RJ1G

t_RJ2G

Random Jitter (RMS Value)

Input Test Channels D

Output Test Channels B

(Note 18)

V_ID= 350 mV

V_CM= 1.2V

Clock (RZ)

1.25 GHz

0.5

25

1.1

ps

1.5625 GHz

2.5 Gbps

t_DJ1G

t_DJ2G

Deterministic Jitter (Peak to Peak)

Input Test Channels D

Output Test Channels B

(Note 19)

V_ID= 350 mV

V_CM= 1.2V

3.125 Gbps

20

K28.5 (NRZ)

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10

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SMBus AC SPECIFICATIONS

f_SMB

t_BUF

SMBus Operating Frequency

10

100

kHz

Bus free time between Stop and Start

Conditions

4.7

μs

t_HD:SDA

Hold time after (Repeated) Start

Condition. After this period, the first clock

is generated.

4.0

μs

t_SU:SDA

t_SU:SDO

t_HD:DAT

t_SU:DAT

t_TIMEOUT

t_LOW

Repeated Start Condition setup time.

Stop Condition setup time

Data hold time

4.7

4.0

300

250

25

μs

ns

ms

μs

Data setup time

Detect clock low timeout

Clock low period

35

4.7

4.0

t_HIGH

Clock high period

50

t_POR

Time in which a device must be

operational after power-on reset

500

ms

Note 12: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 13: Typical values represent most likely parametric norms for V_CC= +3.3V and T_A= +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 14: Specification is guaranteed by characterization and is not tested in production.

Note 15: t_SKD1, |t_PLHD− t_PHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

Note 16: t_SKD2, Channel to Channel Skew, is the difference in propagation delay (t_PLHDor t_PHLD) among all output channels in Broadcast mode (any one input to

all outputs).

Note 17: t_SKD3, Part to Part Skew, is defined as the difference between the same signal path of any two devices running at the same V_CCand within 5°C of each

other within the operating temperature range.

Note 18: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.

Note 19: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted

algebraically.

Note 20: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.

11

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DC Test Circuits

30073620

FIGURE 1. Differential Driver DC Test Circuit

AC Test Circuits and Timing Diagrams

30073621

FIGURE 2. Differential Driver AC Test Circuit

Note: DS25CP114 requires external 100Ω input termination.

30073622

FIGURE 3. Propagation Delay Timing Diagram

30073623

FIGURE 4. LVDS Output Transition Times

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Pre-Emphasis and Equalization Test Circuits

30073629

FIGURE 5. Jitter Performance Test Circuit

Note: DS25CP114 requires external 100Ω input termination.

30073627

FIGURE 6. Pre-Emphasis Performance Test Circuit

Note: DS25CP114 requires external 100Ω input termination.

30073626

FIGURE 7. Equalization Performance Test Circuit

Note: DS25CP114 requires external 100Ω input termination.

13

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30073630

FIGURE 8. Pre-Emphasis and Equalization Performance Test Circuit

Note: DS25CP114 requires external 100Ω input termination.

30073628

FIGURE 9. Test Channel Block Diagram

Test Channel Loss Characteristics

The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric constant of 3.7

and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries: Trace Width (W) = 5 mils, Gap

(S) = 5 mils, Height (B) = 16 mils.

Test Channel

Length

(inches)

Insertion Loss (dB)

1000 MHz 1250 MHz

-2.0 -2.4

500 MHz

-1.2

750 MHz

-1.7

1500 MHz

-2.7

1560 MHz

-2.8

A

B

C

D

E

F

10

20

30

15

30

60

-2.6

-3.5

-4.1

-7.0

-2.7

-5.6

-12.4

-4.8

-8.2

-3.2

-6.6

-14.5

-5.5

-5.6

-4.3

-5.7

-9.4

-9.7

-1.6

-2.2

-3.7

-3.8

-3.4

-4.5

-7.7

-7.9

-7.8

-10.3

-16.6

-17.0

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14

S10, S11, S21 and S21 pins become the User-Set SMBus

Slave Address input pins (ADDR0, 1, 2 and 3) while the S30

and S31 pins become non-functional (tieing these two pins to

either H or L is recommended if the device will function only

in the SMBus mode).

Functional Description

The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4

LVDS digital crosspoint switch optimized for high-speed sig-

nal routing and switching over lossy FR-4 printed circuit board

backplanes and balanced cables. The DS25CP104A and

DS25CP114 operate in two modes: Pin Mode

(EN_smb = 0) and SMBus Mode (EN_smb = 1).

In the SMBus Mode, the PE and EQ select pins as well as the

PWDN pin remain functional. How these pins function in each

mode is explained in the following sections.

When in the Pin Mode, the switch is fully configurable with

external pins. This is possible with two input select pins per

output (e.g. S00 and S01 pins for OUT0). There is also one

transmit pre-emphasis (PE) level select pin per output for

switching the PE levels between Medium and Off settings and

one receive equalization (EQ) level select pin per input for

switching the EQ levels between Low and Off settings.

OPERATION IN PIN MODE

Power Up

In the Pin Mode, when the power is applied to the device

power suppy pins, the DS25CP104A/DS25CP114 enters the

Power Up mode when the PWDN pin is set to logic H. When

in the Power Down mode (PWDN pin is set to logic L), all

circuitry is shut down except the minimum required circuitry

for the LOS and SMBus Slave operation.

In the Pin Mode, feedback from the LOS (Loss Of Signal)

monitor circuitry is not available (there is not an LOS output

pin).

When in the SMBus Mode, the full switch configuration, four

levels of transmit pre-emphasis (Off, Low, Medium and High),

four levels of receive equalization (Off, Low, Medium and

High) and SoftPWDN can be programmed via the SMBus in-

terface. In addition, by using the SMBus interface, a user can

obtain the feedback from the built-in LOS circuitry which de-

tects an open inputs fault condition.

Switch Configuration

In the Pin Mode, the DS25CP104A/DS25CP114 operates as

a fully pin-configurable crosspoint switch. The following truth

tables illustrate how the swich can be configured with external

pins.

In the SMBus Mode, the S00 and S01 pins become SMBus

clock (SCL) input and data (SDA) input pins respectively; the

Switch Configuration Truth Tables

TABLE 1. Input Select Pins Configuration for the Output OUT0

S01

0

S00

0

INPUT SELECTED

IN0

IN1

IN2

IN3

0

1

0

1

TABLE 2. Input Select Pins Configuration for the Output OUT1

S11

0

S10

0

INPUT SELECTED

IN0

IN1

IN2

IN3

0

1

0

1

15

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TABLE 3. Input Select Pins Configuration for the Output OUT2

S21

0

S20

0

INPUT SELECTED

IN0

IN1

IN2

IN3

0

1

0

1

TABLE 4. Input Select Pins Configuration for the Output OUT3

S31

0

S30

0

INPUT SELECTED

IN0

IN1

IN2

IN3

0

1

0

1

Setting Pre-Emphasis Levels

Medium or Off level. The following is the transmit pre-empha-

sis truth table.

The DS25CP104A/DS25CP114 has one PE level select pin

per output for setting the transmit pre-emphasis to either

TABLE 5. Transmit Pre-Emphasis Truth Table

OUTPUT OUTn, n = {0, 1, 2, 3}

Pre-Emphasis Control Pin (PEn) State

Pre-Emphasis Level

0

1

Off

Medium

Transmit Pre-emphasis Level Selection for an Output OUTn

Setting Equalization Levels

The DS25CP104A/DS25CP114 has one EQ level select pin

per input for setting the receive equalization to either Low or

Off level. The following is the receive equalization truth table.

TABLE 6. Receive Equalization Truth Table

INPUT INn, n = {0, 1, 2, 3}

Equalization Control Pin (EQn) State

Equalization Level

0

1

Off

Low

Receive Equalization Level Selection for an Input INn

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16

OPERATION IN SMBUS MODE

nificant bits of the slave address are hard wired inside the

DS25CP104A/DS25CP114 and are “101”. The four least sig-

nificant bits of the address are assigned to pins ADDR3-

ADDR0 and are set by connecting these pins to GND for a

low (0) or to VCC for a high (1). The complete slave address

is shown in the following table:

The DS25CP104A/DS25CP114 operates as a slave on the

System Management Bus (SMBus) when the EN_smb pin is

set to a high (1). Under these conditions, the SCL pin is a clock

input while the SDA pin is a serial data input pin.

Device Address

Based on the SMBus 2.0 specification, the DS25CP104A/

DS25CP114 has a 7-bit slave address. The three most sig-

TABLE 7. Slave Address

1

0

1

ADDR3

ADDR2

ADDR1

ADDR0

LSB

MSB

This slave address configuration allows up to sixteen

DS25CP104A/DS25CP114 devices on a single SMBus bus.

2) The Device (Slave) drives an ACK bit (“0”).

3) The Host drives the 8-bit Register Address.

4) The Device drives an ACK bit (“0”).

5) The Host drives the 8-bit data byte.

6) The Device drives an ACK bit “0”.

Transfer of Data via the SMBus

During normal operation the data on SDA must be stable dur-

ing the time when SCK is high.

7) The Host drives a STOP condition.

There are three unique states for the SMBus:

The WRITE transaction is completed, the bus goes Idle and

communication with other SMBus devices may now occur.

START: A HIGH to LOW transition on SDA while SCK is high

indicates a message START condition.

STOP: A LOW to HIGH transition on SDA while SCK is high

indicates a message STOP condition.

Reading From a Register

To read a register, the following protocol is used (see SMBus

2.0 specification):

IDLE: If SCK and SDA are both high for a time exceeding

tBUF from the last detected STOP condition or if they are high

for a total exceeding the maximum specification for tHIGH

then the bus will transfer to the IDLE state.

1) The Host drives a START condition, the 7-bit SMBus ad-

dress, and a “0” indicating a WRITE.

2) The Device (Slave) drives an ACK bit (“0”).

3) The Host drives the 8-bit Register Address.

4) The Device drives an ACK bit (“0”).

SMBus Transactions

A transaction begins with the host placing the DS25CP104A

SMBus into the START condition, then a byte (8 bits) is trans-

ferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’

to signify an ACK, or ‘1’ to signify NACK, after this the host

holds the SCL line low, and waits for the receiver to raise the

SDA line as an ACKnowledge that the byte has been re-

ceived.

5) The Host drives a START condition.

6) The Host drives the 7-bit SMBus Address, and a “1” indi-

cating a READ.

7) The Device drives an ACK bit “0”.

8) The Device drives the 8-bit data value (register contents).

9) The Host drives a NACK bit “1” indicating end of READ

transfer.

Writing to a Register

To write a register, the following protocol is used (see SMBus

2.0 specification):

10) The Host drives a STOP condition.

The READ transaction is completed, the bus goes Idle and

communication with other SMBus devices may now occur.

1) The Host drives a START condition, the 7-bit SMBus ad-

dress, and a “0” indicating a WRITE.

17

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Register Descriptions

There are five data registers in the DS25CP104A/DS25CP114 accessible via the SMBus interface.

TABLE 8. SMBus Data Registers

Address

(hex)

Name

Access

Description

0

1

2

3

4

Switch Configuration

PE Level Select

EQ Level Select

Control

R/W

RO

Switch Configuration Register

Transmit Pre-emphasis Level Select Register

Receive Equalization Level Select Register

Powerdown, LOS Enable and Pin Control Register

Loss Of Signal (LOS) Reporting Register

LOS

30073610

FIGURE 10. Registers Block Diagram

SWITCH CONFIGURATION REGISTER

The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register

mapping and associated truth table.

Bit

Default

00

Bit Name

Access

R/W

Description

D[1:0]

D[3:2]

D[5:4]

D[7:6]

Input Select 0

Input Select 1

Input Select 2

Input Select 3

Selects which input is routed to the OUT0.

Selects which input is routed to the OUT1.

Selects which input is routed to the OUT2.

Selects which input is routed to the OUT3.

00

R/W

00

R/W

00

R/W

TABLE 9. Switch Configuration Register Truth Table

Input Routed to the OUT0

D1

0

D0

0

IN0

IN1

IN2

IN3

0

1

0

1

The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.

The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based

on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state).

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18

PE LEVEL SELECT REGISTER

The PE Level Select register selects the pre-emphasis level for each of the outputs. The following two tables show the register

mapping and associated truth table.

Bit

Default

00

Bit Name

Access

R/W

Description

D[1:0]

D[3:2]

D[5:4]

D[7:6]

PE Level Select 0

PE Level Select 1

PE Level Select 2

PE Level Select 3

Sets pre-emphasis level on the OUT0.

Sets pre-emphasis level on the OUT1.

Sets pre-emphasis level on the OUT2.

Sets pre-emphasis level on the OUT3.

00

R/W

00

R/W

00

R/W

TABLE 10. PE Level Select Register Truth Table

Pre-Emphasis Level for the OUT0

D1

0

D0

0

Off

Low

0

1

0

Medium

High

1

NOTE: The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.

EQ LEVEL SELECT REGISTER

The EQ Level Select register selects the equalization level for each of the inputs. The following two tables show the register mapping

and associated truth table.

Bit

Default

00

Bit Name

Access

R/W

Description

D[1:0]

D[3:2]

D[5:4]

D[7:6]

EQ Level Select 0

EQ Level Select 1

EQ Level Select 2

EQ Level Select 3

Sets equalization level on the IN0.

Sets equalization level on the IN1.

Sets equalization level on the IN2.

Sets equalization level on the IN3.

00

R/W

00

R/W

00

R/W

TABLE 11. EQ Level Select Register Truth Table

Equalization Level for the IN0

D1

0

D0

0

Off

Low

0

1

0

Medium

High

1

NOTE: The truth tables for the IN1, IN2, and IN3 outputs are identical to this table.

19

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CONTROL REGISTER

The Control register enables SoftPWDN control, individual output power down (PWDNn) control, LOS Circuitry Enable control, PE

Level Select Enable control and EQ Level Select Enable control via the SMBus. The following table shows the register mapping.

Bit

Default

Bit Name

Access Description

D[3:0]

1111

PWDNn

R/W

Writing a [0] to the bit D[n] will power down the output OUTn

when either the PWDN pin OR the Control Register bit D[7]

(SoftPWDN) is set to a high [1].

D[4]

D[5]

D[6]

0

Ignore_External_EQ

Ignore_External_PE

EN_LOS

Writing a [1] to the bit D[4] will ignore the state of the external

EQ pins and will allow setting the EQ levels via the SMBus

interface.

Writing a [1] to the bit D[5] will ignore the state of the external

PE pins and will allow setting the PE levels via the SMBus

interface.

Writing a [1] to the bit D[6] will enable the LOS circuitry and

receivers on all four inputs. The SmartPWDN circuitry will not

disable any of the inputs nor any supporting LOS circuitry

depending on the switch configuration.

D[7]

0

SoftPWDN

R/W

Writing a [0] to the bit D[7] will place the device into the power

down mode. This pin is ORed together with the PWDN pin.

TABLE 12. Power Modes Truth Table

PWDNn Power Mode

PWDN

SoftPWDN

0

x

Power Down Mode. In this mode, all circuitry is shut down except the

minimum required circuitry for the LOS and SMBus Slave operation. The

SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs

in this mode by setting the EN_LOS bit to a [1].

0

1

0

1

x

Power Up Mode. In this mode, the SmartPWDN circuitry will automatically

power down any unused I/O and logic blocks and other supporting circuitry

depending on the switch configuration.

An output will be enabled only when the SmartPWDN circuitry indicates that

that particular output is needed for the particular switch configuration and

the respective PWDNn bit has logic high [1].

An input will be enabled when the SmartPWDN circuitry indicates that that

particular input is needed for the particular switch configuration or the

EN_LOS bit is set to a [1].

LOS REGISTER

The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.

Bit

Default

Bit Name

Access Description

D[0]

0

LOS0

RO

Reading a [0] from the bit D[0] indicates an open inputs fault condition on

the IN0. A [1] indicates presence of a valid signal.

D[1]

D[2]

0

LOS1

Reading a [0] from the bit D[1] indicates an open inputs fault condition on

the IN1. A [1] indicates presence of a valid signal.

0

LOS2

Reading a [0] from the bit D[2] indicates an open inputs fault condition on

the IN2. A [1] indicates presence of a valid signal.

D[3]

0

LOS3

Reading a [0] from the bit D[3] indicates an open inputs fault condition on

the IN3. A [1] indicates presence of a valid signal.

D[7:4]

0000

Reserved

Reserved for future use. Returns undefined value when read.

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20

INPUT INTERFACING

ommended that SMT resistors sized 0402 or smaller be used

and the mounting distance to the DS25CP114 pins kept under

200 mils.

The DS25CP104A/DS25CP114 accepts differential signals

and allows simple AC or DC coupling. With a wide common

mode range, the DS25CP104A/DS25CP114 can be DC-cou-

pled with all common differential drivers (i.e. LVPECL, LVDS,

CML). The following three figures illustrate typical DC-cou-

pled interface to common differential drivers.

When using the DS25CP114 in a limited multi-drop topology,

any transmission line stubs should be kept very short to min-

imize any negative effects on signal quality. A single termi-

nation resistor or resistor network that matches the differential

line impedance should be used. If DS25CP114 input pairs

from two separate devices are to be connected to a single

differential output, it is recommended that the DS25CP114

devices are mounted directly opposite of each other. One on

top of the PCB and the other directly under the first on the

bottom of the PCB, this keeps the distance between inputs

equal to the PCB thickness.

The DS25CP104A inputs are internally terminated with a

100Ω resistor for optimal device performance, reduced com-

ponent count, and minimum board space. External input ter-

minations on the DS25CP114 need to be placed as close as

possible to the device inputs to achieve equivalent AC per-

formance. When all four inputs are utilized it may be neces-

sary to alternate between the top and bottom layers to achieve

the minimum device input to termination distance. It is rec-

Typical LVDS Driver DC-Coupled Interface to DS25CP104A Inpu³t^0073631

30073632

Typical CML Driver DC-Coupled Interface to DS25CP104A Input

30073633

Typical LVPECL Driver DC-Coupled Interface to DS25CP104A Input

Note: DS25CP114 requires external 100Ω input termination.

21

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OUTPUT INTERFACING

impedance inputs. While most differential receivers have a

common mode input range that can accomodate LVDS com-

pliant signals, it is recommended to check respective

receiver's data sheet prior to implementing the suggested in-

terface implementation.

The DS25CP104A/DS25CP114 outputs signals that are com-

pliant to the LVDS standard. Its outputs can be DC-coupled

to most common differential receivers. The following figure

illustrates typical DC-coupled interface to common differential

receivers and assumes that the receivers have high

30073634

Typical Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver

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22

Typical Performance Characteristics

30073650

30073652

Total Jitter as a Function of Data Rate

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and EQ Level

30073651

30073653

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and EQ Level

30073654

30073656

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and PE Level

23

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30073657

30073655

Supply Current as a Function of Data Rate and PE Level

Residual Jitter as a Function of Data Rate, FR4 Stripline

Length and PE Level

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24

Typical Performance

30073662

30073663

A 2.5 Gbps NRZ PRBS-23 without PE

After 30" Differential FR-4 Stripline

H: 75 ps / DIV, V: 100 mV / DIV

A 3.125 Gbps NRZ PRBS-23 without PE

After 30" Differential FR-4 Stripline

H: 50 ps / DIV, V: 100 mV / DIV

30073660

A 2.5 Gbps NRZ PRBS-23 with High PE

After 2" Differential FR-4 Microstrip

H: 75 ps / DIV, V: 100 mV / DIV

A 3.125 Gbps NRZ PRBS-23 with ³H⁰⁰i⁷g³⁶h⁶¹PE

After 2" Differential FR-4 Microstrip

H: 50 ps / DIV, V: 100 mV / DIV

30073664

A 2.5 Gbps NRZ PRBS-23 with High PE

After 30" Differential FR-4 Stripline

H: 75 ps / DIV, V: 100 mV / DIV

A 3.125 Gbps NRZ PRBS-23 with ³H⁰⁰i⁷g³⁶h⁶⁵PE

After 30" Differential FR-4 Stripline

H: 50 ps / DIV, V: 100 mV / DIV

25

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30073667

30073666

A 3.125 Gbps NRZ PRBS-23 without EQ

After 60" Differential FR-4 Stripline

H: 50 ps / DIV, V: 100 mV / DIV

A 2.5 Gbps NRZ PRBS-23 without EQ

After 60" Differential FR-4 Stripline

H: 75 ps / DIV, V: 100 mV / DIV

30073669

30073668

A 3.125 Gbps NRZ PRBS-23 with High EQ

A 2.5 Gbps NRZ PRBS-23 with High EQ

After 60" Differential FR-4 Stripline

H: 75 ps / DIV, V: 100 mV / DIV

After 60" Differential FR-4 Stripline

H: 50 ps / DIV, V: 100 mV / DIV

www.national.com

26

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number DS25CP104ATSQ

Order Number DS25CP114TSQ

NS Package Number SQA40A

(See AN-1187 for PCB Design and Assembly Recommendations)

27

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型号：	DS25CP104ATSQ
厂家：	National Semiconductor
描述：	3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-Emphasis and Receive Equalization 3.125 Gbps的LVDS 4×4交叉点开关与发送预加重和接收均衡复用器开关复用器或开关信号电路输出元件
文件：	总28页 (文件大小：568K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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