DS42MB200 [NSC]

Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization; 双通道4.25 Gbps的2 ： 1/1 ： 2的CML复用器/缓冲器与发送预加重和接收均衡


型号：	DS42MB200
厂家：	National Semiconductor
描述：	Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization 双通道4.25 Gbps的2 ： 1/1 ： 2的CML复用器/缓冲器与发送预加重和接收均衡复用器
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December 7, 2007

DS42MB200

Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-

Emphasis and Receive Equalization

General Description

Features

The DS42MB200 is a dual signal conditioning 2:1 multiplexer

and 1:2 fan-out buffer designed for use in backplane redun-

dancy applications. Signal conditioning features include input

equalization and programmable output pre-emphasis that en-

able data communication in FR4 backplanes up to 4.25 Gbps.

Each input stage has a fixed equalizer to reduce ISI distortion

from board traces.

1– 4.25 Gbps fully differential data paths

■

Fixed input equalization

Programmable output pre-emphasis

Independent switch and line side pre-emphasis controls

Programmable switch-side loopback mode

On-chip terminations

All output drivers have 4 selectable steps of pre-emphasis to

compensate for transmission losses from long FR4 back-

planes and reduce deterministic jitter. The pre-emphasis lev-

els can be independently controlled for the line-side and

switch-side drivers. The internal loopback paths from switch-

side input to switch-side output enable at-speed system test-

ing. All receiver inputs and driver outputs are internally

terminated with 100Ω differential terminating resistors.

+3.3V supply

ESD rating HBM 6 kV

Lead-less LLP-48 package (7mmx7mmx0.8mm, 0.5mm

pitch)

■

–40°C to +85°C operating temperature range

■

Applications

Backplane driver or cable driver

■

Redundancy and signal conditioning applications

XAUI

Functional Block Diagram

20178633

201786

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Simplified Block Diagram

20178631

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Connection Diagram

20178632

Order number DS42MB200TSQ

See NS Package Number SQA48D

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Pin Descriptions

Pin Name Pin Number I/O

Description

LINE SIDE HIGH SPEED DIFFERENTIAL IO's

LI_0+

LI_0−

Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an

internal 50Ω connected to an internal reference voltage.

LO_0+

LO_0−

Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have

an internal 50Ω connected to V_CC

LI_1+

LI_1−

Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an

internal 50Ω connected to an internal reference voltage.

LO_1+

LO_1−

Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have

an internal 50Ω connected to V_CC

SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's

SOA_0+

SOA_0−

Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0

− have an internal 50Ω connected to V_CC

Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0

− have an internal 50Ω connected to V_CC

SOB_0+

SOB_0−

SIA_0+

SIA_0−

Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0

− have an internal 50Ω connected to an internal reference voltage.

SIB_0+

SIB_0−

Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0

− have an internal 50Ω connected to an internal reference voltage.

SOA_1+

SOA_1−

Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1

− have an internal 50Ω connected to V_CC

Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1

− have an internal 50Ω connected to V_CC

SOB_1+

SOB_1−

SIA_1+

SIA_1−

Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1

− have an internal 50Ω connected to an internal reference voltage.

SIB_1+

SIB_1−

Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1

− have an internal 50Ω connected to an internal reference voltage.

CONTROL (3.3V LVCMOS)

MUX_S0

A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state

for mux_0 is switch A.

MUX_S1

A logic low at MUX_S1 selects mux_1 to switch B. MUX_S0 is internally pulled high. Default state

for mux_1 is switch A.

PREL_0

PREL_1

PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and LO_1±).

PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasis levels.

PRES_0

PRES_1

PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±, SOB_0

±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4 for switch

side pre-emphasis levels.

LB0A

LB0B

LB1A

LB1B

RSV

A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is internally

pulled high.

A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is internally

pulled high.

A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is internally

pulled high.

A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is internally

pulled high.

Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND

through an external pull-down resistor.

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Pin Name Pin Number I/O

POWER

Description

V_CC

2, 8, 14, 20,

29, 35, 38,

V_CC= 3.3V ± 5%.

Each V_CCpin should be connected to the V_CCplane through a low inductance path, typically with a

via located as close as possible to the landing pad of the V_CCpin.

It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each V_CC

pin to ground plane.

GND

5, 11, 17, 32,

Ground reference. Each ground pin should be connected to the ground plane through a low

inductance path, typically with a via located as close as possible to the landing pad of the GND pin.

DAP

Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the LLP-48

package. It should be connected to the GND plane with at least 4 via to lower the ground impedance

and improve the thermal performance of the package.

Note: I = Input, O = Output, P = Power

parity. The DS42MB200 provides 4 steps of user-selectable

Functional Description

pre-emphasis ranging from 0, -3, -6 and –9 dB to handle dif-

ferent lengths of backplane. Figure 1 shows a driver pre-

emphasis waveform. The pre-emphasis duration is 200ps

nominal, corresponds to 0.75 bit-width at 4 Gbps. The pre-

emphasis levels of switch-side and line-side can be individu-

ally programmed.

The DS42MB200 is a signal conditioning 2:1 multiplexer and

a 1:2 buffer designed to support port redundancy up to 4.25

Gbps. Each input stage has a fixed equalizer that provides

equalization to compensate about 5 dB of transmission loss

from a short backplane trace (about 10 inches backplane).

The output driver has pre-emphasis (driver-side equalization)

to compensate the transmission loss of the backplane that it

is driving. The driver conditions the output signal such that the

lower frequency and higher frequency pulses reach approxi-

mately the same amplitude at the end of the backplane, and

minimize the deterministic jitter caused by the amplitude dis-

The high speed inputs are self-biased to about 1.5V and are

designed for AC coupling. The inputs are compatible to most

AC coupling differential signals such as LVDS, LVPECL and

CML.

TABLE 1. LOGIC TABLE FOR MULTIPLEX CONTROLS

MUX_S0

Mux Function

MUX_0 select switch_B input, SIB_0±.

MUX_0 select switch_A input, SIA_0±.

Mux Function

1 (default)

MUX_S1

MUX_1 select switch_B input, SIB_1±.

MUX_1 select switch_A input, SIA_0±.

1 (default)

TABLE 2. LOGIC TABLE FOR LOOPBACK Controls

LB0A

Loopback Function

Enable loopback from SIA_0± to SOA_0±.

Normal mode. Loopback disabled.

Loopback Function

1 (default)

LB0B

Enable loopback from SIB_0± to SOB_0±.

Normal mode. Loopback disabled.

Loopback Function

1 (default)

LB1A

Enable loopback from SIA_1± to SOA_1±.

Normal mode. Loopback disabled.

Loopback Function

1 (default)

LB1B

Enable loopback from SIB_1± to SOB_1±.

Normal mode. Loopback disabled.

1 (default)

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TABLE 3. LINE-SIDE PRE-EMPHASIS CONTROLS

Pre-Emphasis Level in De-Emphasis Level

Pre-Emphasis in dB Typical FR4 board

(VODPE/VODB) trace

mV_PP

(VODB)

in mV_PP

(VODPE)

PreL_[1:0]

0 0

1200

850

600

426

10 inches

0 1

−3

−6

−9

20 inches

30 inches

40 inches

1 0

1 1 (default)

TABLE 4. SWITCH-SIDE PRE-EMPHASIS CONTROLS

Pre-Emphasis Level in De-Emphasis Level

Pre-Emphasis in dB Typical FR4 board

mV_PP

in mV_PP

PreS_[1:0]

(VODPE/VODB)

trace

(VODB)

(VODPE)

0 0

1200

850

600

426

10 inches

0 1

−3

−6

−9

20 inches

30 inches

40 inches

1 0

1 1 (default)

20178637

FIGURE 1. Driver Pre-Emphasis Differential Waveform (showing all 4 pre-emphasis steps)

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Thermal Resistance,Φ_JB

18.2°C/W

6 kV

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ESD Rating HBM, 1.5 kΩ, 100 pF

ESD Rating Machine Model

250V

Recommended Operating Ratings

Supply Voltage (V_CC

)

−0.3V to 4V

−0.3V to (V_CC+0.3V)

+125°C

CMOS/TTL Input Voltage

CML Input/Output Voltage

Junction Temperature

Storage Temperature

Lead Temperature

Soldering, 4 sec

Min Typ Max Units

Supply Voltage (V_CC-GND)

3.13 3.3 3.465

−65°C to +150°C

Supply Noise Amplitude

10 Hz to 2 GHz

mV_PP

+260°C

33.7°C/W

20.7°C/W

5.8°C/W

Ambient Temperature

Case Temperature

-40

°C

Thermal Resistance, θ_JA

100

Thermal Resistance, θ_JC-top

Thermal Resistance, θ_JC-bottom

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Typ

(Note 2)

Symbol

Parameter

Conditions

Min

Max

Units

LVCMOS DC SPECIFICATIONS

V_IH

V_IL

I_IH

High Level Input

Voltage

V_CC+0.3

0.8

2.0

Low Level Input

Voltage

−0.3

High Level Input

Current

V_IN= V_CC

−10

µA

I_IL

Low Level Input Current V_IN= GND

Pull-High Resistance

124

µA

R_PU

kΩ

RECEIVER SPECIFICATIONS

V_ID

Differential Input

Voltage Range

AC Coupled Differential Signal

Below 1.25 Gbps

At 1.25 Gbps–3.125 Gbps

Above 3.125 Gbps

ꢀ

100

ꢀ

mV_P-P

1750

1560

1200

ꢀ

This parameter is not production tested.

ꢀ

V_ICM

R_ITD

R_ITSE

Common Mode Voltage Measured at receiver inputs reference to ground.

at Receiver Inputs

1.3

100

Input Differential

Termination

On-chip differential termination between IN+ or IN

−.

116

Ω

Input Termination

(single-end)

On-chip termination IN+ or IN− to GND for

frequency > 100 MHz.

DRIVER SPECIFICATIONS

VODB

Output Differential

Voltage Swing without

Pre-Emphasis

R_L= 100Ω ±1%

PRES_1=PRES_0=0

PREL_1=PREL_0=0

mV_P-P

1000

1200

1400

Driver pre-emphasis disabled.

Running K28.7 pattern at 4.25 Gbps.

See Figure 5 for test circuit.

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Typ

(Note 2)

Symbol

V_PE

Parameter

Conditions

Min

Max

Units

Output Pre-Emphasis

Voltage Ratio

20*log(VODPE/VODB)

R_L= 100Ω ±1%

ꢀ

−3

−6

−9

ꢀ

Running K28.7 pattern at 4.25 Gbps

PREx_[1:0]=00

PREx_[1:0]=01

PREx_[1:0]=10

PREx_[1:0]=11

x=S for switch side pre-emphasis control

x=L for line side pre-emphasis control

See Figure 1 on waveform.

See Figure 5 for test circuit.

t_PE

Pre-Emphasis Width

(Note 8)

Tested at −9 dB pre-emphasis level, PREx[1:0]=11

x=S for switch side pre-emphasis control

x=L for line side pre-emphasis control

125

200

250

See Figure 4 on measurement condition.

R_OTSE

R_OTD

Output Termination

On-chip termination from OUT+ or OUT− to V_CC

Ω

Output Differential

Termination

On-chip differential termination between OUT+ and

OUT−

100

Mis-Match in Output

Termination Resistors

Mis-match in output terminations at OUT+ and OUT

−

ΔR_OTSE

V_OCM

Output Common Mode

Voltage

2.4

2.9

POWER DISSIPATION

P_D

Power Dissipation

V_DD= 3.465V

All outputs terminated by 100Ω ±1%.

PREL_[1:0]=0, PRES_[1:0]=0

Running PRBS 2⁷-1 pattern at 4.25 Gbps

AC CHARACTERISTICS

t_R

Differential Low to High Measured with a clock-like pattern at 100 MHz,

Transition Time

between 20% and 80% of the differential output

voltage. Pre-emphasis disabled.

Transition time is measured with fixture as shown

in Figure 5, adjusted to reflect the transition time at

the output pins.

t_F

Differential High to Low

Transition Time

t_PLH

t_PHL

Differential Low to High Measured at 50% differential voltage from input to

0.5

Propagation Delay

output.

Differential High to Low

Propagation Delay

t_SKP

t_SKO

Pulse Skew (Note 8)

|t_PHL–t_PLH|

Output Skew

(Notes 7, 8)

Difference in propagation delay among data paths

in the same device.

200

t_SKPP

Part-to-Part Skew

(Note 8)

Difference in propagation delay between the same

output from devices operating under identical

condition.

500

t_SM

Mux Switch Time

Measured from V_IHor V_ILof the mux-control or

loopback control to 50% of the valid differential

output.

1.8

Device Random Jitter See Figure 5 for test circuit.

(Notes 5, 8)

Alternating-1-0 pattern.

Pre-emphasis disabled.

At 1.25 Gbps

psrms

At 4.25 Gbps

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Typ

(Note 2)

Symbol

Parameter

Conditions

See Figure 5 for test circuit.

Min

Max

Units

Device Deterministic

Jitter (Notes 6, 8)

Pre-emphasis disabled.

At 4.25 Gbps, PRBS7 pattern for DS42MB200@ –

40° to 85°C

pspp

DR_MAX

Maximum Data Rate

(Note 8)

Tested with alternating-1-0 pattern

4.25

Gbps

Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits.

Note 2: Typical parameters measured at V_CC= 3.3V, T_A= 25°C. They are for reference purposes and are not production-tested.

Note 3: IN+ and IN− are generic names refer to one of the many pairs of complimentary inputs of the DS42MB200. OUT+ and OUT− are generic names refer to

one of the many pairs of the complimentary outputs of the DS42MB200. Differential input voltage V_IDis defined as |IN+–IN−|. Differential output voltage V_ODis

defined as |OUT+–OUT−|.

Note 4: K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000}

K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010}

Note 5: Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJ_OUT²– RJ_IN²), where

RJ_OUTis the total random jitter measured at the output of the device in psrms, RJ_INis the random jitter of the pattern generator driving the device.

Note 6: Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ_OUT–DJ_IN), where

DJ_OUTis the total peak-to-peak deterministic jitter measured at the output of the device in pspp, DJ_INis the peak-to-peak deterministic jitter of the pattern generator

driving the device.

Note 7: t_SKOis the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and similar data paths

between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1

±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. t_SKOalso refers to

the delay skew of the loopback paths of the same port and between similar data paths between port 0 and port 1. An example is the output skew among data

paths SIA_0± to SOA_0±, SIB_0± to SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±.

Note 8: Guaranteed by desigh and characterization using statistical analysis.

Timing Diagrams

20178636

FIGURE 2. Driver Output Transition Time

20178635

FIGURE 3. Propagation Delay from input to output

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20178639

FIGURE 4. Test condition for output pre-emphasis duration

20178634

FIGURE 5. AC Test Circuit

The DS42MB200 input equalizer provides equalization to

compensate about 5 dB of transmission loss from a short

backplane transmission line. For characterization purposes,

a 25-inch FR4 coupled micro-strip board trace is used in place

of the short backplane link. The 25-inch microstrip board trace

has approximately 5 dB of attenuation between 375 MHz and

1.875 GHz, representing closely the transmission loss of the

short backplane transmission line. The 25-inch microstrip is

connected between the pattern generator and the differential

inputs of the DS42MB200 for AC measurements.

Dielectric Constant

Finished Trace

Width W

Separation between

Traces

Trace Length

Dielectric Height H

Loss Tangent

ε_R

25 inches

8.5 mil

11.5 mil

6 mil

3.8

0.022

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20178642

FIGURE 6. Data input and output eye patterns with driver set to 0 dB pre-emphasis

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20178643

FIGURE 7. Data input and output eye patterns with driver set to 9dB pre-emphasis

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Application Information

20178644

FIGURE 8. Application diagram (showing data paths of port 0)

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Physical Dimensions inches (millimeters) unless otherwise noted

LLP-48 Package

Order number DS42MB200TSQ

See NS Package Number SQA48D

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Notes

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DS42MB200 [NSC]

相关型号：

DS42MB200TSQ

DS42MB200TSQ/NOPB

DS42MB200_07

DS42MB200_14

DS430

DS4300D+

DS4300P+

DS4301

DS4301U-200

DS4301U-200

DS4301U-200/T&R

DS4301Z-200