DS42MB200TSQ/NOPB [TI]
Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer w/ Tx Pre-Emphasis & Rx Equalization 48-WQFN -40 to 85;
| 型号： | DS42MB200TSQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer w/ Tx Pre-Emphasis & Rx Equalization 48-WQFN -40 to 85 解复用器 逻辑集成电路 |
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DS42MB200
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SNOSAT8G –JANUARY 2006–REVISED APRIL 2013
DS42MB200 Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and
Receive Equalization
Check for Samples: DS42MB200
1
FEATURES
DESCRIPTION
The DS42MB200 is a dual signal conditioning 2:1
multiplexer and 1:2 fan-out buffer designed for use in
2
•
1– 4.25 Gbps Fully Differential Data Paths
Fixed Input Equalization
•
•
•
backplane
redundancy
applications.
Signal
Programmable Output Pre-emphasis
conditioning features include input equalization and
programmable output pre-emphasis that enable data
communication in FR4 backplanes up to 4.25 Gbps.
Each input stage has a fixed equalizer to reduce ISI
distortion from board traces.
Independent Switch and Line Side Pre-
emphasis Controls
•
•
•
•
•
Programmable Switch-side Loopback Mode
On-chip Terminations
All output drivers have 4 selectable steps of pre-
emphasis to compensate for transmission losses from
long FR4 backplanes and reduce deterministic jitter.
The pre-emphasis levels can be independently
controlled for the line-side and switch-side drivers.
The internal loopback paths from switch-side input to
switch-side output enable at-speed system testing. All
receiver inputs are internally terminated with 100Ω
differential terminating resistors. All driver outputs are
+3.3V Dupply
ESD Rating HBM 6 kV
Lead-less WQFN-48 Package
(7mmx7mmx0.8mm, 0.5mm Pitch)
•
–40°C to +85°C Operating Temperature Range
APPLICATIONS
internally terminated with 50Ω to VCC
.
•
•
Backplane Driver or Cable Driver
Redundancy and Signal Conditioning
Applications
•
XAUI
Functional Block Diagram
SIA_0 ±
SIB_0 ±
EQ
EQ
LO_0 ±
PRE_L
MUX_S0
LB0A
Port 0
SOA_0 ±
PRE_S
SOB_0 ±
LB0B
LI_0 ±
EQ
PRE_S
SIA_1 ±
SIB_1 ±
EQ
LO_1 ±
PRE_L
MUX_S1
EQ
LB1A
Port 1
SOA_1 ±
PRE_S
SOB_1 ±
LB1B
LI_1 ±
EQ
PRE_S
PreL_0
PreL_1
V
PRE_L
PRE_S
CC
Pre-emphasis
Control
PreS_0
PreS_1
GND
RSV
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS42MB200
SNOSAT8G –JANUARY 2006–REVISED APRIL 2013
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Simplified Block Diagram
DS42MB200
V
CC
1.5V
50
50
SIA_0+
SIA_0-
50
50
Inputstage
+EQ
LO_0+
M
U
X
CML
driver
LO_0-
SIB_0+
SIB_0-
Inputstage
+EQ
PRE_L
1.5V
50
50
MUX_S0
LB0A
V
CC
PORT 0
PRE_S
50
LB0B
50
SOA_0+
2
2
M
U
X
LI_0+
LI_0-
CML
driver
SOA_0-
Inputstage
+EQ
SOB_0+
SOB_0-
2
2
M
U
X
CML
driver
50
50
1.5V
50
50
PreL_0
PreL_1
PRE_L
PRE_S
PRE_S
Pre-emphasis
Control
V
CC
PreS_0
PreS_1
V
CC
1.5V
50
50
SIA_1+
SIA_1-
50
50
Inputstage
+EQ
LO_1+
M
U
X
CML
driver
LO_1-
SIB_1+
SIB_1-
Inputstage
+EQ
PRE_L
1.5V
50
50
MUX_S1
V
CC
PORT 1
LB1A
LB1B
PRE_S
50
50
2
2
SOA_1+
M
U
X
LI_1+
LI_1-
CML
driver
SOA_1-
Inputstage
+EQ
SOB_1+
SOB_1-
50
2
2
M
U
X
CML
driver
50
50
1.5V
50
PRE_S
GND pins
and DAP
V
CC
pins
V
CC
2
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Connection Diagram
48
47
46
45
44
43
42
41
40
39
38
37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PreL1
PreS0
V
V
CC
DAP = GND
CC
3
LO_0-
SOB_0-
SOB_0+
GND
4
LO_0+
GND
5
6
LI_1-
LI_0+
WQFN-48
Top View Shown
7
LI_1+
LI_0-
8
V
CC
V
CC
9
SOB_1+
SOB_1-
RSV
LO_1+
LO_1-
10
11
12
GND
PreL0
PreS1
13
14
15
16
17
18
19
20
21
22
23
24
Figure 1. See Package Number NJU0048D
PIN DESCRIPTIONS
Pin Name
Pin Number
I/O
Description
LINE SIDE HIGH SPEED DIFFERENTIAL IO's
LI_0+
LI_0−
6
7
I
Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an
internal 50Ω connected to an internal reference voltage. See Figure 7.
LO_0+
LO_0−
33
34
O
I
Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have an
internal 50Ω connected to VCC.
LI_1+
LI_1−
30
31
Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an
internal 50Ω connected to an internal reference voltage. See Figure 7.
LO_1+
9
O
Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have an
LO_1−
10
internal 50Ω connected to VCC.
SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's
SOA_0+
SOA_0−
46
45
O
O
I
Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0−
have an internal 50Ω connected to VCC
.
SOB_0+
SOB_0−
4
3
Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0−
have an internal 50Ω connected to VCC
.
SIA_0+
SIA_0−
40
39
Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
SIB_0+
SIB_0−
43
42
I
Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
SOA_1+
SOA_1−
22
21
O
O
Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1−
have an internal 50Ω connected to VCC
.
SOB_1+
SOB_1−
28
27
Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1−
have an internal 50Ω connected to VCC
.
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PIN DESCRIPTIONS (continued)
Pin Name
Pin Number
I/O
Description
SIA_1+
SIA_1−
16
15
I
Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
SIB_1+
SIB_1−
19
18
I
Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1−
have an internal 50Ω connected to an internal reference voltage. See Figure 7.
CONTROL (3.3V LVCMOS)
MUX_S0
37
I
I
I
I
A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state for
mux_0 is switch A.
MUX_S1
13
A logic low at MUX_S1 selects mux_1 to switch B. MUX_S1 is internally pulled high. Default state for
mux_1 is switch A.
PREL_0
PREL_1
12
1
PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and LO_1±).
PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasis levels.
PRES_0
PRES_1
36
25
PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±, SOB_0±,
SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4 for switch side
pre-emphasis levels.
LB0A
LB0B
LB1A
LB1B
RSV
47
48
23
24
26
I
I
I
I
I
A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is internally
pulled high.
A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is internally
pulled high.
A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is internally
pulled high.
A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is internally
pulled high.
Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND
through an external pull-down resistor.
POWER
VCC
2, 8, 14, 20,
29, 35, 38,
44
P
VCC = 3.3V ± 5%.
Each VCC pin should be connected to the VCC plane through a low inductance path, typically with a
via located as close as possible to the landing pad of the VCC pin.
It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin
to ground plane.
GND
GND
5, 11, 17, 32,
41
P
P
Ground reference. Each ground pin should be connected to the ground plane through a low
inductance path, typically with a via located as close as possible to the landing pad of the GND pin.
DAP
Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the WQFN-48
package. It should be connected to the GND plane with at least 4 via to lower the ground impedance
and improve the thermal performance of the package.
Functional Description
The DS42MB200 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up
to 4.25 Gbps. Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB of
transmission loss from a short backplane trace (about 10 inches backplane). The output driver has pre-emphasis
(driver-side equalization) to compensate the transmission loss of the backplane that it is driving. The driver
conditions the output signal such that the lower frequency and higher frequency pulses reach approximately the
same amplitude at the end of the backplane, and minimize the deterministic jitter caused by the amplitude
disparity. The DS42MB200 provides 4 steps of user-selectable pre-emphasis ranging from 0, -3, -6 and –9 dB to
handle different lengths of backplane. Figure 1 shows a driver pre-emphasis waveform. The pre-emphasis
duration is 200ps nominal, corresponds to 0.8 bit-width at 4 Gbps. The pre-emphasis levels of switch-side and
line-side can be individually programmed.
The high speed inputs are self-biased to about 1.5V and are designed for AC coupling allowing the DS42MB200
to be directly inserted into the datapath without any limitation. The ideal AC coupling capacitor value is often
based on the lowest frequency component embedded within the serial link. A typical AC coupling capacitor value
ranges between 100 and 1000nF, some specifications with scrambled data may require a larger coupling
capacitor for optimal performance. To reduce unwanted parasitics around and within the AC coupling capacitor, a
body size of 0402 is recommended. Figure 5 shows the AC coupling capacitor placement in an AC test circuit.
The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL and CML. See
Figure 7 for details.
4
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Table 1. LOGIC TABLE FOR MULTIPLEX CONTROLS
MUX_S0
0
Mux Function
MUX_0 select switch_B input, SIB_0±.
MUX_0 select switch_A input, SIA_0±.
Mux Function
1 (default)
MUX_S1
0
MUX_1 select switch_B input, SIB_1±.
MUX_1 select switch_A input, SIA_0±.
1 (default)
Table 2. LOGIC TABLE FOR LOOPBACK Controls
LB0A
0
Loopback Function
Enable loopback from SIA_0± to SOA_0±.
Normal mode. Loopback disabled.
Loopback Function
1 (default)
LB0B
0
Enable loopback from SIB_0± to SOB_0±.
Normal mode. Loopback disabled.
Loopback Function
1 (default)
LB1A
0
Enable loopback from SIA_1± to SOA_1±.
Normal mode. Loopback disabled.
Loopback Function
1 (default)
LB1B
0
Enable loopback from SIB_1± to SOB_1±.
Normal mode. Loopback disabled.
1 (default)
Table 3. LINE-SIDE PRE-EMPHASIS CONTROLS
De-Emphasis Level in
Pre-Emphasis Level in mVPP
Pre-Emphasis in dB
(VODPE/VODB)
Typical FR4 board
trace
PreL_[1:0]
mVPP
(VODPE)
(VODB)
0 0
0 1
1 0
1200
1200
1200
1200
1200
850
600
426
0
10 inches
−3
−6
−9
20 inches
30 inches
40 inches
1 1
(default)
Table 4. SWITCH-SIDE PRE-EMPHASIS CONTROLS
De-Emphasis Level in
Pre-Emphasis Level in mVPP
Pre-Emphasis in dB
(VODPE/VODB)
Typical FR4 board
trace
PreS_[1:0]
mVPP
(VODPE)
(VODB)
0 0
0 1
1 0
1200
1200
1200
1200
1200
850
600
426
0
10 inches
20 inches
30 inches
40 inches
−3
−6
−9
1 1
(default)
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1-bit
1 to N bits
1-bit
1 to N bits
0 dB
-3 dB
-6 dB
-9 dB
VODB
VODPE3
0V
VODPE2
VODPE1
Figure 2. Driver Pre-Emphasis Differential Waveform (showing all 4 pre-emphasis steps)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage (VCC
)
−0.3V to 4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
+125°C
CMOS/TTL Input Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 sec.)
Thermal Resistance, θJA
33.7°C/W
Thermal Resistance, θJC-top
Thermal Resistance, θJC-bottom
Thermal Resistance,ΦJB
20.7°C/W
5.8°C/W
18.2°C/W
ESD Rating HBM, 1.5 kΩ, 100 pF
ESD Rating Machine Model
6 kV
250V
(1) “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be verified. They are not meant to imply that
the device should be operated at these limits.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Ratings
Min
Typ
Max
3.465
20
Units
V
Supply Voltage (VCC-GND)
Supply Noise Amplitude (10 Hz to 2 GHz)
Ambient Temperature
3.135
3.3
mVPP
°C
-40
85
Case Temperature
100
°C
6
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Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIH
High Level Input
Voltage
2.0
VCC +0.3
0.8
V
V
Low Level Input
Voltage
−0.3
High Level Input
Current
VIN = VCC
−10
10
µA
IIL
Low Level Input Current VIN = GND
Pull-High Resistance
75
94
35
124
µA
RPU
kΩ
RECEIVER SPECIFICATIONS
VID
Differential Input
Voltage Range
AC Coupled Differential Signal
Below 1.25 Gbps
100
100
100
1750
1560
1200
mVP-P
mVP-P
mVP-P
At 1.25 Gbps–3.125 Gbps
Above 3.125 Gbps
This parameter is not production tested.
VICM
RITD
Common Mode Voltage Measured at receiver inputs reference to ground.
at Receiver Inputs
1.3
V
Input Differential
Termination
On-chip differential termination between IN+ or
84
100
116
Ω
IN−.(2)
DRIVER SPECIFICATIONS
VODB
Output Differential
Voltage Swing without
Pre-Emphasis
RL = 100Ω ±1%
PRES_1=PRES_0=0
PREL_1=PREL_0=0
1000
1200
1400
mVP-P
Driver pre-emphasis disabled.
Running K28.7 pattern at 4.25 Gbps.(3)
See Figure 6 for test circuit.
VPE
Output Pre-Emphasis
Voltage Ratio
RL = 100Ω ±1%
Running K28.7 pattern at 4.25 Gbps(3)
20*log(VODPE/VODB) PREx_[1:0]=00
PREx_[1:0]=01
0
dB
dB
dB
dB
−3
−6
−9
PREx_[1:0]=10
PREx_[1:0]=11
x=S for switch side pre-emphasis control
x=L for line side pre-emphasis control
See Figure 2 on waveform.
See Figure 6 for test circuit.
tPE
Pre-Emphasis Width(4) Tested at −9 dB pre-emphasis level, PREx[1:0]=11
x=S for switch side pre-emphasis control
125
42
200
250
58
ps
x=L for line side pre-emphasis control
See Figure 5 on measurement condition.
ROTSE
ROTD
Output Termination
On-chip termination from OUT+ or OUT− to VCC
50
Ω
Ω
Output Differential
Termination
On-chip differential termination between OUT+ and
OUT−
100
ΔROTSE
Mis-Match in Output
Termination Resistors
Mis-match in output terminations at OUT+ and
OUT−
5
%
V
VOCM
Output Common Mode
Voltage
2.4
2.9
(1) Typical parameters measured at VCC = 3.3V, TA = 25°C. They are for reference purposes and are not production-tested.
(2) IN+ and IN− are generic names refer to one of the many pairs of complimentary inputs of the DS42MB200. OUT+ and OUT− are
generic names refer to one of the many pairs of the complimentary outputs of the DS42MB200. Differential input voltage VID is defined
as |IN+–IN−|. Differential output voltage VOD is defined as |OUT+–OUT−|.
(3) K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000}K28.5 pattern is a 20-bit repeating pattern of +K28.5 and
−K28.5 code groups {110000 0101 001111 1010}
(4) Specified by desigh and characterization using statistical analysis.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Units
POWER DISSIPATION
PD
Power Dissipation
VDD = 3.465V
All outputs terminated by 100Ω ±1%.
PREL_[1:0]=0, PRES_[1:0]=0
1
W
Running PRBS 27-1 pattern at 4.25 Gbps
AC CHARACTERISTICS
tR
Differential Low to High Measured with a clock-like pattern at 100 MHz,
80
80
ps
ps
ns
Transition Time
between 20% and 80% of the differential output
voltage. Pre-emphasis disabled.
Transition time is measured with fixture as shown in
Figure 6, adjusted to reflect the transition time at the
output pins.
tF
Differential High to Low
Transition Time
tPLH
tPHL
Differential Low to High Measured at 50% differential voltage from input to
0.5
0.5
2
Propagation Delay
output.
Differential High to Low
Propagation Delay
2
ns
ps
ps
tSKP
tSKO
Pulse Skew(5)
|tPHL–tPLH
|
20
Output Skew(6)(5)
Difference in propagation delay among data paths in
the same device.
200
tSKPP
Part-to-Part Skew(5)
Difference in propagation delay between the same
output from devices operating under identical
condition.
500
6
ps
ns
tSM
Mux Switch Time
Measured from VIH or VIL of the mux-control or
loopback control to 50% of the valid differential
output.
1.8
RJ
Device Random
Jitter(7)(5)
See Figure 6 for test circuit.
Alternating-1-0 pattern.
Pre-emphasis disabled.
At 1.25 Gbps
2
2
psrms
psrms
At 4.25 Gbps
DJ
Device Deterministic
Jitter(8)(5)
See Figure 6 for test circuit.
Pre-emphasis disabled.
At 4.25 Gbps, PRBS7 pattern for DS42MB200@ –
40° to 85°C
35
pspp
DRMAX
Maximum Data Rate(5) Tested with alternating-1-0 pattern
4.25
Gbps
(5) Specified by desigh and characterization using statistical analysis.
(6) tSKO is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and
similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to
LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to
SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. tSKO also refers to the delay skew of the loopback paths of the same port and
between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to
SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±.
2
(7) Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJOUT
–
RJIN2), where RJOUT is the random jitter measured at the output of the device in psrms, RJIN is the random jitter of the pattern generator
driving the device.
(8) Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJOUT–DJIN), where DJOUT is the peak-to-peak deterministic jitter measured at the output of the device in pspp, DJIN is the peak-to-
peak deterministic jitter of the pattern generator driving the device.
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Timing Diagrams
80%
0V
80%
VODB
20%
20%
t
R
t
F
Figure 3. Driver Output Transition Time
50% VID
IN
t
t
PHL
PLH
50% VOD
OUT
Figure 4. Propagation Delay from input to output
1-bit
1 to N bits
1-bit
1 to N bits
t
PE
20%
-9 dB
80%
0V
VODPE3
Figure 5. Test condition for output pre-emphasis duration
Oscilloscope or
Jitter Measurement
Instrument
DS42MB200 Test Fixture
DC
Block
DC
Block
Pattern
Generator
V
CC
50W TL
DS42MB200
Coax
Coax
Coax
Coax
50+-1%
D+
D-
INPUT
25-inch
TLine
IN+
IN-
OUT+
OUT-
M
U
X
R
< 2"
EQ
D
1000 mVpp
Differential
GND
50 +-1%
50W TL
Figure 6. AC Test Circuit
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VCC
5k
IN+
IN -
50
50
1.5V
EQ
3.9k
180 pF
Figure 7. Receiver Input Termination and Biasing Circuit
APPLICATIONS INFORMATION
The DS42MB200 input equalizer provides equalization to compensate about 5 dB of transmission loss from a
short backplane transmission line. For characterization purposes, a 25-inch FR4 coupled micro-strip board trace
is used in place of the short backplane link. The 25-inch microstrip board trace has approximately 5 dB of
attenuation between 375 MHz and 1.875 GHz, representing closely the transmission loss of the short backplane
transmission line. The 25-inch microstrip is connected between the pattern generator and the differential inputs of
the DS42MB200 for AC measurements.
Finished Trace
Width W
Separation between
Traces
Dielectric Constant
Trace Length
Dielectric Height H
Loss Tangent
εR
25 inches
8.5 mil
11.5 mil
6 mil
3.8
0.022
Data eye from pattern generator
Data eye after 25-inch FR4 trace
Data eye after DS42MB200
50 ps/DIV
50 ps/DIV
50 ps/DIV
Pattern
Generator, 4 Gb/s
DS42MB200
PE=0dB
D
M
U
X
D+
IN+
IN-
OUT+
25-inch FR4
board trace
40-inch
R
EQ
D-
FR4 trace
OUT-
7
2 -1 pattern
50 ps/DIV
Figure 8. Data input and output eye patterns with driver set to 0 dB pre-emphasis
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Product Folder Links: DS42MB200
DS42MB200
SNOSAT8G –JANUARY 2006–REVISED APRIL 2013
Data eye after DS42MB200
www.ti.com
Data eye from pattern generator
Data eye after 25-inch FR4 trace
50 ps/DIV
50 ps/DIV
50 ps/DIV
Pattern
DS42MB200
IN+
Generator, 4 Gb/s
PE = 9 dB
M
U
X
D+
OUT+
OUT-
25-inch FR4
board trace
40-inch
FR4 trace
R
EQ
IN-
D
D-
7
2
-1 pattern
50 ps/DIV
Figure 9. Data input and output eye patterns with driver set to 9dB pre-emphasis
Passive Backplane
Line Cards
DS42MB200
SOA
SOB
SIA
LI
SerDes
HT
HR
TD
T_CLK
PHY
ASIC
RD
LO
R_CLK
SIB
REFCLK
Mux/Buf
Clock
Distribution
mC
ASIC or FPGA with integrated SerDes
Switch Card 2
Switch Card 1
SerDes
HT
TD
Switch
ASIC
T_CLK
RD
HR
R_CLK
REFCLK
Clock
Distribution
ASIC or FPGA with integrated SerDes
Figure 10. Application diagram (showing data paths of port 0)
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REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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Product Folder Links: DS42MB200
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
DS42MB200TSQ
ACTIVE
WQFN
WQFN
NJU
48
48
250
TBD
Call TI
SN
Call TI
-40 to 85
-40 to 85
DS42MB200TSQ/NOPB
ACTIVE
NJU
250
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
42MB200
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS42MB200TSQ/NOPB WQFN
NJU
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN NJU 48
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 55.0
DS42MB200TSQ/NOPB
250
Pack Materials-Page 2
MECHANICAL DATA
NJU0048D
SQA48D (Rev A)
www.ti.com
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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