DS78C120J [NSC]
Dual CMOS Compatible Differential Line Receiver; 双CMOS兼容差动线路接收器
| 型号： | DS78C120J |
| 厂家： | 
National Semiconductor |
| 描述： | Dual CMOS Compatible Differential Line Receiver |
| 文件： | 总10页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1996
DS78C120/DS88C120 Dual CMOS Compatible
Differential Line Receiver
General Description
Features
Y
Full compatibility with EIA Standards RS232-C, RS422
and RS423, Federal Standards 1020, 1030 and MIL-
188-114
The DS78C120 and DS88C120 are high performance, dual
differential, CMOS compatible line receivers for both bal-
anced and unbalanced digital data transmission. The inputs
are compatible with EIA, Federal and MIL standards.
Y
g
Input voltage range of 15V (differential or common-
mode)
Input specifications meet or exceed those of the popular
DS7820/DS8820 line receiver.
Y
Y
Y
Y
Y
Y
Y
Separate strobe input for each receiver
1/2 V
strobe threshold for CMOS compatibility
CC
g
The line receiver will discriminate a 200 mV input signal
over a common-mode range of 10V and a 300 mV sig-
5k typical input impedance
50 mV input hysteresis
200 mV input threshold
g
g
g
nal over a range of 15V.
Circuit features include hysteresis and response control for
applications where controlled rise and fall times and/or high
frequency noise rejection are desirable. Threshold offset
control is provided for fail-safe detection, should the input
be open or short. Each receiver includes a 180X terminating
resistor and the output gate contains a logic strobe for time
e
Operation voltage range
Separate fail-safe mode
4.5V to 15V
b
discrimination. The DS78C120 is specified over a 55 C to
§
a
a
125 C temperature range and the DS88C120 from 0 C to
§
70 C.
§
§
Connection Diagram
Dual-In-Line Package
TL/F/5801–1
Top View
Order Number DS88C120N
See NS Package Number N16A
For Complete Military 883 Specifications,
see RETS Data Sheet.
Order Number DS78C120J/883
See NS Package Number J16A
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/F/5801
RRD-B30M36/Printed in U. S. A.
http://www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
a
65 C to 150 C
Storage Temperature Range
§
§
Lead Temperature (Soldering, 4 seconds)
260 C
§
Supply Voltage
Input Voltage
18V
25V
18V
Operating Conditions
Min
4.5
Max
15
Units
V
g
Supply Voltage (V
)
CC
Strobe Voltage
Output Sink Current
Temperature (T )
A
50 mA
b
a
125
DS78C120
DS88C120
55
0
C
C
§
§
Maximum Power Dissipation* at 25 C
Cavity Package
Molded Package
§
a
70
1433 mW
1362 mW
b
a
Common-Mode Voltage (V
)
15
15
V
CM
*Derate cavity package 9.6 mW/ C above 25 C; derate molded package
§
§
10.9 mW/ C above 25 C.
§
§
Electrical Characteristics (Notes 2 and 3)
Symbol
Parameter
Conditions
Min
Typ
Max Units
s
s
7V
e b
b
b
b
b
b
V
Differential Threshold
Voltage
I
200 mA,
b
1.2V
7V
V
CM
0.06
0.06
0.2
0.3
V
V
V
V
TH
TL
OUT
t
V
V
CC
OUT
s
s
15V
15V
V
CM
s
s
s
7V
CM
e
b
b
V
Differential Threshold
Voltage
I
I
1.6 mA,V
OUT
0.5V
7V
V
0.08
0.08
0.2
0.3
OUT
OUT
s
s
15V
b
b
15V
V
CM
s
s
e b
V
V
Differential Threshold
Voltage Fail-Safe
200 mA,
b
1.2V
7V
V
CM
7V
TH
0.47
0.7
V
t
V
V
CC
OUT
s
s
V
s
e
e
b
Offset
Input Resistance
Line Termination Resistance T
5V
I
1.6 mA, V
0.5V
7V
7V
0.2
4
0.42
5
V
TL
OUT
OUT
CM
s
s
s
s
15V
CC
b
R
R
R
15V
V
15V, 0V
V
kX
X
IN
CM
e
25 C
§
100
180
56
2
300
3.1
T
A
e
s
Offset Control Resistance
T
25 C
§
kX
mA
O
A
s
e
e
I
Data Input Current
(Unterminated)
0V
V
CC
15V
V
CM
V
CM
V
CM
10V
0V
IND
b
b
0
0.5 mA
3.1 mA
e b
s
b
2
10V
t
s
e
b
V
THB
Input Balance
(Note 5)
I
200 mA, V
OUT
7V
V
CM
7V
7V
OUT
0.1
0.4
V
V
b
e
500X
V
1.2V, R
CC
S
s
s
s
e
b
I
1.6 mA, V
OUT
0.5V
7V
V
CM
OUT
b
b
0.1
0.4
e
R
500X
S
e b
e
b
b
0.75
CC
V
V
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Power Supply Current
I
I
200 mA, V
DIFF
1V
1V
V
1.2 V
V
V
OH
OUT
OUT
CC
e
e b
1.6 mA, V
0.25
8
0.5
OL
DIFF
s
s
b
0.5V (Both Receivers)
e
I
15V
V
CM
e b
15V,
V
V
5.5V
15V
15
30
mA
mA
CC
CC
V
DIFF
e
15
CC
e
e
e
3V
I
I
Logical ‘‘1’’ Strobe Input
Current
V
15V, V
DIFF
IN(1)
IN(0)
STROBE
15
100 mA
e b
3V
Logical ‘‘0’’ Strobe Input
Current
V
V
0V, V
DIFF
STROBE
b
b
100 mA
0.5
s
e
e
e
e
V
Logical ‘‘1’’ Strobe Input
Voltage
0.5V, I
OUT
1.6 mA
V
CC
V
CC
V
CC
5V
3.5
8.0
2.5
V
V
V
IH
OL
10V
15V
5.0
7.5
12.5
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2
Electrical Characteristics (Notes 2 and 3) (Continued)
Symbol
Parameter
Conditions
Min
Typ
2.5
5.0
7.5
Max Units
b
e
e
e
V
IL
Logical ‘‘0’’ Strobe Input
Voltage
V
V
1.2V,
V
CC
V
CC
V
CC
5V
1.5
2.0
2.5
V
V
OH CC
e b
I
200 mA
OUT
10V
15V
V
e
V
OUT
e
e
b
b
b
40
I
Output Short-Circuit Current
0V, V
CC
15V, V
STROBE
0V, (Note 4)
5
20
mA
OS
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
b
a
a
Note 2: Unless otherwise specified min/max limits apply across the 55 C to 125 C temperature range for the DS78C120 and across the 0 C to 70 C range
§
§
§
§
e
e
e
0V.
CM
for the DS88C120. All typical values for T
25 C, V
§
5V and V
A
CC
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Refer to EIA-RS422 for exact conditions.
e
e
25 C
Switching Characteristics V
5V, T
§
CC
A
Symbol
Parameter
Conditions
Min
Typ
60
Max
100
150
70
Units
ns
e
e
e
e
t
t
t
t
Differential Input to ‘‘0’’ Output
Differential Input to ‘‘1’’ Output
Strobe Input to ‘‘0’’ Output
Strobe Input to ‘‘1’’ Output
C
L
C
L
C
L
C
L
50 pF
50 pF
50 pF
50 pF
pd0(D)
pd1(D)
pd0(S)
pd1(S)
100
30
ns
ns
100
150
ns
AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal
*Includes probe and test fixture capacita
TL/F/5801–3
s
f
e
t
t
10 ns
r
e
PRR
1 MHz
TL/F/5801–4
Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).
3
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Schematic Diagram ((/2 Circuit Shown)
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4
Application Hints
Balanced Data Transmission
TL/F/5801–5
Unbalanced Data Transmission
TL/F/5801–6
Logic Level Translator
TL/F/5801–8
TL/F/5801–7
g
The DS78C120/DS88C120 may be used as a level transistor to interface between 12V MOS, ECL, TTL and CMOS. To configure, bias either input to a voltage
equal to (/2 the voltage of the input signal, and the other input to the driving gate.
5
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Application Hints (Continued)
LINE DRIVERS
Line drivers which will interface with the DS78C120/
DS88C120 are listed below.
Balanced Drivers
DS26LS31
Quad RS-422 Line Driver
Dual TTL
Dual TRI-STATE TTL
É
Dual TRI-STATE TTL
Quad RS-423/Dual RS-422 TTL
Quad RS-423/Dual TRI-STATE
RS-422 TTL
DS7830, DS8830
DS7831, DS8831
DS7832, DS8832
DS1691A, DS3691
DS1692, DS3692
DS3587, DS3487
Quad TRI-STATE RS-422
Unbalanced Drivers
DS1488
DS14C88
DS75150
Quad RS-232
Quad RS-232
Dual RS-232
TL/F/5801–9
RESPONSE CONTROL AND HYSTERESIS
FIGURE 1. Noise Pulse Width vs
Response Control Capacitor
In unbalanced (RS-232/RS-423) applications it is recom-
mended that the rise time and fall time of the line driver be
controlled to reduce cross-talk. Elimination of switching
noise is accomplished in the DS78C120/DS88C120 by the
50 mV of hysteresis incorporated in the output gate. This
eliminates the oscillations which may appear in a line receiv-
er due to the input signal slowly varying about the threshold
level for extended periods of time.
High frequency noise which is superimposed on the input
signal which may exceed 50 mV can be reduced in ampli-
tude by filtering the device input. On the DS78C120/
DS88C120, a high impedance response control pin in the
input amplifier is available to filter the input signal without
affecting the termination impedance of the transmission
line. Noise pulse width rejection vs the value of the re-
sponse control capacitor is shown in Figures 1 and 2. This
combination of filters followed by hysteresis will optimize
performance in a worse case noise environment.
TL/F/5801–10
TRANSMISSION LINE TERMINATION
On a transmission line which is electrically long, it is advisa-
ble to terminate the line in its characteristic impedance to
prevent signal reflection and its associated noise/cross-
talk.
A 180X termination resistor is provided in the
DS78C120/DS88C120 line receiver. To use the termination
resistor, connect pins 2 and 3 together and pins 13 and 14
together. The 180X resistor provides a good compromise
between line reflections, power dissipation in the driver, and
IR drop in the transmission line. If power dissipation and IR
drop are still a concern, a capacitor may be connected in
series with the resistor to minimize power loss.
TL/F/5801–11
FIGURE 2
The value of the capacitor is recommended to be the line
length (time) divided by 3 times the resistor value. Example:
if the transmission line is 1,000 feet long, (approximately
1000 ns) the capacitor value should be 1852 pF. For addi-
tional application details, refer to application notes AN-22
and AN-108.
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6
Application Hints (Continued)
performance of the receiver over its common-mode operat-
ing range, and will not change the input impedance balance
of the receiver.
FAIL-SAFE OPERATION
Communication systems require elements of a system to
detect the presence of signals in the transmission lines, and
it is desirable to have the system shut-down in a fail-safe
mode if the transmission line is open or shorted. To facilitate
the detection of input opens or shorts, the DS78C120/
DS88C120 incorporates an input threshold voltage offset.
This feature will force the line receiver to a specific logic
state if presence of either fault is a condition.
It is recommended that the receiver be terminated (500X or
less) to insure it will detect an open circuit in the presence
of noise.
The offset control can be used to insure fail-safe operation
for unbalanced interface (RS-423) or for balanced interface
(RS-422) operation.
For unbalanced operation, the receiver would be in an inde-
terminate logic state if the offset control input was open.
Connecting the offset to 5V offsets the receiver threshold
0.45V. The output is forced to a logic zero state if the input
is open or shorted.
g
Given that the receiver input threshold is 200 mV, an input
signal greater than 200 mV insures the receiver will be in
g
a specific logic state. When the offset control input (pins 1
e
offset from 200 mV to 700 mV, referred to the non-inverting
and 15) is connected to V
CC
5V, the input thresholds are
b
b
input, or 200 mV to 700 mV, referred to the inverting
input. Therefore, if the input is open or shorted, the input will
be greater than the input threshold and the receiver will
remain in a specified logic state.
For balanced operation with inputs shorted or open, receiv-
er C will be in an indeterminate logic state. Receivers A and
B will be in a logic zero state allowing the NOR gate to
detect the short or open condition. The strobe will disable
receivers A and B and may therefore be used to sample the
fail-safe detector. Another method of fail-safe detection
consists of filtering the output of the NOR gate D so it would
not indicate a fault condition when receiver inputs pass
through the threshold region, generating an output transient.
The input circuit of the receiver consists of a 5k resistor
terminated to ground through 120X on both inputs. This net-
work acts as an attenuator, and permits operation with com-
g
mon-mode input voltages greater than 15V. The offset
control input is actually another input to the attenuator, but
its resistor value is 56k. The offset control input is connect-
ed to the inverting input side of the attenuator, and the input
voltage to the amplifier is the sum of the inverting input plus
0.09 times the voltage on the offset control input. When the
offset control input is connected to 5V the input amplifier will
In a communications system, only the control signals are
required to detect input fault condition. Advantages of a bal-
anced data transmission system over an unbalanced trans-
mission system are:
1. High noise immunity
2. High data ratio
a
a
0.9V
see V
IN(INVERTING)
when the control input is connected to 10V. The offset con-
trol input will not significantly affect the differential
0.45V or V
IN(INVERTING)
3. Long line lengths
Unbalanced RS-423 and RS-232 Fail-Safe
TL/F/5801–12
7
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Application Hints (Continued)
Balanced RS-422 Fail-Safe
TL/F/5801–13
TL/F/5801–14
TL/F/5801–15
TL/F/5801–16
Truth Table (For Balanced Fail-Safe)
Input Strobe A-OUT B-OUT C-OUT D-OUT
0
1
X
0
1
X
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
X
0
0
0
0
0
1
0
0
0
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8
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number DS78C120J/883
NS Package Number J16A
9
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Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number DS88C120N
NS Package Number N16A
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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