DS90C124QVSX [NSC]
5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer; 5-35MHz直流平衡24位LVDS串行器和解串
| 型号： | DS90C124QVSX |
| 厂家： | 
National Semiconductor |
| 描述： | 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer |
| 文件： | 总26页 (文件大小：1040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 8, 2008
DS90C241/DS90C124
5-35MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS90C241/DS90C124 Chipset translates a 24-bit paral-
lel bus into a fully transparent data/control LVDS serial stream
with embedded clock information. This single serial stream
simplifies transferring a 24-bit bus over PCB traces and cable
by eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size
and pins.
User selectable clock edge for parallel data on both
Transmitter and Receiver
Internal DC Balancing encode/decode – Supports AC-
coupling interface with no external coding required
Individual power-down controls for both Transmitter and
Receiver
Embedded clock CDR (clock and data recovery) on
Receiver and no external source of reference clock
needed
All codes RDL (random data lock) to support live-
pluggable applications
■
■
■
■
■
The DS90C241/DS90C124 incorporates LVDS signaling on
the high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the serializer output edge rate for
the operating frequency range EMI is further reduced.
LOCK output flag to ensure data integrity at Receiver side
■
■
Balanced TSETUP/THOLD between RCLK and RDATA on
Receiver side
PTO (progressive turn-on) LVCMOS outputs to reduce
EMI and minimize SSO effects
All LVCMOS inputs and control pins have internal
pulldown
■
■
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
On-chip filters for PLLs on Transmitter and Receiver
Temperature range –40°C to +105°C
Greater than 8 kV HBM ESD tolerant
Meets AEC-Q100 compliance
■
■
■
■
■
■
Features
5 MHz–35 MHz clock embedded and DC-Balancing 24:1
■
and 1:24 data transmissions
User defined Pre-Emphasis driving ability through external
resistor on LVDS outputs and capable to drive up to 10
meters shielded twisted-pair cable
Power supply range 3.3V ± 10%
48-pin TQFP package
■
Block Diagram
20171901
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation
201719
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DS90C124
ꢀθJA
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
45.4 (4L*); 75.0 (2L*)°C/W
ꢀθJC
21.1°C/W
*JEDEC
ESD Rating (HBM)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to 3.9V
≥±8 kV
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature
(Soldering, 4 seconds)
ESD Rating (ISO10605)
RD = 2 kΩ, CS = 330 pF
DS90C241 meets ISO 10605
ꢀContact Discharge (DOUT+, DOUT-
)
±8 kV
−0.3V to 3.9V
ꢀAir Discharge (DOUT+, DOUT-
)
±25 kV
10 ms
+150°C
−65°C to +150°C
Recommended Operating
Conditions
+260°C
Min
Nom
Max
Units
Maximum Package Power Dissipation Capacity Package
De-rating:
Supply Voltage (VCC
)
3.0
3.3
3.6
V
Operating Free Air
Temperature (TA)
48L TQFP
DS90C241
ꢀθJA
1/θJA °C/W above +25°C
−40
5
+25
+105
35
±100
°C
MHz
mVP-P
Clock Rate
Supply Noise
45.8 (4L*); 75.4 (2L*) °C/W
21.0°C/W
ꢀθJC
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq.
LVCMOS/LVTTL DC SPECIFICATIONS
Min Typ Max Units
VIH
VIL
High Level Voltage
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
Rx: RPWDNB, RRFB,
REN
VCC
0.8
2.0
V
V
Low Level Input Voltage
Input Clamp Voltage
GND
VCL
ICL = −18 mA
(Note 9)
−0.8 −1.5
V
IIN
Input Current
VIN = 0V or 3.6V
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
−10
±5
+10
+20
µA
µA
Rx: RPWDNB, RRFB,
REN
−20
2.3
±5
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IOH = −4 mA
IOL = +4 mA
Rx: ROUT[23:0], RCLK,
LOCK
VCC
0.5
3.0
V
V
GND 0.33
VOUT = 0V
(Note 9)
−40 −70 −110
−30 ±0.4 +30
mA
µA
IOZ
TRI-STATE® Output Current
RPWDNB, REN = 0V
VOUT = 0V or 2.4V
Rx: ROUT[23:0], RCLK,
LOCK
LVDS DC SPECIFICATIONS
VTH
VTL
IIN
Differential Threshold High
Voltage
VCM = +1.2V
Rx: RIN+, RIN−
+50
mV
mV
Differential Threshold Low
Voltage
−50
Input Current
VIN = +2.4V,
±200
±200
µA
µA
VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V
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2
Symbol
Parameter
Conditions
Pin/Freq.
Min Typ Max Units
VOD
Output Differential Voltage
Tx: DOUT+, DOUT−
RL = 100Ω, w/o Pre-emphasis
VODSEL = L (Figure 10)
250 400
450 750 1200
10 50
1.00 1.25 1.50
600
mV
mV
mV
(DOUT+)–(DOUT−
)
RL = 100Ω, w/o Pre-emphasis
VODSEL = H (Figure 10)
Output Differential Voltage
Unbalance
ΔVOD
RL = 100Ω, w/o Pre-emphasis
VOS
Offset Voltage
RL = 100Ω, w/o Pre-emphasis
RL = 100Ω, w/o Pre-emphasis
V
Offset Voltage Unbalance
Output Short Circuit Current
ΔVOS
1
50
mV
IOS
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
−2
−8
mA
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
−7
−13
+15
mA
µA
IOZ
TRI-STATE Output Current
TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
−15
±1
40
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs
ICCT
Serializer (Tx)
Total Supply Current
(includes load current)
f = 35 MHz
RL = 100Ω
RPRE = OFF
65
mA
VODSEL = H/L
Checker-board pattern (Figure 1)
f = 35 MHz
RL = 100Ω
RPRE = 6 kΩ
VODSEL = H/L
Checker-board pattern (Figure 1)
45
40
45
70
65
70
mA
mA
mA
Serializer (Tx)
Total Supply Current
(includes load current)
f = 35 MHz
f = 35 MHz
RL = 100Ω
RPRE = OFF
VODSEL = H/L
RL = 100Ω
RPRE = 6 kΩ
VODSEL = H/L
Random pattern
ICCTZ
ICCR
Serializer (Tx)
Supply Current Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
800
85
µA
Deserializer (Rx)
Total Supply Current
(includes load current)
CL = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)
f = 35 MHz
f = 35 MHz
mA
Deserializer (Rx)
Total Supply Current
(includes load current)
CL = 8 pF LVCMOS Output
Random pattern
80
50
mA
µA
ICCRZ
Deserializer (Rx)
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
RIN+/ RIN- = 0V)
3
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Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Transmit Clock Period
Conditions
Min Typ Max Units
(Figure 5)
28.6
T
200
ns
ns
ns
ns
tTCIH
tTCIL
tCLKT
tJIT
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
0.4T 0.5T 0.6T
0.4T 0.5T 0.6T
(Figure 4)
3
6
(Note 10)
ps
(RMS)
33
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLLHT
tLHLT
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
0.6
ns
ns
ns
ns
RL = 100Ω, (Figure 3)
CL = 10 pF to GND
VODSEL = L
0.6
tDIS
tDIH
DIN (23:0) Setup to TCLK
DIN (23:0) Hold from TCLK
5
5
RL = 100Ω,
CL = 10 pF to GND
(Note 9)
tHZD
tLZD
tZHD
tZLD
tPLD
tSD
DOUT ± HIGH to TRI-STATE Delay
DOUT ± LOW to TRI-STATE Delay
DOUT ± TRI-STATE to HIGH Delay
DOUT ± TRI-STATE to LOW Delay
Serializer PLL Lock Time
15
15
ns
ns
ns
ns
ms
RL = 100Ω,
CL = 10 pF to GND
(Figure 6) (Note 5)
200
200
10
RL = 100Ω, (Figure 7)
Serializer Delay
RL = 100Ω, (Figure 8)
VODSEL = L, TRFB = H
3.5T
+ 10
3.5T + 2.85
3.5T + 2.85
ns
ns
UI
RL = 100Ω, (Figure 8)
VODSEL = L, TRFB = L
3.5T
+ 10
TxOUT_E_O
TxOUT_Eye_Opening
(respect to ideal)
5–35 MHz
(Figure 9)
(Notes 9, 10, 14)
0.75
(Note 11)
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Conditions
tRCP = tTCP
Pin/Freq.
RCLK
Min
28.6
45
Typ
Max
200
55
Units
ns
Receiver out Clock Period
(Note 9)
tRDC
tCLH
RCLK Duty Cycle
RCLK
50
%
LVCMOS Low-to-High
Transition Time
CL = 8 pF
ROUT [23:0],
LOCK, RCLK
2.5
3.5
ns
(lumped load)
(Figure 11)
(Note 9)
tCHL
tROS
tROH
tROS
tROH
LVCMOS High-to-Low
Transition Time
2.5
3.5
ns
ns
ns
ns
ns
ROUT (7:0) Setup Data to
RCLK (Group 1)
(Figure 15)
(Figure 15)
ROUT [7:0]
(0.40)*
tRCP
(29/56)*tRCP
(27/56)*tRCP
0.5*tRCP
ROUT (7:0) Hold Data to RCLK
(0.40)*
tRCP
(Group 1)
ROUT (15:8) Setup Data to
RCLK (Group 2)
ROUT [15:8],
LOCK
(0.40)*
tRCP
ROUT (15:8) Hold Data to
RCLK (Group 2)
(0.40)*
tRCP
0.5*tRCP
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4
Symbol
tROS
Parameter
Conditions
(Figure 15)
Pin/Freq.
Min
Typ
Max
Units
ROUT (23:16) Setup Data to
RCLK (Group 3)
ROUT [23:16]
(0.40)*
tRCP
(27/56)*tRCP
ns
tROH
ROUT (23:16) Hold Data to
RCLK (Group 3)
(0.40)*
tRCP
(29/56)*tRCP
ns
tHZR
tLZR
tZHR
tZLR
tDD
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
(Figure 13)
(Figure 12)
ROUT [23:0],
RCLK, LOCK
3
3
3
3
10
10
10
10
ns
ns
ns
ns
ns
RCLK
[4+(3/56)]T [4+(3/56)]T
+5.9
5
+14
50
tDRDL
Deserializer PLL Lock Time
from Powerdown
(Figure 14)
(Notes 8, 9)
5 MHz
ms
ms
35 MHz
5
50
RxIN_TOL_L Receiver INput TOLerance
Left,
(Figure 16)
(Notes 7, 9, 11)
5 MHz–35 MHz
0.25
0.25
UI
UI
RxIN_TOL_R Receiver INput TOLerance
Right,
(Figure 16)
(Notes 7, 9, 11)
5 MHz–35 MHz
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at VCC = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 6: tDRDL is the time required by the deserializer to obtain lock when exiting powerdown mode. tDRDL is specified with an external synchronization pattern.
Note 7: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 8: The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.
Note 9: Specification is guaranteed by characterization and is not tested in production.
Note 10: tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
Note 11: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 12: Figures 1, 2, 8, 12, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 13: Figures 5, 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 14: TxOUT_E_O is affected by pre-emphasis value.
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AC Timing Diagrams and Test Circuits
20171902
FIGURE 1. Serializer Input Checker-board Pattern
20171903
FIGURE 2. Deserializer Output Checker-board Pattern
20171904
FIGURE 3. Serializer LVDS Output Load and Transition Times
20171906
FIGURE 4. Serializer Input Clock Transition Times
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6
20171907
FIGURE 5. Serializer Setup/Hold Times
20171908
FIGURE 6. Serializer TRI-STATE Test Circuit and Delay
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20171909
FIGURE 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
20171910
FIGURE 8. Serializer Delay
20171915
FIGURE 9. Transmitter Output Eye Opening (TxOUT_E_O)
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8
20171917
VOD = (DOUT+) – (DOUT -
)
Differential output signal is shown as (DOUT+) – (DOUT -), device in Data Transfer mode.
FIGURE 10. Serializer VOD Diagram
20171905
FIGURE 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times
20171911
FIGURE 12. Deserializer Delay
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20171913
Note: CL includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing
20171914
FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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10
20171912
FIGURE 15. Deserializer Setup and Hold Times
20171916
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
FIGURE 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
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DS90C241 Serializer Pin Descriptions
Pin #
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
4-1,
DIN[23:0]
LVCMOS_I
Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float.
48-44,
41-32,
29-25
10
TCLK
LVCMOS_I
Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
CONTROL AND CONFIGURATION PINS
9
TPWDNB
LVCMOS_I
LVCMOS_I
LVCMOS_I
Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are
in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
18
23
DEN
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
PRE
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor value
determines pre-emphasis level. Recommended value RPRE ≥ 3 kΩ; Imax = [(1.2/R)*20], Rmin
3 kΩ
=
11
12
TRFB
LVCMOS_I
LVCMOS_I
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
VODSEL
VOD Level Select
VODSEL = L; LVDS Driver Output is ≈±400 mV (RL = 100Ω)
VODSEL = H; LVDS Driver Output is ≈±750 mV (RL = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
5
DCAOFF
DCBOFF
RESRVD
LVCMOS_I
LVCMOS_I
LVCMOS_I
Reserved. This pin MUST be tied LOW.
Reserved. This pin MUST be tied LOW.
Reserved. This pin MUST be tied LOW.
8
13
LVDS SERIAL INTERFACE PINS
20
DOUT+
LVDS_O
Transmitter LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the DOUT+ pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
19
DOUT−
LVDS_O
Transmitter LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the DOUT- pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
22
21
16
17
14
15
30
31
7
VDDDR
VSSDR
VDDPT0
VSSPT0
VDDPT1
VSSPT1
VDDT
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
Analog Voltage Supply, LVDS Output Power
Analog Ground, LVDS Output Ground
Analog Voltage supply, VCO Power
Analog Ground, VCO Ground
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Digital Voltage supply, Tx Serializer Power
Digital Ground, Tx Serializer Ground
Digital Voltage supply, Tx Logic Power
Digital Ground, Tx Logic Ground
VSST
VDDL
6
VSSL
42
VDDIT
Digital Voltage supply, Tx Input Power
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12
Pin #
43
24
Pin Name
VSSIT
VSS
I/O
Description
GND
GND
Digital Ground, Tx Input Ground
ESD Ground
DS90C241 Pin Diagram
Serializer - DS90C241
20171919
TOP VIEW
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DS90C124 Deserializer Pin Descriptions
Pin #
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
LVCMOS_O Receiver LVCMOS level Outputs – Group 1
LVCMOS_O Receiver LVCMOS level Outputs – Group 2
13-16, ROUT[15:8]
21-24
3-6,
ROUT[23:16] LVCMOS_O Receiver LVCMOS level Outputs – Group 3
9-12
18
RCLK LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43
RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48
REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB
LVCMOS_I
Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), ROUT[23-0], RCLK, and LOCK are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
17
2
LOCK
LVCMOS_O LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
RESRVD
LVCMOS_I
Reserved. This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
41
RIN+
LVDS_I
Receiver LVDS True (+) Input
This input is intended to be terminated with a 100Ω load to the RIN+ pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
42
RIN−
LVDS_I
Receiver LVDS Inverted (−) Input
This input is intended to be terminated with a 100Ω load to the RIN- pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
39
40
47
46
45
44
37
38
36
35
30
29
20
19
7
VDDIR
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
Analog LVDS Voltage supply, Power
Analog LVDS Ground
VSSIR
VDDPR0
VSSPR0
VDDPR1
VSSPR1
VDDR1
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL VCO Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
VSSR1
VDDR0
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
VSSR0
VDDOR1
VSSOR1
VDDOR2
VSSOR2
VDDOR3
VSSOR3
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
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14
DS90C124 Pin Diagram
Deserializer - DS90C124
20171920
TOP VIEW
15
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signal is synchronous to valid data appearing on the outputs.
The Deserializer’s LOCK pin is a convenient way to ensure
data integrity is achieved on receiver side.
Functional Description
The DS90C241 Serializer and DS90C124 Deserializer
chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial
LVDS link from 120 Mbps to 840 Mbps throughput. The
DS90C241 transforms a 24-bit wide parallel LVCMOS data
into a single high speed LVDS serial data stream with em-
bedded clock and scrambles / DC Balances the data to en-
hance signal quality to support AC coupling. The DS90C124
receives the LVDS serial data stream and converts it back into
a 24-bit wide parallel data and recovered clock. The 24-bit
Serializer/Deserializer chipset is designed to transmit data up
to 10 meters over shielded twisted pair (STP) at clock speeds
from 5 MHz to 35 MHz.
DATA TRANSFER
After Serializer lock is established, the inputs DIN0–DIN23
may be used to input data to the Serializer. Data is clocked
into the Serializer by the TCLK input. The edge of TCLK used
to strobe the data is selectable via the TRFB pin. TRFB high
selects the rising edge for clocking data and low selects the
falling edge. The Serializer outputs (DOUT±) are intended to
drive point-to-point connections as shown in Figure 17.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted
along the single LVDS serial data stream. The CLK1 bit is
always high and the CLK0 bit is always low. The CLK1 and
CLK0 bits function as the embedded clock bits in the serial
stream. DCB functions as the DC Balance control bit. It does
not require any pre-coding of data on transmit side. The DC
Balance bit is used to minimize the short and long-term DC
bias on the signal lines. This bit operates by selectively send-
ing the data either unmodified or inverted. The DCA bit is used
to validate data integrity in the embedded data stream. Both
DCA and DCB coding schemes are integrated and automat-
ically performed within Serializer and Deserializer.
The Deserializer can attain lock to a data stream without the
use of a separate reference clock source; greatly simplifying
system complexity and overall cost. The Deserializer syn-
chronizes to the Serializer regardless of data pattern, deliv-
ering true automatic “plug and lock” performance. It will lock
to the incoming serial stream without the need of special
training patterns or sync characters. The Deserializer recov-
ers the clock and data by extracting the embedded clock
information and validating data integrity from the incoming
data stream and then deserializes the data. The Deserializer
monitors the incoming clock information, determines lock sta-
tus, and asserts the LOCK output high when lock occurs.
Each has a power down control to enable efficient operation
in various applications.
Serialized data and clock/control bits (24+4 bits) are trans-
mitted from the serial data output (DOUT±) at 28 times the
TCLK frequency. For example, if TCLK is 35 MHz, the serial
rate is 35 x 28 = 980 Mega bits per second. Since only 24 bits
are from input data, the serial “payload” rate is 24 times the
TCLK frequency. For instance, if TCLK = 35 MHz, the payload
data rate is 35 x 24 = 840 Mbps. TCLK is provided by the data
source and must be in the range of 5 MHz to 35 MHz nominal.
The Serializer outputs (DOUT±) can drive a point-to-point
connection. The outputs transmit data when the enable pin
(DEN) is high, TPWDNB is high. The DEN pin may be used
to TRI-STATE the outputs when driven low.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS90C241 and DS90C124 must be es-
tablished before each device sends or receives data. Initial-
ization refers to synchronizing the Serializer’s and
Deserializer’s PLL’s together. After the Serializers locks to the
input clock source, the Deserializer synchronizes to the Seri-
alizers as the second and final initialization step.
When the Deserializer channel attains lock to the input from
a Serializer, it drives its LOCK pin high and synchronously
delivers valid data and recovered clock on the output. The
Deserializer locks onto the embedded clock, uses it to gen-
erate multiple internal data strobes, and then drives the re-
covered clock to the RCLK pin. The recovered clock (RCLK
output pin) is synchronous to the data on the ROUT[23:0]
pins. While LOCK is high, data on ROUT[23:0] is valid. Oth-
erwise, ROUT[23:0] is invalid. The polarity of the RCLK edge
is controlled by the RRFB input. ROUT(0-23), LOCK and
RCLK outputs will each drive a maximum of 8 pF load with a
35 MHz clock. REN controls TRI-STATE for ROUTn and the
RCLK pin on the Deserializer.
Step 1: When VCC is applied to both Serializer and/or Dese-
rializer, the respective outputs are held in TRI-STATE and
internal circuitry is disabled by on-chip power-on circuitry.
When VCC reaches VCC OK (2.2V) the PLL in Serializer begins
locking to a clock input. For the Serializer, the local clock is
the transmit clock, TCLK. The Serializer outputs are held in
TRI-STATE while the PLL locks to the TCLK. After locking to
TCLK, the Serializer block is now ready to send data patterns.
The Deserializer output will remain in TRI-STATE while its
PLL locks to the embedded clock information in serial data
stream. Also, the Deserializer LOCK output will remain low
until its PLL locks to incoming data and sync-pattern on the
RIN± pins.
Step 2: The Deserializer PLL acquires lock to a data stream
without requiring the Serializer to send special patterns. The
Serializer that is generating the stream to the Deserializer will
automatically send random (non-repetitive) data patterns dur-
ing this step of the Initialization State. The Deserializer will
lock onto embedded clock within the specified amount of time.
An embedded clock and data recovery (CDR) circuit locks to
the incoming bit stream to recover the high-speed receive bit
clock and re-time incoming data. The CDR circuit expects a
coded input bit stream. In order for the Deserializer to lock to
a random data stream from the Serializer, it performs a series
of operations to identify the rising clock edge and validates
data integrity, then locks to it. Because this locking procedure
is independent on the data pattern, total random locking du-
ration may vary. At the point when the Deserializer’s CDR
locks to the embedded clock, the LOCK pin goes high and
valid RCLK/data appears on the outputs. Note that the LOCK
RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-es-
tablish lock. For example, if the embedded clock edge is not
detected one time in succession, the PLL loses lock and the
LOCK pin is driven low. The Deserializer then enters the op-
erating mode where it tries to lock to a random data stream.
It looks for the embedded clock edge, identifies it and then
proceeds through the locking process. The logic state of the
LOCK signal indicates whether the data on ROUT is valid;
when it is high, the data is valid. The system must monitor the
LOCK pin to determine whether data on the ROUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the Se-
rializer and Deserializer may use to reduce power when no
data is being transferred. The TPWDNB and RPWDNB are
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16
used to set each device into power down mode, which re-
duces supply current to the µA range. The Serializer enters
powerdown when the TPWDNB pin is driven low. In power-
down, the PLL stops and the outputs go into TRI-STATE,
disabling load current and reducing supply. To exit Power-
down, TPWDNB must be driven high. When the Serializer
exits Powerdown, its PLL must lock to TCLK before it is ready
for the Initialization state. The system must then allow time for
Initialization before data transfer can begin. The Deserializer
enters powerdown mode when RPWDNB is driven low. In
powerdown mode, the PLL stops and the outputs enter TRI-
STATE. To bring the Deserializer block out of the powerdown
state, the system drives RPWDNB high.
tances, Pre-Emphasis may not be required. Signal quality
measurements are recommended to determine the proper
amount of Pre-Emphasis for each application.
AC-COUPLING AND TERMINATION
The DS90C241 and DS90C124 supports AC-coupled inter-
connects through integrated DC balanced encoding/decoding
scheme. To use AC coupled connection between the Serial-
izer and Deserializer, insert external AC coupling capacitors
in series in the LVDS signal path as illustrated in Figure 17.
The Deserializer input stage is designed for AC-coupling by
providing a built-in AC bias network which sets the internal
VCM to +1.2V. With AC signal coupling, capacitors provide the
ac-coupling path to the signal input.
Both the Serializer and Deserializer must reinitialize and re-
lock before data can be transferred. The Deserializer will
initialize and assert LOCK high when it is locked to the input
clock.
For the high-speed LVDS transmissions, the smallest avail-
able package should be used for the AC coupling capacitor.
This will help minimize degradation of signal quality due to
package parasitics. The most common used capacitor value
for the interface is 100 nF (0.1 uF) capacitor. NPO class 1 or
X7R class 2 type capacitors are recommended. 50 WVDC
should be the minimum used for the best system-level ESD
performance.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or
TPWDNB pin is driven low. This will TRI-STATE both driver
output pins (DOUT+ and DOUT−). When DEN is driven high,
the serializer will return to the previous state as long as all
other control pins remain static (TPWDNB, TRFB).
The DS90C124 input stage is designed for AC-coupling by
providing a built-in AC bias network which sets the internal
VCM to +1.2V. Therefore multiple termination options are
possible.
When you drive the REN or RPWDNB pin low, the Deserial-
izer enters TRI-STATE. Consequently, the receiver output
pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE.
The LOCK output remains active, reflecting the state of the
PLL. The Deserializer input pins are high impedance during
Receiver Termination Option 1
A single 100 Ohm termination resistor is placed across the
RIN± pins (see Figure 17). This provides the signal termina-
tion at the Receiver inputs. Other options may be used to
increase noise tolerance.
receiver powerdown (RPWDNB low) and power-off (VCC
0V).
=
PRE-EMPHASIS
Receiver Termination Option 2
The DS90C241 features a Pre-Emphasis function used to
compensate for long or lossy transmission media. Cable drive
is enhanced with a user selectable Pre-Emphasis feature that
provides additional output current during transitions to coun-
teract cable loading effects. The transmission distance will be
limited by the loss characteristics and quality of the media.
Pre-Emphasis adds extra current during LVDS logic transition
to reduce the cable loading effects and increase driving dis-
tance. In addition, Pre-Emphasis helps provide faster transi-
tions, increased eye openings, and improved signal integrity.
To enable the Pre-Emphasis function, the “PRE” pin requires
one external resistor (Rpre) to Vss in order to set the addi-
tional current level. Pre-Emphasis strength is set via an ex-
ternal resistor (Rpre) applied from min to max (floating to
3kΩ) at the “PRE” pin. A lower input resistor value on the
”PRE” pin increases the magnitude of dynamic current during
data transition. There is an internal current source based on
the following formula: PRE = (Rpre ≥ 3kΩ); IMAX = [(1.2/Rpre)
X 20]. The ability of the DS90C241 to use the Pre-Emphasis
feature will extend the transmission distance up to 10 meters
in most cases.
For additional EMI tolerance, two 50 Ohm resistors may be
used in place of the single 100 Ohm resistor. A small capacitor
is tied from the center point of the 50 Ohm resistors to ground
(see Figure 20). This provides
a high-frequency low
impedance path for noise suppression. Value is not critical,
4.7nF maybe used with general applications.
Receiver Termination Option 3
For high noise environments an additional voltage divider
network may be connected to the center point. This has the
advantage of a providing a DC low-impedance path for noise
suppression. Use resistor values in the range of 75Ω-2KΩ for
the pullup and pulldown. Ratio the resistor values to bias the
center point at 1.2V. For example (see Figure 21): VDD=3.3V,
Rpullup=1.3KΩ, Rpulldown=750Ω; or Rpullup=130Ω, Rpull-
down=75Ω (strongest). The smaller values will consume
more bias current, but will provide enhanced noise suppres-
sion.
PROGRESSIVE TURN–ON (PTO)
Deserializer ROUT[23:0] outputs are grouped into three
groups of eight, with each group switching about 0.5UI apart
in phase to reduce EMI, simultaneous switching noise, and
system ground bounce.
The amount of Pre-Emphasis for a given media will depend
on the transmission distance of the application. In general, too
much Pre-Emphasis can cause over or undershoot at the re-
ceiver input pins. This can result in excessive noise, crosstalk
and increased power dissipation. For short cables or dis-
17
www.national.com
receiver pair. Interconnect for LVDS typically has a differential
impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance
discontinuities. In most applications that involve cables, the
transmission distance will be determined on data rates in-
volved, acceptable bit error rate and transmission medium.
Applications Information
USING THE DS90C241 AND DS90C124
The
DS90C241/DS90C124
Serializer/Deserializer
(SERDES) pair sends 24 bits of parallel LVCMOS data over
a serial LVDS link up to 840 Mbps. Serialization of the input
data is accomplished using an on-board PLL at the Serializer
which embeds clock with the data. The Deserializer extracts
the clock/control information from the incoming data stream
and deserializes the data. The Deserializer monitors the in-
coming clockl information to determine lock status and will
indicate lock by asserting the LOCK output high.
LIVE LINK INSERTION
The Serializer and Deserializer devices support live plug-
gable applications. The automatic receiver lock to random
data “plug & go” hot insertion capability allows the DS90C124
to attain lock to the active data stream during a live insertion
event.
DISPLAY APPLICATION
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
The DS90C241/DS90C124 chipset is intended for interface
between a host (graphics processor) and a Display. It sup-
ports an 18-bit color depth (RGB666) and up to 800 X 480
display formats. In a RGB666 configuration 18 color bits (R
[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits
(VS, HS and DE) along with three spare bits are supported
across the serial link with PCLK rates from 5 to 35 MHz.
Circuit board layout and stack-up for the LVDS SERDES de-
vices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high fre-
quency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin di-
electrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven es-
pecially effective at high frequencies, and makes the value
and placement of external bypass capacitors less critical. Ex-
ternal bypass capacitors should include both RF ceramic and
tantalum electrolytic types. RF capacitors may use values in
the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be
in the 2.2 uF to 10 uF range. Voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage
being used.
TYPICAL APPLICATION CONNECTION
Figure 18 shows a typical application of the DS90C241 Seri-
alizer (SER). The LVDS outputs utilize a 100 ohm termination
and 100nF coupling capacitors to the line. Bypass capacitors
are placed near the power supply pins. A system GPO (Gen-
eral Purpose Output) controls the TPWDNB pin. In this appli-
cation the TRFB pin is tied High to latch data on the rising
edge of the TCLK. The DEN signal is not used and is tied High
also. In this application the link is short, therefore the VODSEL
pin is tied Low for the standard LVDS swing. The pre-empha-
sis input utilizes a resistor to ground to set the amount of pre-
emphasis desired by the application.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
Figure 19 shows a typical application of the DS90C124 De-
serializer (DES). The LVDS inputs utilize a 100 ohm termina-
tion and 100nF coupling capacitors to the line. Bypass
capacitors are placed near the power supply pins. A system
GPO (General Purpose Output) controls the RPWDNB pin. In
this application the RRFB pin is tied High to strobe the data
on the rising edge of the RCLK. The REN signal is not used
and is tied High also.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz range. To pro-
vide effective bypassing, multiple capacitors are often used
to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the slope
of the speed vs. ICC curve of CMOS designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably recover data. Various environmental and systematic fac-
tors include:
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
Serializer: TCLK jitter, VCC noise (noise bandwidth and
out-of-band noise)
Media: ISI, VCM noise
Deserializer: VCC noise
For a graphical representation of noise margin, please see
Figure 16.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS (LVTTL) signals away from the LVDS lines
to prevent coupling from the LVCMOS lines to the LVDS lines.
Closely-coupled differential lines of 100 Ohms are typically
recommended for LVDS interconnect. The closely coupled
TRANSMISSION MEDIA
The Serializer and Deserializer can be used in point-to-point
configuration, through a PCB trace, or through twisted pair
cable. In a point-to-point configuration, the transmission me-
dia needs be terminated at both ends of the transmitter and
www.national.com
18
lines help to ensure that coupled noise will appear as com-
mon-mode and thus is rejected by the receivers. The tightly
coupled lines will also radiate less.
—S = space between the pair
—2S = space between pairs
—3S = space to LVCMOS/LVTTL signal
•
•
Minimize the number of VIA
Use differential connectors when operating above
500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as
possible
Termination of the LVDS interconnect is required. For point-
to-point applications, termination should be located at both
ends of the devices. Nominal value is 100 Ohms to match the
line’s differential impedance. Place the resistor as close to the
transmitter DOUT± outputs and receiver RIN± inputs as pos-
sible to minimize the resulting stub between the termination
resistor and device.
•
•
•
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
20171918
FIGURE 17. AC Coupled Application
19
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20171921
FIGURE 18. DS90C241 Tyical Application Connection
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20
20171922
FIGURE 19. DS90C124 Tyical Application Connection
21
www.national.com
20171923
FIGURE 20. Receiver Termination Option 2
20171924
FIGURE 21. Receiver Termination Option 3
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22
Truth Tables
TABLE 1. DS90C241 Serializer Truth Table
TPWDNB
(Pin 9)
DEN
(Pin 18)
Tx PLL Status
(Internal)
LVDS Outputs
(Pins 19 and 20)
L
H
H
H
X
L
X
X
Hi Z
Hi Z
H
H
Not Locked
Locked
Hi Z
Serialized Data with Embedded Clock
TABLE 2. DS90C124 Deserializer Truth Table
Rx PLL Status
RPWDNB
(Pin 1)
REN
(Pin 48)
ROUTn and RCLK
LOCK
(Pin 17)
(Internal)
(See Pin Diagram)
L
X
L
X
X
Hi Z
Hi Z
Hi Z
H
L = PLL Unocked;
H = PLL Locked
H
H
H
H
Not Locked
Locked
Hi Z
L
Data and RCLK Active
H
23
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Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions show in millimeters only
NS Package Number VBC48A
Ordering Information
NSID
Package Type
Package ID
VBC48A
VBC48A
VBC48A
VBC48A
VBC48A
VBC48A
VBC48A
VBC48A
DS90C241QVS
DS90C241QVSX
DS90C241IVS
DS90C241IVSX
DS90C124QVS
DS90C124QVSX
DS90C124IVS
DS90C124IVSX
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch
48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel
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24
Notes
25
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Notes
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