DS90CF364A_07 [NSC]
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65MHz; + 3.3V LVDS接收器24位平板显示器（ FPD ）链路的65MHz ， + 3.3V LVDS接收器18位平板显示器（ FPD ）链路的65MHz
| 型号： | DS90CF364A_07 |
| 厂家： | 
National Semiconductor |
| 描述： | +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65MHz |
| 文件： | 总18页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2007
DS90CF384A/DS90CF364A
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link
—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display
(FPD) Link—65 MHz
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
General Description
The DS90CF384A receiver converts the four LVDS data
streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec
bandwidth) back into parallel 28 bits of CMOS/TTL data (24
Features
20 to 65 MHz shift clock support
■
■
■
■
bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also
available is the DS90CF364A that converts the three LVDS
data streams (Up to 1.3 Gbps throughput or 170 Megabytes/
sec bandwidth) back into parallel 21 bits of CMOS/TTL data
(18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both
Receivers' outputs are Falling edge strobe. A Rising edge or
Falling edge strobe transmitter (DS90C383A/DS90C363A)
will interoperate with a Falling edge strobe Receiver without
any translation logic.
50% duty cycle on receiver output clock
Best–in–Class Set & Hold Times on RxOUTPUTs
Rx power consumption <142 mW (typ) @65MHz
Grayscale
Rx Power-down mode <200μW (max)
■
■
■
■
■
■
■
ESD rating >7 kV (HBM), >700V (EIAJ)
Supports VGA, SVGA, XGA and Dual Pixel SXGA.
PLL requires no external components
The DS90CF384A / DS90CF364A devices are enhanced
over prior generation receivers and provided a wider data
valid time on the receiver output.
Compatible with TIA/EIA-644 LVDS standard
Low profile 56-lead or 48-lead TSSOP package
The DS90CF384A is also offered in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which provides a 44 % re-
duction in PCB footprint compared to the 56L TSSOP pack-
age.
DS90CF384A is also available in a 64 ball, 0.8mm fine
pitch ball grid array (FBGA) package
Block Diagrams
DS90CF384A
DS90CF364A
10087027
10087028
Order Number DS90CF384AMTD or DS90CF384ASLC
Order Number DS90CF364AMTD
See NS Package Number MTD48
See NS Package Number MTD56 or SLC64A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
100870
www.national.com
SLC (FBGA) Package:
DS90CF384A
Absolute Maximum Ratings (Note 1)
2.0 W
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Derating:
DS90CF384AMTD
DS90CF364AMTD
DS90CF384ASLC
ESD Rating
12.4 mW/°C above +25°C
15 mW/°C above +25°C
10.2 mW/°C above +25°C
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
+150°C
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
> 7 kV
> 700V
Storage Temperature
Lead Temperature
(Soldering, 4 sec)
Solder Reflow Temperature
(20 sec for FBGA)
Maximum Package Power
Dissipation Capacity @ 25°C
MTD56 (TSSOP) Package:
DS90CF384A
MTD48 (TSSOP) Package:
DS90CF364A
−65°C to +150°C
Recommended Operating
Conditions
+260°C
+220°C
Min Nom Max Units
Supply Voltage (VCC
Operating Free Air
Temperature (TA )
)
3.0
3.3
3.6
V
−10
0
+25
+70
2.4
°C
V
Receiver Input Range
1.61 W
1.89 W
Supply Noise Voltage (VCC
)
100
mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions
CMOS/TTL DC SPECIFICATIONS (For Power Down Pin)
Min
Typ
Max
Units
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
−0.79 −1.5
V
V IN = 0.4V, 2.5V or VCC
V IN = GND
+1.8
0
+10
μA
μA
−10
2.7
CMOS/TTL DC SPECIFICATIONS
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IOH = −0.4 mA
IOL = 2 mA
VOUT = 0V
3.3
0.06
−60
V
V
0.3
−120
mA
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V CM = +1.2V
+100
mV
mV
μA
−100
V IN = +2.4V, VCC = 3.6V
V IN = 0V, VCC = 3.6V
±10
±10
μA
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current
Worst Case
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
49
53
81
65
70
mA
mA
mA
Worst Case Pattern,
DS90CF384A (Figures 1,
105
4 )
ICCRW
Receiver Supply Current
Worst Case
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
49
53
78
55
60
90
mA
mA
mA
Worst Case Pattern,
DS90CF364A (Figures 1,
4 )
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2
Symbol
Parameter
Receiver Supply Current,
16 Grayscale
Conditions
Min
Typ
28
Max
45
Units
mA
mA
mA
μA
ICCRG
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
16 Grayscale Pattern,
(Figures 2, 3, 4 )
30
47
43
60
ICCRZ
Receiver Supply Current
Power Down
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
10
55
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ΔV OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
Parameter
Min
Typ
2
Max
5
Units
ns
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CMOS/TTL High-to-Low Transition Time (Figure 4 )
CHLT
1.8
1.96
5
ns
RSPos0
Receiver Input Strobe Position for Bit 0 (Figure 11,
f = 25 MHz
1.20
2.82
ns
Figure 12 )
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
6.91
12.62
18.33
24.04
29.75
35.46
0.7
7.67
13.38
19.09
24.80
30.51
36.22
1.1
8.53
14.24
19.95
25.66
31.37
37.08
1.4
ns
ns
ns
ns
ns
ns
ns
Receiver Input Strobe Position for Bit 0 (Figure 11,
f = 65 MHz
Figure 12 )
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 4) (Figure 13 )
2.9
5.1
7.3
9.5
11.7
13.9
750
500
15
3.3
5.5
3.6
5.8
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ms
μs
7.7
8.0
9.9
10.2
12.4
14.6
12.1
14.3
f = 25 MHz
f = 65 MHz
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
RxCLK OUT Period (Figure 5)
T
50
9.0
9.0
RxCLK OUT High Time (Figure 5 )
RxCLK OUT Low Time (Figure 5)
RxOUT Setup to RxCLK OUT (Figure 5 )
RxOUT Hold to RxCLK OUT (Figure 5 )
f = 65 MHz
5.0
5.0
4.5
4.0
3.5
7.6
6.3
7.3
6.3
5.0
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 6 )
Receiver Phase Lock Loop Set (Figure 7 )
7.5
10
1
Receiver Power Down Delay (Figure 10 )
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the DS90C383B transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). The RSKM will change when different
transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less
than 250 ps).
3
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AC Timing Diagrams
10087002
FIGURE 1. “Worst Case” Test Pattern
10087012
FIGURE 2. “16 Grayscale” Test Pattern (DS90CF384A)(Notes 5, 6, 7, 8)
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4
10087003
FIGURE 3. “16 Grayscale” Test Pattern (DS90CF364A)(Notes 5, 6, 7, 8)
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
10087004
FIGURE 4. DS90CF384A/DS90CF364A (Receiver) CMOS/TTL Output Load and Transition Times
10087005
FIGURE 5. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times
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10087006
FIGURE 6. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay
10087007
FIGURE 7. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time
10087009
FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A
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6
10087010
FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A
10087008
FIGURE 10. DS90CF384A/DS90CF364A (Receiver) Power Down Delay
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10087025
FIGURE 11. DS90CF384A (Receiver) LVDS Input Strobe Position
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8
10087026
FIGURE 12. DS90CF364A (Receiver) LVDS Input Strobe Position
9
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10087011
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Note 9: Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
Note 10: ISI is dependent on interconnect length; may be zero.
FIGURE 13. Receiver LVDS Input Skew Margin
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10
DS90CF384A Pin Descriptions — 56L TSSOP Package — 24-Bit FPD Link
Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
O
I
I
GND
I
PLL VCC
I
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
DS90CF364A Pin Descriptions — 48L TSSOP Package — 18-Bit FPD Link
Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
3
3
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
O
I
I
GND
I
PLL VCC
I
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
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DS90CF384A Pin Summary — 64 ball FBGA Package — FPD Link
Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
6
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Also known as FPSHIFT OUT
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
O
I
I
GND
I
Ground pins for TTL outputs.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
NC
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
Pins not connected.
DS90CF384A Pin Descriptions — 64 ball FBGA Package — FPD Link
Receiver
By Pin
Pin Name
RxOUT17
VCC
By Pin Type
Pin Name
GND
Pin
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
Type
O
Pin
A4
B1
B6
D8
E3
E5
G3
G7
H5
F6
G8
E6
H6
H7
H2
H3
F4
G4
G5
F5
G6
H8
E7
E8
C8
D5
Type
G
G
G
G
G
G
G
G
G
G
G
I
P
GND
RxOUT15
GND
O
GND
G
GND
RxOUT12
RxOUT8
RxOUT7
RxOUT6
GND
O
GND
O
LVDS GND
LVDS GND
LVDS GND
LVDS GND
PLL GND
PLL GND
PWR DWN
RxCLKIN-
RxCLKIN+
RxIN0-
O
O
G
NC
RxOUT16
RxOUT11
VCC
O
O
P
I
GND
G
O
O
O
I
RxOUT5
RxOUT3
RxOUT21
NC
I
RxIN0+
I
RxIN1-
I
RxIN1+
I
RxOUT18
RxOUT14
RxOUT9
RxOUT4
NC
O
O
O
O
RxIN2-
I
RxIN2+
I
RxIN3-
I
RxIN3+
I
RxCLKOUT
RxOUT0
RxOUT1
RxOUT10
O
O
O
O
RxOUT1
VCC
O
P
RxOUT20
O
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By Pin
RxOUT19
RxOUT13
RxOUT10
VCC
By Pin Type
RxOUT11
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
RxOUT17
RxOUT18
RxOUT19
RxOUT2
RxOUT20
RxOUT21
RxOUT22
RxOUT23
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
LVDS VCC
LVDS VCC
PLL VCC
VCC
D3
D4
D5
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
O
O
O
P
O
G
O
O
G
P
G
I
B4
A5
D4
C4
A3
B3
A1
C3
D3
D7
D2
C1
E1
F1
E2
G1
F2
H1
B8
C6
B7
A8
A7
A6
C5
E4
H4
F7
A2
B5
D1
D6
B2
C2
C7
F3
F8
G2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
RxOUT2
GND
RxOUT22
RxOUT24
GND
LVDS VCC
LVDS GND
PWR DWN
RxCLKOUT
RxOUT0
RxOUT23
RxOUT26
NC
O
O
O
O
RxIN1-
I
I
RxIN2+
PLL GND
PLL VCC
NC
G
P
RxOUT25
NC
O
LVDS GND
RxIN1+
G
I
RxIN2-
I
P
RxIN3-
I
P
LVDS GND
PLL GND
RxOUT27
RxIN0-
G
G
O
I
P
VCC
P
VCC
P
VCC
P
RxIN0+
I
NC
LVDS VCC
LVDS GND
RxCLKIN-
RxCLKIN+
RxIN3+
P
G
I
NC
NC
NC
I
NC
I
NC
G: Ground
I : Input
O: Output
P: Power
NC: Not connectted
13
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DS90CF364A
Pin Diagram for TSSOP Packages
DS90CF384A
10087013
10087023
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14
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Dimensions shown in millimeters only
Order Number DS90CF384AMTD
NS Package Number MTD56
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
Dimensions shown in millimeters only
Order Number DS90CF364AMTD
NS Package Number MTD48
15
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64 ball, 0.8mm Fine Pitch Ball Grid Array (FBGA) Package
Dimensions shown in millimeters only
Order Number DS90CF384ASLC
NS Package Number SLC64A
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16
Notes
17
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Notes
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NSC
DS90CF364MTD/NOPB
3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Linkâ65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Linkâ65 MHz
TI
DS90CF364MTDX/NOPB
+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz 48-TSSOP -40 to 85
TI
DS90CF364MTDX/NOPB
IC QUAD LINE RECEIVER, PDSO48, LOW PROFILE, PLASTIC, TSSOP-48, Line Driver or Receiver
NSC
DS90CF366
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link?85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link?85 MHz
NSC
DS90CF366MTD
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link?85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link?85 MHz
NSC
DS90CF366MTD/NOPB
+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz 48-TSSOP -10 to 70
TI
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