DS90CF383MTD [NSC]
+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) LinkΑ65 MHz; + 3.3V LVDS发射器24位平板显示器（ FPD ） LinkΑ65兆赫
| 型号： | DS90CF383MTD |
| 厂家： | 
National Semiconductor |
| 描述： | +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) LinkΑ65 MHz |
| 文件： | 总9页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2000
DS90CF383
+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD)
Link—65 MHz
General Description
Features
n 20 to 65 MHz shift clock support
n Single 3.3V supply
The DS90CF383 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 65 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughputs is 227 Mbytes/sec.
<
n Chipset (Tx + Rx) power consumption 250 mW (typ)
n Power-down mode ( 0.5 mW total)
<
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 227 Megabytes/sec bandwidth
n Up to 1.8 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Falling edge data strobe Transmitter
n Compatible with TIA/EIA-644 LVDS standard
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
>
n ESD rating 7 kV
n Operating Temperature: −40˚C to +85˚C
Block Diagram
DS90CF383
DS100033-1
Order Number DS90CF383MTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS100033
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Derating:
DS90CF383
12.5 mW/˚C above +25˚C
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
>
7 kV
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Recommended Operating
Conditions
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
Min Nom Max
3.0 3.3 3.6
Units
LVDS Output Short Circuit
Duration
Continuous
+150˚C
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
V
Junction Temperature
Storage Temperature
−65˚C to +150˚C
−40 +25 +85
2.4
˚C
V
Lead Temperature
(Soldering, 4 sec)
Receiver Input Range
0
+260˚C
Supply Noise Voltage (VCC
)
100 mVPP
@
Maximum Package Power Dissipation Capacity 25˚C
MTD56 (TSSOP) Package:
DS90CF383
1.63 W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = −0.4 mA
IOL = 2 mA
3.3
0.1
V
0.3
V
ICL = −18 mA
−0.79
−1.5
V
±
±
10
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
5.1
µA
mA
IOS
Output Short Circuit Current
−60
−120
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
250
345
450
35
mV
mV
∆VOD
Change in VOD between
complimentary output states
VOS
Offset Voltage (Note 4)
1.125
1.25
−3.5
1.375
35
V
∆VOS
Change in VOS between
complimentary output states
mV
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE® Current
VOUT = 0V, RL = 100Ω
−5
mA
µA
±
±
Power Down = 0V,
VOUT = 0V or VCC
1
10
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
VCM = +1.2V
+100
mV
mV
µA
−100
±
±
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
10
10
µA
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
ICCTZ
Transmitter Supply Current
Worst Case
RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figures 1, 3)
f = 32.5 MHz
31
32
42
23
28
31
10
45
mA
mA
mA
mA
mA
mA
µA
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
50
55
35
40
45
55
Transmitter Supply Current
16 Grayscale
RL = 100Ω,
CL = 5 pF,
16 Grayscale Pattern
(Figures 2, 3)
Transmitter Supply Current
Power Down
Power Down = Low
Driver Outputs in TRI-STATE® under
Power Down Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
www.national.com
2
Electrical Characteristics (Continued)
Note 2: Typical values are given for V
= 3.3V and T = +25C.
CC
A
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V and ∆V ).
OD
OD
Note 4:
V
previously referred as V .
CM
OS
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 3 )
LVDS High-to-Low Transition Time (Figure 3 )
TxCLK IN Transition Time (Figure 4 )
Min
Typ
0.75
0.75
Max Units
1.5
1.5
5
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TxOUT Channel-to-Channel Skew (Figure 5 )
Transmitter Output Pulse Position for Bit 0 (Figure 12 )
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 6)
250
0
f = 65 MHz
−0.4
1.8
0.3
2.5
2.2
4.4
6.6
8.8
11.0
13.2
T
4.0
4.7
6.2
6.9
8.4
9.1
10.6
12.8
15
11.3
13.5
50
TCIH
TxCLK IN High Time (Figure 6)
0.35T
0.35T
2.5
0.5T 0.65T
0.5T 0.65T
TCIL
TxCLK IN Low Time (Figure 6)
TSTC
TxIN Setup to TxCLK IN (Figure 6)
f = 65 MHz
THTC
TxIN Hold to TxCLK IN (Figure 6)
0
TCCD
TPLLS
TPDD
TxCLK IN to TxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 7 )
Transmitter Phase Lock Loop Set (Figure 8 )
Transmitter Power Down Delay (Figure 11)
3
5.5
10
100
AC Timing Diagrams
DS100033-4
FIGURE 1. “Worst Case” Test Pattern
3
www.national.com
AC Timing Diagrams (Continued)
DS100033-5
FIGURE 2. “16 Grayscale” Test Pattern (Notes 5, 6, 7, 8)
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
DS100033-6
FIGURE 3. DS90CF383 (Transmitter) LVDS Output Load and Transition Times
DS100033-8
FIGURE 4. DS90CF383 (Transmitter) Input Clock Transition Time
www.national.com
4
AC Timing Diagrams (Continued)
DS100033-9
Measurements at V = 0V
diff
TCCS measured between earliest and latest LVDS edges
→
TxCLK Differential Low
High Edge
FIGURE 5. DS90CF383 (Transmitter) Channel-to-Channel Skew
DS100033-10
FIGURE 6. DS90CF383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
DS100033-12
FIGURE 7. DS90CF383 (Transmitter) Clock In to Clock Out Delay
5
www.national.com
AC Timing Diagrams (Continued)
DS100033-14
FIGURE 8. DS90CF383 (Transmitter) Phase Lock Loop Set Time
DS100033-16
FIGURE 9. Seven Bits of LVDS in Once Clock Cycle
DS100033-17
FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
www.national.com
6
AC Timing Diagrams (Continued)
DS100033-18
FIGURE 11. Transmitter Power Down Delay
DS100033-26
FIGURE 12. Transmitter LVDS Output Pulse Position Measurement
DS90CF383 Pin Description— FPD Link Transmitter
Pin Name
TxIN
I/O No.
Description
I
28
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O
O
I
4
4
1
1
1
1
Positive LVDS differentiaI data output.
TxOUT−
Negative LVDS differential data output.
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
O
O
I
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
VCC
I
4
Power supply pins for TTL inputs.
7
www.national.com
DS90CF383 Pin Description— FPD Link Transmitter (Continued)
Pin Name
GND
I/O No.
Description
I
I
I
I
I
4
1
2
1
3
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Applications Information
The DS90CF383 and DS90CF384 are backward compatible
with the existing 5V FPD Link transmitter/receiver pair
(DS90CF583 and DS90CF584). To upgrade from a 5V to a
3.3V system the following must be addressed:
and receiver devices. This change may enable the re-
moval of a 5V supply from the system, and power may
be supplied from an existing 3V power source.
2. The DS90CF383 transmitter input and control inputs ac-
cept 3.3V TTL/CMOS levels. They are not 5V tolerant.
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL VCC of both the transmitter
Pin Diagram
DS90CF383
DS100033-23
Application
DS100033-3
www.national.com
8
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CF383MTD
NS Package Number MTD56
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
DS90CF383MTDX/NOPB
IC LINE DRIVER, PDSO56, LOW PROFILE, PLASTIC, TSSOP-56, Line Driver or Receiver
NSC
DS90CF384
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
NSC
DS90CF384A
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkΑ65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz
NSC
DS90CF384A
DS90CF384A/DS90CF364A 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz
TI
DS90CF384AMTD
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkΑ65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz
NSC
DS90CF384AMTDX
DS90CF384A/DS90CF364A 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz
TI
©2020 ICPDF网 联系我们和版权申明