DS90CF386SLCX/NOPB [NSC]
IC QUAD LINE RECEIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver;
| 型号： | DS90CF386SLCX/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC QUAD LINE RECEIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver 显示器 光电二极管 |
| 文件： | 总16页 (文件大小：782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2006
DS90CF386/DS90CF366
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link—85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel
Display (FPD) Link—85 MHz
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
General Description
The DS90CF386 receiver converts the four LVDS data
streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/
sec bandwidth) back into parallel 28 bits of CMOS/TTL data
Features
n 20 to 85 MHz shift clock support
(24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL).
Also available is the DS90CF366 that converts the three
LVDS data streams (Up to 1.78 Gbps throughput or 223
Megabytes/sec bandwidth) back into parallel 21 bits of
CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync
and DE). Both Receivers’ outputs are Falling edge strobe. A
Rising edge or Falling edge strobe transmitter (DS90C385/
DS90C365) will interoperate with a Falling edge strobe Re-
ceiver without any translation logic.
<
@
n Rx power consumption 142 mW (typ) 85MHz
Grayscale
n Rx Power-down mode 1.44 mW (max)
<
>
>
n ESD rating 7 kV (HBM), 700V (EIAJ)
n Supports VGA, SVGA, XGA and Single Pixel SXGA.
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
n DS90CF386 also available in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package
The DS90CF386 is also offered in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which provides a 44 %
reduction in PCB footprint compared to the 56L TSSOP
package.
Block Diagrams
DS90CF386
DS90CF366
10108527
10108528
Order Number DS90CF366MTD
Order Number DS90CF386MTD or DS90CF386SLC
See NS Package Number MTD56 or SLC64A
See NS Package Number MTD48
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS101085
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Absolute Maximum Ratings (Note 1)
DS90CF366MTD
15 mW/˚C above +25˚C
Maximum Package Power
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
@
Dissipation Capacity 25˚C
SLC64A Package:
DS90CF386SLC
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
+150˚C
2.0 W
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Package Derating:
DS90CF386SLC
ESD Rating
10.2 mW/˚C above +25˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
>
>
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
7 kV
(Soldering, 4 sec for TSSOP)
Solder Reflow Temperature
(Soldering, 20 sec for FBGA)
Maximum Package Power
+260˚C
+220˚C
700V
Recommended Operating
Conditions
@
Dissipation Capacity 25˚C
MTD56 (TSSOP) Package:
DS90CF386MTD
Min Nom Max Units
1.61 W
1.89 W
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
3.0 3.3 3.6
V
MTD48 (TSSOP) Package:
DS90CF366MTD
−10 +25 +70
˚C
V
Package Derating:
Receiver Input Range
0
2.4
DS90CF386MTD
12.4 mW/˚C above +25˚C
Supply Noise Voltage (VCC
)
100 mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions
CMOS/TTL DC SPECIFICATIONS
Min
Typ
Max
Units
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
Input Current
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = - 0.4 mA
IOL = 2 mA
3.3
0.06
-0.79
+1.8
0
V
0.3
-1.5
+15
V
ICL = −18 mA
V
VIN = 0.4V, 2.5V or VCC
VIN = GND
uA
uA
mA
-10
IOS
Output Short Circuit Current
VOUT = 0V
-60
-120
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
I IN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
= +1.2V
+100
mV
mV
µA
CM
−100
V
V
= +2.4V, VCC = 3.6V
= 0V, VCC = 3.6V
10
10
IN
IN
µA
RECEIVER SUPPLY CURRENT
ICCRW
ICCRW
ICCRG
Receiver Supply Current
Worst Case
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
49
53
81
70
75
mA
mA
mA
Worst Case Pattern,
DS90CF386 (Figures 1, f = 65 MHz
114
4 )
f = 85 MHz
96
49
53
78
135
60
mA
mA
mA
mA
Receiver Supply Current
Worst Case
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
Worst Case Pattern,
65
DS90CF366 (Figures 1, f = 65 MHz
100
4 )
f = 85 MHz
90
28
30
115
45
mA
mA
mA
Receiver Supply Current,
16 Grayscale
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
16 Grayscale Pattern,
47
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2
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
(Figures 2, 3, 4 )
Power Down = Low
Min
Typ
Max
Units
RECEIVER SUPPLY CURRENT
f = 65 MHz
f = 85 MHz
43
43
60
70
mA
mA
µA
ICCRZ
Receiver Supply Current
Power Down
140
400
Receiver Outputs Stay Low during
Power Down Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V and ∆V ).
OD
OD
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CMOS/TTL High-to-Low Transition Time (Figure 4 )
Receiver Input Strobe Position for Bit 0 (Figure 11,
Figure 12 )
Min
Typ
2.0
Max
3.5
Units
ns
CHLT
1.8
3.5
ns
RSPos0
f = 85 MHz
0.49
0.84
1.19
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 4) (Figure 13 )
RxCLK OUT Period (Figure 5)
2.17
3.85
5.53
7.21
8.89
10.57
290
11.76
4.5
2.52
4.20
5.88
7.56
9.24
10.92
2.87
4.55
6.23
7.91
9.59
11.27
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
µs
f = 85 MHz
f = 85 MHz
RCOP
T
5
5
50
7
RCOH
RCOL
RxCLK OUT High Time (Figure 5 )
RxCLK OUT Low Time (Figure 5)
4.0
6.5
RSRC
RxOUT Setup to RxCLK OUT (Figure 5 )
RxOUT Hold to RxCLK OUT (Figure 5 )
2.0
RHRC
3.5
@
RCCD
RxCLK IN to RxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 6 )
Receiver Phase Lock Loop Set (Figure 7 )
5.5
7.0
9.5
10
1
RPLLS
RPDD
Receiver Power Down Delay (Figure 10 )
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).
3
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AC Timing Diagrams
10108502
FIGURE 1. “Worst Case” Test Pattern
10108512
FIGURE 2. “16 Grayscale” Test Pattern (DS90CF386)(Notes 5, 6, 7, 8)
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4
AC Timing Diagrams (Continued)
10108503
FIGURE 3. “16 Grayscale” Test Pattern (DS90CF366)(Notes 5, 6, 7, 8)
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
10108504
FIGURE 4. DS90CF386/DS90CF366 (Receiver) CMOS/TTL Output Load and Transition Times
10108505
FIGURE 5. DS90CF386/DS90CF366 (Receiver) Setup/Hold and High/Low Times
5
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AC Timing Diagrams (Continued)
10108506
FIGURE 6. DS90CF386/DS90CF366 (Receiver) Clock In to Clock Out Delay
10108507
FIGURE 7. DS90CF386/DS90CF366 (Receiver) Phase Lock Loop Set Time
10108509
FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF386
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6
AC Timing Diagrams (Continued)
10108510
FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF366
10108508
FIGURE 10. DS90CF386/DS90CF366 (Receiver) Power Down Delay
7
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AC Timing Diagrams (Continued)
10108525
FIGURE 11. DS90CF386 (Receiver) LVDS Input Strobe Position
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8
AC Timing Diagrams (Continued)
10108526
FIGURE 12. DS90CF366 (Receiver) LVDS Input Strobe Position
9
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AC Timing Diagrams (Continued)
10108511
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 9) + ISI (Inter-symbol interference) (Note 10)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 9: Cycle-to-cycle jitter is less than 250 ps at 85 MHz.
Note 10: ISI is dependent on interconnect length; may be zero.
FIGURE 13. Receiver LVDS Input Skew Margin
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10
DS90CF386 MTD56 Package Pin Descriptions—24-Bit FPD Link Receiver
Pin Name
RxIN+
I/O
No.
4
Description
Positive LVDS differentiaI data inputs.
I
I
RxIN−
4
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control
lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data
Enable).
RxOUT
O
28
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V CC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
O
I
I
GND
I
Ground pins for TTL outputs.
PLL V CC
PLL GND
LVDS V CC
LVDS GND
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
DS90CF366 MTD48 Package Pin Descriptions—18-Bit FPD Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
3
3
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
21
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V CC
I
I
1
1
1
1
4
5
1
2
1
3
Negative LVDS differential clock input.
O
I
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
I
GND
I
Ground pins for TTL outputs.
PLL V CC
PLL GND
LVDS V CC
LVDS GND
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
DS90CF386 — 64 ball FBGA package Pin Descriptions —
FPD Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
28
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
Negative LVDS differential clock input.
O
I
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
I
GND
I
Ground pins for TTL outputs.
PLL VCC
I
Power supply for PLL.
PLL GND
LVDS VCC
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
11
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DS90CF386 — 64 ball FBGA package Pin Descriptions —
FPD Link Receiver (Continued)
Pin Name
LVDS GND
NC
I/O No.
Description
I
3
6
Ground pins for LVDS inputs.
Pins not connected.
DS90CF386 Pin Descriptions — 64 ball FBGA Package —
FPD Link Receiver
By Pin
Pin Name
RxOUT17
VCC
By Pin Type
Pin
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
Type
O
Pin
A4
B1
B6
D8
E3
E5
G3
G7
H5
F6
G8
E6
H6
H7
H2
H3
F4
G4
G5
F5
G6
H8
E7
E8
C8
D5
B4
A5
D4
C4
A3
B3
A1
C3
D3
D7
D2
C1
E1
F1
Pin Name
GND
Type
G
G
G
G
G
G
G
G
G
G
G
I
P
GND
RxOUT15
GND
O
GND
G
GND
RxOUT12
RxOUT8
RxOUT7
RxOUT6
GND
O
GND
O
LVDS GND
LVDS GND
LVDS GND
LVDS GND
PLL GND
PLL GND
PWR DWN
RxCLKIN-
RxCLKIN+
RxIN0-
O
O
G
NC
RxOUT16
RxOUT11
VCC
O
O
P
I
GND
G
O
O
O
I
RxOUT5
RxOUT3
RxOUT21
NC
I
RxIN0+
I
RxIN1-
I
RxIN1+
I
RxOUT18
RxOUT14
RxOUT9
RxOUT4
NC
O
O
O
O
RxIN2-
I
RxIN2+
I
RxIN3-
I
RxIN3+
I
RxCLKOUT
RxOUT0
RxOUT1
RxOUT10
RxOUT11
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
RxOUT17
RxOUT18
RxOUT19
RxOUT2
RxOUT20
RxOUT21
RxOUT22
RxOUT23
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
RxOUT1
VCC
O
P
O
O
O
O
P
O
G
O
O
G
P
G
I
RxOUT20
RxOUT19
RxOUT13
RxOUT10
VCC
RxOUT2
GND
RxOUT22
RxOUT24
GND
LVDS VCC
LVDS GND
PWR DWN
RxCLKOUT
RxOUT0
O
O
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12
DS90CF386 Pin Descriptions — 64 ball FBGA Package —
FPD Link Receiver (Continued)
By Pin
RxOUT23
RxOUT26
NC
By Pin Type
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
O
O
E2
G1
F2
H1
B8
C6
B7
A8
A7
A6
C5
E4
H4
F7
A2
B5
D1
D6
B2
C2
C7
F3
F8
G2
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
LVDS VCC
LVDS VCC
PLL VCC
VCC
O
O
O
O
O
O
O
O
O
O
O
P
RxIN1-
I
I
RxIN2+
PLL GND
PLL VCC
NC
G
P
RxOUT25
NC
O
LVDS GND
RxIN1+
G
I
RxIN2-
I
P
RxIN3-
I
P
LVDS GND
PLL GND
RxOUT27
RxIN0-
G
G
O
I
P
VCC
P
VCC
P
VCC
P
RxIN0+
I
NC
LVDS VCC
LVDS GND
RxCLKIN-
RxCLKIN+
RxIN3+
P
G
I
NC
NC
NC
I
NC
I
NC
G: Ground
I : Input
O: Output
P: Power
NC: Not connectted
13
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Pin Diagrams for TSSOP Packages
DS90CF386MTD
DS90CF366MTD
10108513
10108523
Applications Information
POWER SEQUENCING AND POWERDOWN MODE
The FPD Link chipset is designed to protect itself from
accidental loss of power to either the transmitter or receiver.
If power to the transmit board is lost, the receiver clocks
(input and output) stop. The data outputs (RxOUT) retain the
states they were in when the clocks stopped. When the
receiver board loses power, the receiver inputs are con-
trolled by a failsafe bias circuitry. The LVDS inputs are
High-Z during initial power on and power off conditions.
Current is limited (5 mA per input) by the fixed current mode
drivers, thus avoiding the potential for latchup when power-
ing the device.
Outputs of the transmitter remain in TRI-STATE until the
power supply reaches 2V. Clock and data outputs will begin
to toggle 10 ms after VCC has reached 3V and the Power-
down pin is above 1.5V. Either device may be placed into a
powerdown mode at any time by asserting the Powerdown
pin (active low). Total power dissipation for each device will
decrease to 5 µW (typical).
The transmitter input clock may be applied prior to powering
up and enabling the transmitter. The transmitter input clock
may also be applied after power up; however, the use of the
PWR DOWN pin is required as described in the Transmitter
Input Clock section. Do not power up and enable (PWR
DOWN = HIGH) the transmitter without a valid clock signal
applied to the TxCLK IN pin.
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14
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Dimensions shown in millimeters only
Order Number DS90CF386MTD
NS Package Number MTD56
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
Dimensions shown in millimeters only
Order Number DS90CF366MTD
NS Package Number MTD48
15
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
64 ball, 0.8mm fine pitch ball grid array (FBGA) Package
Dimensions show in millimeters
Order Number DS90CF386SLC
NS Package Number SLC64A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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